CN219499929U - Semiconductor memory - Google Patents

Abstract

A semiconductor memory includes a substrate, a plurality of bottom electrodes disposed on the substrate, and arranged in an array along a row direction and a column direction. The support layer is disposed on the substrate, directly contacts and supports each of the bottom electrodes. At least one first slit, at least one second slit and at least one third slit are defined in the supporting layer and extend along different directions respectively, and part of the side wall of the bottom electrode is exposed. The slit reduces structural collapse or crack caused by stress mismatch, and achieves the technical effect of improving the yield and reliability of the semiconductor memory.

Description

Semiconductor memory

Technical Field

The present utility model relates to a semiconductor memory, and more particularly, to a semiconductor memory having a stacked capacitor (stacked capacitor).

Background

The dynamic random access memory (dynamic random access memory, DRAM) is a volatile memory, and includes an array area (array area) formed of a plurality of memory cells (memory cells) and a peripheral area (peripheral area) formed of a control circuit. Each memory cell is composed of a transistor (transducer) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. Control circuitry controls access of data to each memory cell by addressing each memory cell through Word Lines (WL) and Bit Lines (BL) that span the array region and are electrically connected to each memory cell.

To reduce the size of memory cells to produce chips with higher density, the structure of memory cells has been advanced toward three-dimensional (three-dimensional) technology, such as using buried word line (word line) and stacked capacitors (stacked capacitor). The stacked capacitor is vertically arranged above the substrate, thereby saving the substrate area occupied by the capacitor and conveniently obtaining larger capacitance by increasing the height of the electrode plate of the capacitor. Along with the gradual increase of the storage capacity, the stacked capacitors are higher and higher in height and tighter in arrangement, so that the manufacturing difficulty is increased, and structural defects such as toppling or cracking are more likely to occur due to the influence of stress.

Disclosure of Invention

One of the objectives of the present utility model is to provide a semiconductor memory having a stacked capacitor (stacked capacitor).

An embodiment of the present utility model provides a semiconductor memory device including a substrate on which a plurality of bottom electrodes are disposed in an array along a row direction and a column direction, the row direction and the column direction being perpendicular to each other. One or more support layers are disposed on the substrate and directly contact and support each of the bottom electrodes. At least one first slit, at least one second slit and at least one third slit are defined in the same supporting layer, extend along different directions respectively, and partially expose the side walls of the bottom electrodes.

Another embodiment of the present utility model provides a semiconductor memory device including a substrate, a plurality of bottom electrodes disposed on the substrate and arranged in an array along a row direction and a column direction, wherein the row direction and the column direction are perpendicular to each other. One or more support layers are disposed on the substrate in direct contact with and supporting each of the bottom electrodes. At least one slit is defined in the support layer and extends to the edge of the support layer at two ends, wherein the extending direction of the slit is different from the row direction and the column direction.

The utility model is characterized in that the slit formed in the supporting layer can play a role in buffering stress on the stacked capacitor, reduce structural collapse or crack caused by stress mismatch, and achieve the technical effect of improving the yield and reliability of the semiconductor memory.

Drawings

The accompanying drawings provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 6 are views for explaining a method of manufacturing a semiconductor memory according to an embodiment of the present utility model, in which:

FIG. 1 is a schematic cross-sectional view of a semiconductor memory after forming a sacrificial layer and a support layer on a substrate;

FIG. 2 is a schematic plan view of a semiconductor memory after forming a bottom electrode;

FIG. 3 is a schematic cross-sectional view of the semiconductor memory device along the line A-A' shown in FIG. 2 after forming the bottom electrode;

fig. 4 is a schematic plan view of the semiconductor memory after forming openings and slits in the support layer;

FIG. 5 is a schematic cross-sectional view of the semiconductor memory device along the line A-A' shown in FIG. 4 after forming openings and slits in the support layer;

FIG. 6 is a schematic cross-sectional view of the semiconductor memory after the sacrificial layer is removed; and

fig. 7 is a schematic cross-sectional view of the semiconductor memory after forming a capacitor dielectric layer and a top electrode.

Fig. 8 to 12 are schematic plan views of a semiconductor memory according to some embodiments of the present utility model after forming openings and slits in a support layer.

FIG. 13 is a schematic plan view of a bottom electrode and opening arrangement in accordance with one embodiment of the present utility model.

Wherein reference numerals are as follows:

12. substrate and method for manufacturing the same

14. Interlayer dielectric layer

16. Storage node contact pad

18. Etching stop layer

20. Sacrificial layer

22. Support layer

24. Sacrificial layer

26. Support layer

26a block

30. Bottom electrode hole

31. Hexagonal shape

32. Cavity cavity

42. Extension wire

44. Extension wire

46. Extension wire

a1 First direction

a2 Second direction

a3 Third direction of

a4 Fourth direction

AA' tangent line

BE bottom electrode

S1 distance

D1 Direction of row

D2 Column direction

DL capacitance dielectric layer

OP opening

P1 center point

P2 center point

P3 intersection area

TE top electrode layer

TR1 slit

TR2 slit

TR3 slit

TR4 slit

Detailed Description

The following description of the preferred embodiments of the present utility model will be presented to enable those skilled in the art to which the utility model pertains and to further illustrate the utility model and its advantages. Those of skill in the art will be able to make substitutions, rearrangements, and combinations of features from several different embodiments to accomplish other embodiments without departing from the spirit of the utility model by referring to the following examples.

Referring to fig. 1 to 6, a method for manufacturing a semiconductor memory according to an embodiment of the utility model is described. First, as shown in fig. 1, a substrate 12 is provided, then an interlayer dielectric layer 14 and a storage node contact pad 16 disposed in the interlayer dielectric layer 14 are formed on the substrate 12, and then a stacked structure composed of stacks of different dielectric materials is formed on the interlayer dielectric layer 14. In this embodiment, the stacked structure may include, in order from bottom to top, an etch stop layer 18, a sacrificial layer 20 (also referred to as a lower sacrificial layer), a support layer 22 (also referred to as a lower support layer), a sacrificial layer 24 (also referred to as an upper sacrificial layer), and a support layer 26 (also referred to as an upper support layer). In some embodiments, sacrificial layer 20 and support layer 22 may be omitted and sacrificial layer 24 and support layer 26 may be formed directly on etch stop layer 18 and/or a sacrificial layer or hard mask layer (not shown) may be formed on support layer 26.

The substrate 12 may include, but is not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. Semiconductor devices and circuit structures, such as transistors, buried word lines, bit lines, may be provided in the substrate 12The contact plugs are not shown in the drawings for simplicity of illustration. The interlayer dielectric layer 14 is composed of a dielectric material, which may include silicon oxide (SiO ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials, or combinations thereof, but are not limited thereto. In accordance with an embodiment of the present utility model, interlayer dielectric layer 14 consists essentially of silicon nitride (SiN). The storage node contact pad 16 is formed of a conductive material, and suitable conductive materials may include, but are not limited to, metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and/or composite layers of the foregoing. According to an embodiment of the present utility model, the storage node contact pad 16 mainly comprises tungsten (W). The storage node contact pads 16 are equidistantly arranged in an array for electrically connecting the bottom electrode BE (refer to fig. 3) with the source/drain regions of the transistors of the memory cells provided in the substrate 12. The etching stop layer 18, the sacrificial layer 20, the supporting layer 22, the sacrificial layer 24, and the supporting layer 26 respectively comprise dielectric materials, and the dielectric materials having etching selectivity to the supporting layer 22 and the supporting layer 26 need to BE selected for the sacrificial layer 20 and the sacrificial layer 24, so that the sacrificial layer 20 and the sacrificial layer 24 can BE removed from the stacked structure by using a selective etching process, and the sidewalls of the bottom electrode BE are exposed by the cavity 32 (as shown in fig. 6). According to an embodiment of the present utility model, each of the sacrificial layer 20 and the sacrificial layer 24 may comprise an oxide (oxide) dielectric material, such as silicon oxide (SiO) ₂ ) Or boron phosphorus doped silicon glass (BPSG), but is not limited thereto. The support layer 22, the support layer 26, and the etch stop layer 18 may each include a nitride (nitride) dielectric material, such as silicon carbide nitride (SiCN) or silicon nitride (SiN), but are not limited thereto.

Referring to fig. 2 and 3, the stacked structure is etched to form a plurality of bottom electrode holes 30 penetrating the support layer 26, the sacrificial layer 24, the support layer 22, the sacrificial layer 20 and the etch stop layer 18, respectively, to expose the surfaces of the storage node contact pads 16. Then, a conductive material is filled into each bottom electrode hole 30 to form a bottom electrode BE. The bottom of the bottom electrode BE is in direct contact with and electrically connected to the storage node contact pad 16. The height of the bottom electrode BE is substantially determined by the overall thickness of the stacked structure. Conductive materials suitable for fabricating the bottom electrode BE may include metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and/or composite layers of the foregoing metal materials, but are not limited thereto. According to an embodiment of the present utility model, the bottom electrode BE is mainly composed of titanium (Ti).

As shown in fig. 2 and 3, the bottom electrodes BE are respectively in direct contact with and electrically connected to a storage node contact pad 16, and are arranged in an array along a row direction (row direction) D1 and a column direction (column direction) D2. The row direction D1 and the column direction D2 are perpendicular to each other. The bottom electrodes BE of adjacent rows are staggered in a zigzag (staggered) manner along the column direction D2, so that the bottom electrodes BE are arranged in an array in a hexagonal close arrangement as a whole. For ease of understanding, fig. 2 shows one of the hexagons 31. In more detail, referring to fig. 13, any one bottom electrode BE and six bottom electrodes BE surrounding the same are disposed at the center and the end points of the hexagon 31, respectively. The side length of the hexagon 31 is approximately equal to the distance S1 between the center points P1 of the adjacent bottom electrodes BE.

In this embodiment, the bottom electrode BE is formed along the bottom surface and the side wall of the bottom electrode hole 30 to have a hollow cylindrical (hollow cylindrical shape) structure. In other embodiments, the bottom electrode BE may have a solid cylindrical (pilar) structure and fill the bottom electrode hole 30.

Please refer to fig. 4 and 5, and refer to fig. 13 at the same time. Next, an etching process is performed on the support layer 26 to define a plurality of openings OP and slits TR1 and TR2 in the support layer 26. In some embodiments, as shown in fig. 4, the openings OP are substantially circular, and are respectively located between three adjacent bottom electrodes BE, and partially overlap the bottom electrodes BE, exposing a portion of the sidewalls of the bottom electrodes BE. In some embodiments, as shown in fig. 13, the extending lines 42, 44, and 46 from the center point P2 of the opening OP to the center point P1 of the three bottom electrodes BE overlapped therewith are substantially equal to each other, for example, about 120 degrees. In the embodiment shown in fig. 4, the extension lines 44 are substantially parallel to the row direction D1. In other embodiments of the present utility model, the opening OP may comprise other shapes, such as rectangular, oval, or closed loop, and is not limited to the embodiment shown in fig. 4.

As shown in fig. 4, the slits TR1 and TR2 extend between the bottom electrodes BE straight along the first and second directions a1 and a2, respectively, partially overlap the bottom electrodes BE to expose a portion of the sidewalls of the bottom electrodes BE, and are connected at an intersection region P3. The first direction a1 and the second direction a2 are different from the row direction D1 and the column direction D2, and include an included angle therebetween of more than 90 degrees (i.e., include an included angle between the slits TR1 and the slits TR2 of more than 90 degrees). In this embodiment, the first direction a1 and the second direction a2 are substantially parallel to adjacent sides of the hexagon 31, respectively, and include an included angle of about 120 degrees therebetween.

The lengths of the slits TR1 and TR2 can be adjusted as required. According to an embodiment of the present utility model, the slits TR1 and TR2 may respectively expose sidewalls (on the same side of the slits) of more than 10 bottom electrodes BE. According to an embodiment of the present utility model, at least one of the slits TR1 and TR2 (for example, the slit TR1 of fig. 4) may extend to pass through the entire support layer 26, and both ends thereof are aligned with the edges of the support layer 26.

The widths of the slits TR1 and TR2 need to BE controlled to BE not more than twice the distance S1 between the adjacent bottom electrodes BE in order to avoid the bottom electrodes BE from being completely surrounded by the slits TR1 or TR2 without being in contact with the support layer 26 and losing the support of the support layer 26. According to an embodiment of the utility model, the width of the slits TR1 and TR2 is approximately between 0.8 and 1.5 times the distance S1.

In some embodiments, the openings overlapping the slit passing paths may be selectively removed (in other words, the openings overlapping the slit are not formed in the support layer) to ensure that the bottom electrode exposed from the slit has a sufficient contact area with the support layer to be stably supported. For example, as shown in fig. 4, the openings OP overlapping the passage paths of the slits TR1 and TR2 are mostly removed, and are not formed in the support layer 26. In some embodiments, when the openings overlapping the slit pass-through path are all removed, the slit does not overlap or contact any of the openings.

In some embodiments, the openings in the slit pass path may be selectively left without causing insufficient bottom electrode support, and incorporated as part of the slit, forming a serrated slit (not shown).

Referring to fig. 5 and 6, the sacrificial layer 24 and the sacrificial layer 20 are then selectively etched and removed through the openings OP, the slits TR1 and the slits TR2 simultaneously, thereby forming horizontally extending cavities 32 between the support layer 26, the support layer 22 and the etch stop layer 18, exposing the sidewalls of the respective bottom electrodes BE. The selective etching process may include a plurality of etching steps, for example, a first step of removing the sacrificial layer 24 to expose a portion of the support layer 22, a second step of forming an opening in the support layer 22 to expose the sacrificial layer 20, and a third step of removing the remaining sacrificial layer 24 and the sacrificial layer 20.

Please refer to fig. 7. Next, a capacitor dielectric layer DL is formed along the exposed surfaces of the bottom electrode BE, the support layer 26, the support layer 22 and the etch stop layer 18, and then a top electrode layer TE is formed on the capacitor dielectric layer DL until the top electrode layer TE fills the remaining space of the cavity 32 and the bottom electrode hole 30, thereby obtaining a stacked capacitor. The capacitor dielectric layer DL is formed of a dielectric material, which may include silicon oxide (SiO ₂ ) Silicon nitride (SiN), or a high-k dielectric material, but is not limited thereto. The top electrode layer TE may comprise a conductive material, such as a metal, and suitable metals may include, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and/or composite layer of the foregoing. According to an embodiment of the present utility model, the top electrode layer TE is mainly composed of titanium (Ti). The process thus far obtains the semiconductor memory of the present utility model.

Referring to fig. 7 and 4 together, the semiconductor memory of the present utility model includes a substrate 12, and a plurality of bottom electrodes BE disposed on the substrate 12 and arranged in an array along a row direction (row direction) D1 and a column direction (column direction) D2. A support layer 26 is disposed on the substrate 12, directly contacting and supporting each bottom electrode BE. The support layer 26 defines a plurality of openings OP and slits TR1 and TR2 extending straight. The capacitive dielectric layer DL covers along the sidewalls of the bottom electrode BE and the surface of the support layer 26. The top electrode layer TE is located on the capacitive dielectric layer DL around the bottom electrode BE. In this embodiment, the top electrode layer TE is further filled into the cavity of the bottom electrode BE in the shape of hollow cylinder (hollow cylindrical shape), so as to increase the capacitive coupling area between the bottom electrode BE and the top electrode layer TE, thereby increasing the capacitance and improving the data retention time (data retention time) and reliability of the memory cell. The utility model can play a role of stress buffering for the stacked capacitor by forming the slits TR1 and the slits TR2 which extend along different directions in the supporting layer 26, reduce structural collapse or crack caused by stress mismatch, and improve the yield and reliability of the semiconductor memory. In some embodiments, the semiconductor memory further includes another support layer 22 located between the support layer 26 and the substrate 12. The support layer 22 directly contacts the sidewall of the middle portion of each bottom electrode BE to help support the bottom electrode BE. In some embodiments, the pattern of openings OP and slits TR1, TR2 of the support layer 26 is transferred into the support layer 22 by an etching process, forming corresponding openings and slits (not shown) in the support layer 22.

The extending direction, number and pattern of the slits of the supporting layer can be adjusted according to design requirements, and is not limited to the embodiment shown in fig. 4. The following description will be made with respect to different embodiments of the present utility model, and for simplicity of description, the following description mainly describes different parts of each embodiment, and the same parts will not be repeated. Like parts in the various embodiments of the present utility model are designated by like reference numerals to facilitate cross-reference to various embodiments.

Referring to fig. 8-12, schematic plan views of a semiconductor memory after patterning an upper support layer according to some embodiments of the utility model are shown. For simplicity of illustration, fig. 12 omits the structure of the opening of the upper support layer, the bottom electrode, and the like.

In the embodiment shown in fig. 8, the supporting layer 26 may include a plurality of openings OP, a slit TR1 extending along the first direction a1, a slit TR2 extending along the second direction a2, and a slit TR3 extending along the third direction a3, wherein the first direction a1, the second direction a2, and the third direction a3 are different directions, and the ends of the slit TR1, the slit TR2, and the slit TR3 are connected at the intersection region P3 to form a radiation pattern. Any two of the first direction a1, the second direction a2 and the third direction a3 include an included angle greater than 90 degrees therebetween (i.e., any two of the slits TR1, TR2 and TR2 include an included angle greater than 90 degrees therebetween). In this embodiment, the first direction a1 and the second direction a2 are substantially parallel to the adjacent two sides of the hexagon, the third direction a3 is substantially parallel to the column direction D2, and the first direction a1, the second direction a2 and the third direction a3 include an included angle of about 120 degrees.

In the embodiment shown in fig. 9, the supporting layer 26 may include a plurality of openings OP, a slit TR1 extending along the first direction a1, a slit TR2 extending along the second direction a2, and a slit TR3 extending along the third direction a3, wherein the first direction a1, the second direction a2, and the third direction a3 are different directions, and the ends of the slit TR1, the slit TR2, and the slit TR3 are connected at the intersection region P3 to form a radiation pattern. Unlike the embodiment of fig. 8, the first direction a1, the second direction a2, and the third direction a3 of the embodiment of fig. 9 are substantially parallel to the extension lines 42, 44, and 46, respectively, of fig. 13, and include an included angle of about 120 degrees with respect to each other. In some embodiments, the slit TR2 is substantially parallel to the row direction D1. In some embodiments, the slits TR1, TR2 and TR3 pass through the bottom electrodes BE along the connection lines of the center points of the bottom electrodes BE, respectively, exposing the sidewalls of the opposite sides of the bottom electrodes BE. In order to avoid the bottom electrodes BE being completely surrounded by the slits TR1, TR2 or TR3 and losing the support of the support layer 26, the width of the slits TR1, TR2 or TR3 of the present embodiment is preferably controlled to BE smaller than the diameter d2 of the bottom electrode BE.

In the embodiment shown in fig. 10, the supporting layer 26 may include a plurality of openings OP, a slit TR1 extending along the first direction a1, a slit TR2 extending along the second direction a2, and a slit TR3 extending along the third direction a3, wherein the first direction a1, the second direction a2, and the third direction a3 are different directions, and the slit TR1, the slit TR2, and the slit TR3 are connected at three intersecting regions P3 to form a closed pattern. The first direction a1, the second direction a2, and the third direction a3 are substantially parallel to the extension lines 42, 44, and 46, respectively, shown in fig. 13) and include an included angle of about 120 degrees with respect to each other. In some embodiments, the slits TR1, TR2 and TR3 pass through the bottom electrodes BE along the connection lines of the center points of the bottom electrodes BE, respectively, exposing the sidewalls of the opposite sides of the bottom electrodes BE. At least one of the slits TR1, TR2, and TR3 (e.g., the slit TR2 of fig. 10) may extend to traverse the entire support layer 26, with both ends being aligned with edges of the support layer 26.

In the embodiment shown in fig. 11, the support layer 26 may include a plurality of openings OP, and slits TR1, TR2, and TR3 extending along the first, second, and third directions a1, a2, and a3, respectively. The detailed descriptions of the slits TR1, TR2 and TR3 may refer to the description of the embodiment shown in fig. 9, and will not be repeated here. In the present embodiment, the support layer 26 further includes a slit TR4 extending along the fourth direction a4, wherein the fourth direction a4 is different from all of the first direction a1, the second direction a2, and the third direction a 3. In some embodiments, the fourth direction a4 is substantially parallel to one of the sides of the hexagon. The slit TR4 may be connected with at least one of the slits TR1, TR2, and TR3 (e.g., the slit TR 1) at the intersection region P3 to form another radiation pattern.

In some embodiments, the support layer 26 may include more slits extending in different directions, and the slits may be connected to form a mesh pattern. For example, as shown in fig. 12, the supporting layer 26 may include a plurality of slits TR1 extending along the first direction a1, a plurality of slits TR2 extending along the second direction a2, and a plurality of slits TR3 extending along the third direction a3, and the slits TR1, TR2, and TR3 are connected to each other to form a mesh pattern, dividing the supporting layer 26 into a plurality of blocks 26a separated from each other. The detailed descriptions of the slits TR1, TR2 and TR3 may refer to the description of the embodiment shown in fig. 8 or 9, and will not be repeated here. As shown in fig. 12, the slit TR1, the slit TR2 and the slit TR3 divide the support layer 26 into a plurality of blocks 26a separated from each other, wherein the shape and area of each block 26a are determined by the extending direction and length of the slit TR1, the slit TR2 and the slit TR3, and may have the same or different shapes and/or areas. In some embodiments, the blocks 26a are each hexagonal, but are not limited thereto.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (11)

1. A semiconductor memory device, comprising:

a substrate;

a plurality of bottom electrodes disposed on the substrate and arranged in an array along a row direction and a column direction, the row direction and the column direction being perpendicular to each other;

one or more support layers disposed on the substrate, in direct contact with and supporting each of the bottom electrodes; and

at least one first slit, at least one second slit and at least one third slit are defined in the same supporting layer, extend along different directions respectively, and partially expose the side walls of the bottom electrodes.

2. The semiconductor memory of claim 1, wherein the first slit, the second slit, and the third slit are connected to form a closed pattern.

3. The semiconductor memory of claim 1, wherein the first slit, the second slit, and the third slit are connected to form a radiation pattern.

4. The semiconductor memory according to claim 1, wherein one of the first slit, the second slit, and the third slit extends along the row direction or the column direction.

5. The semiconductor memory according to claim 4, wherein an extending direction of any two of the first slit, the second slit, and the third slit includes an included angle greater than 90 degrees.

6. The semiconductor memory of claim 1, further comprising at least a fourth slit extending along a fourth direction different from the first slit, the second slit, and the third slit.

7. The semiconductor memory of claim 1, wherein the support layer includes a plurality of the first slits, a plurality of the second slits, and a plurality of the third slits, which are connected to form a mesh pattern.

8. The semiconductor memory according to claim 1, wherein the first slit, the second slit, and the third slit each expose more than 10 sidewalls of the bottom electrode.

9. The semiconductor memory according to claim 1, further comprising:

and a plurality of openings defined in the support layer and respectively positioned between three adjacent bottom electrodes to expose part of the side walls of the bottom electrodes.

10. The semiconductor memory according to claim 1, further comprising:

the capacitor dielectric layer is covered on the bottom electrode and the supporting layer; and

and the top electrode layer is covered on the capacitance dielectric layer.

11. A semiconductor memory device, comprising:

a substrate;

a plurality of bottom electrodes disposed on the substrate and arranged in an array along a row direction and a column direction, wherein the row direction and the column direction are perpendicular to each other;

one or more support layers disposed on the substrate, in direct contact with and supporting each of the bottom electrodes; and

at least one slit is defined in the support layer and extends to the edge of the support layer at two ends, wherein the extending direction of the slit is different from the row direction and the column direction.