CN220106515U - High-voltage-resistant package for SOT89 product - Google Patents
High-voltage-resistant package for SOT89 product Download PDFInfo
- Publication number
- CN220106515U CN220106515U CN202321640652.2U CN202321640652U CN220106515U CN 220106515 U CN220106515 U CN 220106515U CN 202321640652 U CN202321640652 U CN 202321640652U CN 220106515 U CN220106515 U CN 220106515U
- Authority
- CN
- China
- Prior art keywords
- chip
- product
- bonding material
- sot89
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 claims abstract description 20
- 238000005192 partition Methods 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 2
- 238000010276 construction Methods 0.000 claims 2
- 238000000926 separation method Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 239000007787 solid Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
The utility model discloses a high-pressure-resistant package for an SOT89 product, which relates to the technical field of chip packaging and comprises a frame structure and a chip, wherein the chip is combined on the frame structure through a bonding material, a resin packaging structure is arranged outside the chip, a partition interval is arranged between the chip and an IN end pin of the chip on the frame structure, and the resin packaging structure is filled IN the partition interval. According to the utility model, the copper material of the IN-end pin of the product is separated from the chip by the separation interval, the resin packaging structure after packaging forms a solid structure at the position, so that the strength is increased, the high-pressure-resistant packaging product is realized, the separation distance of the separation interval can be designed to be tens of um-thousands um according to requirements, and meanwhile, the chip is separated from the IN-end pin, and the chip originally using the insulating bonding material can be adhered to the base island by adopting the conductive bonding material, so that the heat conducting performance of the product is improved.
Description
Technical Field
The utility model relates to the technical field of chip packaging, in particular to high-voltage-resistant packaging for SOT89 products.
Background
The package for mounting semiconductor integrated circuit chip has functions of placing, fixing, sealing, protecting chip and enhancing electrothermal property, and the bridge-chip connection point for communicating the internal world of chip with external circuit is connected to pins of package by means of wire, and these pins are connected with other devices by means of wire on the printed board. Therefore, packaging plays an important role for both CPU and other LSI integrated circuits.
In the prior art, a part of SOT89 packaged products (such as a schematic diagram before improvement) must be designed with middle pins as input driving pins due to reasons such as inter-board limitation, high voltage is required for driving a chip to work, the chip is electrically isolated by using insulating bonding materials with a thickness of several to tens of microns, and when the insulating bonding materials are unevenly distributed, the bonding materials are broken down due to high voltage caused by the occurrence of cavities in the bonding materials, the doping of foreign impurities and the like, so that the chip is burnt.
Disclosure of Invention
The object of the present utility model is to provide a high pressure package for SOT89 products, which solves the above-mentioned drawbacks of the prior art.
The utility model provides the following technical scheme: the high pressure resistant package for the SOT89 product comprises a frame structure and a chip, wherein the chip is combined on the frame structure through a bonding material, a resin packaging structure is arranged outside the chip, a partition interval is arranged between the chip and an IN-end pin of the chip on the frame structure, and the resin packaging structure is filled into the partition interval.
Preferably, the bonding material is of a heat-conducting material structure, so that the chip is adhered to the base island of the frame structure, and the heat-conducting performance of the product is improved.
Preferably, the side of the frame structure facing away from the chip is provided with an LF coating.
In the technical scheme, the utility model has the technical effects and advantages that:
according to the utility model, the copper material of the IN-end pin of the product is separated from the chip by the separation interval, the resin packaging structure after packaging forms a solid structure at the position, so that the strength is increased, the high-pressure-resistant packaging product is realized, the separation distance of the separation interval can be designed to be tens of um-thousands um according to requirements, and meanwhile, the chip is separated from the IN-end pin, and the chip originally using the insulating bonding material can be adhered to the base island by adopting the conductive bonding material, so that the heat conducting performance of the product is improved.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required to be used in the embodiments will be briefly described below.
Fig. 1 is a cross-sectional view of a package structure of the present utility model.
Fig. 2 is a schematic structural view of the present utility model.
Fig. 3 is an enlarged view of the structure of the portion a of fig. 1 according to the present utility model.
Fig. 4 is a schematic view of the POD of the present utility model.
Fig. 5 is a cross-sectional view of a package structure of a conventional product.
Fig. 6 is a schematic structural diagram of a conventional product.
Fig. 7 is a schematic diagram of a POD of a prior art product.
Reference numerals illustrate:
1. a frame structure; 2. a chip; 3. a resin encapsulation structure; 4. a bonding material; 5. a partition section; 6. LF plating.
Detailed Description
The utility model provides a high-pressure-resistant package for SOT89 products, which is shown IN figures 1-4, and comprises a frame structure 1 and a chip 2, wherein the chip 2 is combined on the frame structure 1 through a bonding material 4, a resin packaging structure 3 is arranged outside the chip 2, a partition interval 5 is arranged between the chip 2 and an IN-end pin of the chip 1 on the frame structure 1, and the resin packaging structure 3 is filled IN the partition interval 5.
Furthermore, IN the above technical scheme, the bonding material 4 is of a heat conducting material structure, and the bonding material 4 IN the traditional product is mostly an insulating bonding material, and after the improvement of the utility model, the chip 2 is separated from the IN-end pin, and the original insulating bonding material can be adhered to the base island by adopting the conductive bonding material, so that the heat conducting performance of the product is improved.
Further, in the above technical solution, the side of the frame structure 1 facing away from the chip 2 is provided with the LF plating layer 6.
Working principle: if fig. 1 to 4 are shown, a partition section 5 is arranged between the copper material of the IN-end pin of the product and the chip 2 for partition, (the partition is not limited to the schematic mode and materials, any plane and three-dimensional structure for realizing the electrical property isolation are IN the patent protection scope), the chip 2 is positioned at one side of the partition section 5, the IN-end pin of the chip is input and connected at the other side of the partition section 5, the packaged resin packaging structure 3 forms a solid structure at the position, the strength is increased, the high-pressure-resistant SOT89 packaging product is realized, the partition distance of the partition section 5 can be designed to be tens of um to thousands um as required, and meanwhile, the chip originally using the insulating bonding material can be bonded with a base island by adopting the conductive bonding material due to the partition of the chip and the IN-end pin, so that the heat conducting property of the product is improved.
Claims (3)
1. The utility model provides a high withstand voltage encapsulation to SOT89 product, includes frame construction (1) and chip (2), chip (2) are combined on frame construction (1) through bonding material (4), chip (2) are provided with resin packaging structure (3) outward, its characterized in that: and a partition interval (5) is arranged between the chip (2) and the IN-end pin of the chip on the frame structure (1), and the resin packaging structure (3) is filled into the partition interval (5).
2. A high pressure package for SOT89 products according to claim 1, characterized in that: the bonding material (4) is of a heat conducting material structure.
3. A high pressure package for SOT89 products according to claim 1, characterized in that: one side of the frame structure (1) deviating from the chip (2) is provided with an LF plating layer (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321640652.2U CN220106515U (en) | 2023-06-27 | 2023-06-27 | High-voltage-resistant package for SOT89 product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321640652.2U CN220106515U (en) | 2023-06-27 | 2023-06-27 | High-voltage-resistant package for SOT89 product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220106515U true CN220106515U (en) | 2023-11-28 |
Family
ID=88846153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321640652.2U Active CN220106515U (en) | 2023-06-27 | 2023-06-27 | High-voltage-resistant package for SOT89 product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220106515U (en) |
-
2023
- 2023-06-27 CN CN202321640652.2U patent/CN220106515U/en active Active
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