CN220019786U - High-efficiency testing device for improving coverage rate of circuit board - Google Patents
High-efficiency testing device for improving coverage rate of circuit board Download PDFInfo
- Publication number
- CN220019786U CN220019786U CN202222611291.0U CN202222611291U CN220019786U CN 220019786 U CN220019786 U CN 220019786U CN 202222611291 U CN202222611291 U CN 202222611291U CN 220019786 U CN220019786 U CN 220019786U
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- China
- Prior art keywords
- circuit board
- carrier plate
- upper cover
- thimble
- connecting hole
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- 238000012360 testing method Methods 0.000 title claims abstract description 30
- 230000003139 buffering effect Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Abstract
The high-efficiency testing device for improving the coverage rate of the circuit board comprises a base, wherein the upper surface of the base is provided with a thimble placing groove, a spring is arranged at the corner, the lower bottom surface of the thimble placing groove is provided with a testing thimble, and a first upper cover connecting hole and a carrier plate connecting hole are respectively arranged at the sides of the spring; according to the utility model, the upper cover is pressed down to act on the upper surface of the carrier plate, the carrier plate is sunk down to play a certain buffering role under the influence of the springs, so that the circuit board is fully contacted with the test thimble, and the test operation is carried out on different kinds of products in the mode, and the products are fully contacted with the test thimble, so that the beneficial effects of ensuring the operation quality and improving the operation efficiency are achieved.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to a high-efficiency testing device for improving coverage rate of a circuit board.
Background
At present, a single-mode test mode is generally adopted in the market to test a product, if a plurality of products are required to be tested simultaneously, a plurality of independent jigs and operation equipment are required to be used for testing the products, and by the mode, labor cost is required to be increased, a plurality of operation equipment is required to be additionally arranged, so that the problems of wasting operation time and improving operation cost are caused.
Disclosure of Invention
In order to solve the problems, the utility model provides a high-efficiency testing device for improving the coverage rate of a circuit board.
The technical scheme adopted for solving the technical problems is as follows: the utility model provides an improve high-efficient testing arrangement of circuit board coverage rate, includes base, its characterized in that: the base upper surface is equipped with the thimble standing groove, and the corner is equipped with the spring, the bottom surface is equipped with the test thimble under the thimble standing groove, the spring side is equipped with first upper cover connecting hole and carrier plate connecting hole respectively, and the carrier plate upper surface is equipped with the circuit board standing groove, and bottom surface corner is equipped with the carrier plate reference column down, the circuit board standing groove bottom surface is equipped with the thimble groove, and both sides are located carrier plate upper surface symmetry and are equipped with the stopper, carrier plate upper surface is located carrier plate reference column side and is equipped with the second upper cover connecting hole, the carrier plate passes through carrier plate reference column and carrier plate connecting hole and splices each other and connect, circuit board standing groove and thimble standing groove are in same vertical line, and the upper cover bottom surface is equipped with the upper cover reference column down to pass second upper cover connecting hole and first upper cover connecting hole and splice each other and connect.
Further, 1-4 thimble placing grooves are formed in the upper surface of the base, and 1-4 circuit board placing grooves are formed in the upper surface of the carrier plate.
Further, 4-8 springs are arranged on the upper surface of the base.
Further, 4-8 upper cover positioning columns are arranged on the lower bottom surface of the upper cover, 4-8 first upper cover connecting holes are formed in the upper surface of the base, and 4-8 second upper cover connecting holes are formed in the upper surface of the carrier plate.
Further, 4-8 carrier plate positioning columns are arranged on the lower bottom surface of the carrier plate, and 4-8 carrier plate connecting holes are formed in the upper surface of the base.
Further, 2-6 thimble grooves are arranged on the lower bottom surface of the circuit board placing groove.
The beneficial effects of the utility model are as follows: according to the utility model, a plurality of circuit boards are placed in the circuit board placing groove, then the upper cover is pressed down to act on the upper surface of the carrier plate, the carrier plate is sunk down to be influenced by the springs to play a certain buffering role, so that the circuit board is in full contact with the test thimble, and the test operation is performed on different kinds of products in the way, and the products are in full contact with the test thimble, so that the problem of bad conditions in the test operation process is effectively avoided, the operation quality is ensured, and the operation efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a front view structure according to an embodiment of the present utility model;
FIG. 2 is a schematic top view of a carrier plate according to an embodiment of the utility model;
fig. 3 is a schematic top view of a base according to an embodiment of the utility model.
Reference numerals: base 1, carrier plate 2, upper cover 3, first upper cover connecting hole 11, carrier plate connecting hole 12, spring 13, thimble standing groove 14, test thimble 15, circuit board standing groove 21, stopper 22, thimble groove 23, second upper cover connecting hole 24, carrier plate reference column 25, upper cover reference column 31.
Detailed Description
In order to make the technical scheme of the utility model more clear, the utility model is further described below by referring to the specific embodiments in the drawings.
As shown in fig. 1-3, the high-efficiency testing device for improving coverage rate of a circuit board according to the embodiment of the utility model comprises a base 1, wherein an ejector pin placing groove 14 is arranged on the upper surface of the base 1, a spring 13 is arranged at a corner, a test ejector pin 15 is arranged on the lower bottom surface of the ejector pin placing groove 14, a first upper cover connecting hole 11 and a carrier plate connecting hole 12 are respectively arranged on the side of the spring 13, a circuit board placing groove 21 is arranged on the upper surface of the carrier plate 2, a carrier plate positioning column 25 is arranged at the corner of the lower bottom surface, an ejector pin groove 23 is arranged on the lower bottom surface of the circuit board placing groove 21, limit blocks 22 are symmetrically arranged on the upper surface of the carrier plate 2 at two sides, a second upper cover connecting hole 24 is arranged on the upper surface of the carrier plate 2 and is connected with the carrier plate connecting hole 12 in a splicing manner, the circuit board placing groove 21 and the ejector pin placing groove 14 are arranged on the same vertical line, an upper cover positioning column 31 is arranged on the lower bottom surface of the upper cover 3 and is connected with the first upper cover connecting hole 11 in a splicing manner through the second upper cover connecting hole 24.
Further, 1-4 thimble placing grooves 14 are formed in the upper surface of the base 1, and 1-4 circuit board placing grooves 21 are formed in the upper surface of the carrier plate 2.
Further, 4-8 springs 13 are arranged on the upper surface of the base 1.
Further, 4-8 upper cover positioning columns 31 are arranged on the lower bottom surface of the upper cover 3, 4-8 first upper cover connecting holes 11 are arranged on the upper surface of the base 1, and 4-8 second upper cover connecting holes 24 are arranged on the upper surface of the carrier plate 2.
Further, 4-8 carrier plate positioning columns 25 are arranged on the lower bottom surface of the carrier plate 2, and 4-8 carrier plate connecting holes 12 are arranged on the upper surface of the base 1.
Further, 2-6 thimble grooves 23 are arranged on the lower bottom surface of the circuit board placing groove 21.
As shown in fig. 1-3, when the utility model is required to be used for testing circuit board products, the utility model is firstly connected with operation equipment, then a plurality of circuit boards are put into the circuit board placing groove 21, and the upper cover positioning column 31 passes through the second upper cover connecting hole 24 to be connected with the first upper cover connecting hole 11, so that the upper cover 3 acts on the upper surface of the carrier plate 2, then the operation equipment applies a pressurizing force to the upper cover 3 to act on the carrier plate 2, and the spring 13 plays a certain buffering role on the carrier plate 2 in the sinking process under the influence of the pressure, so that the lower bottom surface of the upper cover 3 is attached to the circuit board products, and further the circuit board products are attached to the test thimble 15.
The above embodiments may be combined with each other without being opposed to each other, and further implemented.
The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical scheme of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.
Claims (6)
1. The utility model provides an improve high-efficient testing arrangement of circuit board coverage rate, includes base (1), its characterized in that: the upper surface of the base (1) is provided with a thimble placing groove (14), the corners are provided with springs (13), the lower bottom surface of the thimble placing groove (14) is provided with test thimbles (15), the sides of the springs (13) are respectively provided with a first upper cover connecting hole (11) and a carrier plate connecting hole (12), the upper surface of the carrier plate (2) is provided with a circuit board placing groove (21), the corners of the lower bottom surface are provided with carrier plate positioning columns (25), the lower bottom surface of the circuit board placing groove (21) is provided with thimble grooves (23), two sides of the thimble placing groove are symmetrically provided with limiting blocks (22) on the upper surface of the carrier plate (2), the support plate (2) upper surface is located support plate reference column (25) side and is equipped with second upper cover connecting hole (24), support plate (2) are connected with support plate connecting hole (12) through support plate reference column (25) concatenation each other, circuit board standing groove (21) and thimble standing groove (14) are in same vertical line, and the lower bottom surface of upper cover (3) is equipped with upper cover reference column (31) to pass second upper cover connecting hole (24) and first upper cover connecting hole (11) concatenation each other and connect.
2. The high-efficiency test device for improving coverage of a circuit board according to claim 1, wherein: 1-4 thimble placing grooves (14) are formed in the upper surface of the base (1), and 1-4 circuit board placing grooves (21) are formed in the upper surface of the carrier plate (2).
3. The high-efficiency test device for improving coverage of a circuit board according to claim 1, wherein: 4-8 springs (13) are arranged on the upper surface of the base (1).
4. The high-efficiency test device for improving coverage of a circuit board according to claim 1, wherein: the lower bottom surface of the upper cover (3) is provided with 4-8 upper cover positioning columns (31), the upper surface of the base (1) is provided with 4-8 first upper cover connecting holes (11), and the upper surface of the carrier plate (2) is provided with 4-8 second upper cover connecting holes (24).
5. The high-efficiency test device for improving coverage of a circuit board according to claim 1, wherein: 4-8 carrier plate positioning columns (25) are arranged on the lower bottom surface of the carrier plate (2), and 4-8 carrier plate connecting holes (12) are formed in the upper surface of the base (1).
6. The high-efficiency test device for improving coverage of a circuit board according to claim 1, wherein: 2-6 thimble grooves (23) are formed in the lower bottom surface of the circuit board placing groove (21).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222611291.0U CN220019786U (en) | 2022-09-30 | 2022-09-30 | High-efficiency testing device for improving coverage rate of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222611291.0U CN220019786U (en) | 2022-09-30 | 2022-09-30 | High-efficiency testing device for improving coverage rate of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220019786U true CN220019786U (en) | 2023-11-14 |
Family
ID=88670017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222611291.0U Active CN220019786U (en) | 2022-09-30 | 2022-09-30 | High-efficiency testing device for improving coverage rate of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220019786U (en) |
-
2022
- 2022-09-30 CN CN202222611291.0U patent/CN220019786U/en active Active
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| GR01 | Patent grant |