CN219998245U - Semiconductor structure - Google Patents

Abstract

The utility model relates to a semiconductor structure comprising: the light-emitting chip comprises a plurality of light-emitting chips and a first dielectric layer, wherein the light-emitting chips comprise an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer which are sequentially formed, and the first dielectric layer covers the light-emitting chips; the first electrode is positioned in the first dielectric layer and connected with the P-type semiconductor layer; the driving substrate is bonded with the light-emitting chip through the first dielectric layer and the first electrode; and the second electrode is positioned on one side of the first dielectric layer far away from the driving substrate and is electrically connected with the N-type semiconductor layer. The luminous efficiency is improved by the bonding mode that the first dielectric layer and the first electrode are bonded to the driving substrate. In addition, by filling the electrode grooves and forming the first electrode and forming the second electrode on the surface of the first dielectric layer far away from the driving substrate, the effect that each light emitting chip comprises an independent anode and adjacent light emitting chips share a cathode is achieved.

Description

Semiconductor structure

Technical Field

The present utility model relates to the field of integrated circuits, and in particular, to a semiconductor structure.

Background

The light-emitting chip is a commonly used light-emitting device, and has wide application in the field of illumination. The light emitting chip can efficiently convert electric energy into light energy, and has wide application in modern society, such as illumination, flat panel display, medical devices and the like.

With the continuous progress of technology, light emitting chips have been widely used in the fields of displays, lighting, and the like, and thus, higher demands are being made on the light emitting efficiency of the light emitting chips.

Disclosure of Invention

Based on this, it is necessary to provide a semiconductor structure against the problem of low light emitting efficiency of the light emitting chip in the related art.

In order to achieve the above object, the present utility model provides a semiconductor structure comprising:

the light-emitting chips comprise an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer which are sequentially formed;

a first dielectric layer covering the light emitting chip;

the first electrode is positioned in the first dielectric layer and connected with the P-type semiconductor layer;

a driving substrate bonded to the first dielectric layer and the first electrode;

and the second electrode is positioned on one side of the first dielectric layer far away from the driving substrate and is electrically connected with the N-type semiconductor layer.

In one embodiment, the semiconductor structure includes:

and the first current diffusion layer is positioned on the P-type semiconductor layer.

In one embodiment, the semiconductor structure includes:

and the etching barrier layer is positioned on the first current diffusion layer.

In one embodiment, the semiconductor structure includes:

and a growth blocking layer positioned between the first electrode and the first dielectric layer.

In one embodiment, adjacent ones of the light emitting chips are spaced apart.

In one embodiment, the semiconductor structure includes:

and the second current diffusion layer is positioned on the surface of the first dielectric layer close to the N-type semiconductor layer and the surface of the N-type semiconductor layer.

In one embodiment, the second electrode is electrically connected to the second current diffusion layer between adjacent N-type semiconductor layers.

In one embodiment, the second electrode is located on the second current diffusion layer between adjacent N-type semiconductor layers.

In one embodiment, the driving substrate includes:

the driving electrode is positioned in the second dielectric layer; the driving electrode is bonded with the first electrode, and the second dielectric layer is bonded with the first dielectric layer.

In one embodiment, the material of the first electrode comprises copper.

In the semiconductor structure, the first electrode is arranged in the first dielectric layer, the second electrode is arranged on the second current diffusion layer between the adjacent N-type semiconductor layers, the first dielectric layer and the first electrode are bonded to the driving substrate, and the driving substrate can drive the light emitting chip to emit light, so that the light emitting efficiency of the light emitting chip is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present utility model, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;

FIG. 2 is a schematic diagram of a chip substrate structure according to an embodiment;

FIG. 3 is a top view of a chip substrate provided in one embodiment;

FIG. 4 is a schematic diagram of a first dielectric layer according to one embodiment;

FIG. 5 is a top view of an electrode recess provided in one embodiment;

FIG. 6 is a schematic diagram of a first electrode provided in an embodiment;

FIG. 7 is a schematic diagram of removing a first substrate provided in one embodiment;

FIG. 8 is a schematic diagram of a second electrode provided in an embodiment;

fig. 9 is a top view of a second electrode provided in an embodiment.

Reference numerals illustrate: 100-chip substrate; 110-a first substrate; 120-a light emitting chip; a 120-a-N type semiconductor layer; 120-b-a light emitting layer; a 120-c-P type semiconductor layer; 130-a first current spreading layer; 140-etching the barrier layer; 150-a first dielectric layer; 160-electrode grooves; 170-a first electrode; 180-a second electrode; 200-driving a substrate; 210-a second substrate; 220-driving a chip; 230-a second dielectric layer; 240-drive electrode.

Detailed Description

In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Embodiments of the utility model are illustrated in the accompanying drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" another element or layer, it can be directly on, adjacent to, connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present utility model.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the utility model are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the utility model, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present utility model should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the utility model.

In one embodiment, referring to fig. 1, the present utility model provides a method for preparing a semiconductor structure, which includes the following steps:

step S100: providing a chip substrate 100; the chip substrate 100 includes a first substrate 110 and a plurality of light emitting chips 120, and the light emitting chips 120 include an N-type semiconductor layer 120-a, a light emitting layer 120-b, and a P-type semiconductor layer 120-c formed in this order.

Step S300: a first dielectric layer 150 is formed on the substrate and the light emitting chip 120.

Step S400: the first dielectric layer 150 is etched to the P-type semiconductor layer 120-c to form an electrode recess 160.

Step S500: the electrode groove 160 is filled, and the first electrode 170 is formed.

Step S600: the driving substrate 200 is provided, and the first dielectric layer 150 and the first electrode 170 are bonded to the driving substrate 200.

Step S700: the first substrate 110 is removed, and a second electrode 180 is formed on a surface of the first dielectric layer 150 away from the driving substrate 200.

Referring to fig. 2, in step S100, the first substrate 110 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the first substrate 110 may include a substrate such as a silicon substrate, a silicon germanium carbon substrate, a silicon carbide substrate, a gallium arsenide substrate, an indium phosphide substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate may comprise a layered substrate such as Si/SiGe, si/SiC, silicon-on-insulator, or silicon-germanium-on-insulator, for example.

The N-type semiconductor layer 120-a, the light emitting layer 120-b, and the P-type semiconductor layer 120-c may be sequentially formed on the first substrate 110. As an example, the N-type semiconductor layer 120-a may include an N-type GaN layer, the light emitting layer 120-b may include a MOW layer, and the P-type semiconductor layer 120-c may include a P-type GaN layer. Of course, a film layer such as a buffer layer or a confinement layer may be formed over the first substrate 110.

After the N-type semiconductor layer 120-a, the light emitting layer 120-b, and the P-type semiconductor layer 120-c are sequentially formed on the first substrate 110, each film layer may be etched from the P-type semiconductor layer 120-c to the first substrate 110 to form a plurality of light emitting chips 120 arranged at intervals. Referring to fig. 2, the distance a between adjacent light emitting chips 120 is greater than 0. The number of the light emitting chips 120 included on the first substrate 110 is not particularly limited in this embodiment.

As an example, referring to fig. 3, the light emitting chip 120 may have a mesa structure in the X direction. Of course, the mesa structure is only an exemplary structure, and the light emitting chip 120 may include other shapes. For example, cylindrical. When energized, the light emitting chip 120 may be lit to emit light of a specified color. For example, the light emitting chip 120 may emit red, blue, or green light.

Specifically, dry etching may be used when etching each of the film layers from the P-type semiconductor layer 120-c to the first substrate 110. As an example, the dry etching may include at least any one of reactive ion etching, inductively coupled plasma etching, or high-concentration plasma etching.

Referring to fig. 4, in step S300, the first dielectric layer 150 may be used to form the electrode recess 160 in a subsequent step. Specifically, the first dielectric layer 150 may be formed using a plasma enhanced chemical vapor deposition method. The material of the first dielectric layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the first dielectric layer 150 is formed, the surface of the first dielectric layer 150 may be polished by using a chemical mechanical polishing method, so that the surface of the first dielectric layer 150 is smoother, which is beneficial to the subsequent preparation process. Specifically, when a chemical mechanical polishing method is used, an acidic polishing liquid having polishing particles with a certain particle size can be used.

Referring to fig. 4, in step S400, the electrode recess 160 may be formed by etching the first dielectric layer 150 to the P-type semiconductor layer 120-c using a dry method or a wet method. The electrode groove 160 forms the first electrode 170 in a subsequent step. Referring to fig. 5, in the X direction, the electrode recess 160 exposes the P-type semiconductor layer 120-c. As an example, the dry etching may include at least any one of reactive ion etching, inductively coupled plasma etching, or high-concentration plasma etching.

Referring to fig. 6, in step S500, the first electrode 170 may be formed using a damascene process, as an example. For example, the first electrode 170 may be formed using an electrochemical plating method using electrode metal to fill the electrode recess 160. The electrode metal may include cobalt, nickel, titanium, tungsten, tantalum titanate, tungsten nitride, copper, aluminum, and the like. Since the first electrode 170 is electrically connected to the P-type semiconductor layer 120-c, the first electrode 170 is an anode.

After filling the electrode recess 160, the electrode metal may be planarized using a chemical mechanical polishing process such that the surface of the first electrode 170 is flush with the surface of the first dielectric layer 150.

Referring to fig. 5, since the electrode grooves 160 form the communicating grooves on the first dielectric layer 150, when each electrode groove 160 is filled with electrode metal, the first electrodes 170 are communicated to form a mesh structure. In the case where one of the first electrodes 170 has a voltage, the connected first electrodes 170 may cause the other first electrodes 170 to also have a voltage.

Referring to fig. 7, in step S600, the driving substrate 200 may include a driving chip 220 and a second substrate 210, and the driving chip 220 is formed on the second substrate 210.

Specifically, the first dielectric layer 150 and the first electrode 170 may be bonded to the driving substrate 200 in a hybrid bonding manner.

Referring to fig. 8, in step S700, the first substrate 110 may be removed by polishing. Since the first substrate 110 may be opaque, removing the opaque first substrate 110 may improve the light emitting efficiency of the light emitting chip 120. At this time, the light emitting device fabricated from the semiconductor structure has a vertical structure.

Referring to fig. 8 and 9, the second electrode 180 is electrically connected to the N-type semiconductor layer 120-a, and thus the second electrode 180 is a cathode.

In the above embodiment, by forming the first dielectric layer 150 on the substrate and the light emitting chip 120, etching the first dielectric layer 150 to the P-type semiconductor layer 120-c, forming the electrode groove 160, filling the electrode groove 160 and forming the first electrode 170, and bonding the first dielectric layer 150 and the first electrode 170 to the driving substrate 200, and removing the first substrate 110, the second electrode 180 is formed on the surface of the first dielectric layer 150 away from the driving substrate 200, so that the driving substrate 200 can emit light by driving the first electrode 170 and the second electrode 180, and the light emitting chip 120 is achieved. And the light emitting efficiency is improved by the bonding manner in which the first dielectric layer 150 and the first electrode 170 are bonded to the driving substrate 200. In addition, by filling the electrode grooves 160 and forming the first electrode 170 and forming the second electrode 180 on the surface of the first dielectric layer 150 far from the driving substrate 200, the effect that each light emitting chip 120 includes a single anode and adjacent light emitting chips 120 share a cathode is achieved

The display panel prepared by the semiconductor structure has lower power consumption, can save electric energy and prolongs the service life of the display panel. In addition, the chip substrate 100 is preferably bonded to the driving backplate 200 by hybrid bonding, so that the light emitting performance can be further improved.

In one embodiment, prior to step S300, it includes:

step S200: a first current diffusion layer 130 is formed on the P-type semiconductor layer 120-c.

Step S210: an etch stopper 140 is formed on the first current spreading layer 130.

Referring to fig. 2, in step S200, the first current diffusion layer 130 is configured to diffuse the received current onto the P-type semiconductor layer 120-c, so as to facilitate improving the light emitting efficiency of the light emitting chip 120. As an example, electron beam evaporation or other means may be used to grow the entire first current spreading layer 130 on the P-type semiconductor layer 120-c. The material of the first current diffusion layer 130 may include indium tin oxide, nickel, platinum, or other metals that may form good ohmic contact with the P-type semiconductor layer 120-c.

Of course, an annealing process may be performed after the first current diffusion layer 130 is formed on the P-type semiconductor layer 120-c.

In step S210, the etch stopper 140 may be produced on the first current spreading layer 130 using a plasma enhanced chemical vapor deposition method. The etch stopper 140 may prevent over-etching when the electrode groove 160 is formed by subsequent etching, and protect the first current diffusion layer 130 and the light emitting chip 120. As an example, the material of the etch stop layer 140 may include silicon nitride.

In one embodiment, the drive substrate 200 includes a second dielectric layer 230 and a drive electrode 240. In step S600, it includes:

step S610: the driving electrode 240 is bonded to the first electrode 170, and the second dielectric layer 230 is bonded to the first dielectric layer 150.

Referring to fig. 7, the second dielectric layer 230 is disposed on the driving chip 220, and the driving electrode 240 is disposed in the second dielectric layer 230. The material of the driving electrode 240 may include indium tin oxide, indium zinc oxide, or a nano-sized transparent conductive material.

In step S610, when bonding the driving electrode 240 and the chip substrate 100, a hybrid bonding method may be used. For example, the driving electrode 240 and the first electrode 170 are bonded, respectively, and the second dielectric layer 230 and the first dielectric layer 150, such that the driving chip 220 may apply a voltage to the light emitting chip 120 through the driving electrode 240.

When the driving chip 220 drives the light emitting chip 120 to emit light, the side of the N-type semiconductor layer 120-a may be a light emitting side, i.e., light is mainly emitted from the side of the N-type semiconductor layer 120-a.

When the semiconductor structure is prepared as a display panel, a flip-chip packaging method may be used.

In one embodiment, in step S700, it includes:

step S710: the first substrate 110 is removed.

Step S720: a second current diffusion layer is formed on the surface of the first dielectric layer 150 away from the driving substrate 200.

Step S730: a second electrode 180 is formed on the second current spreading layer between the adjacent N-type semiconductor layers 120-a.

Referring to fig. 7, in step S710, the first substrate 110 may be removed using a mechanical polishing method. In the conventional art, the material of the first substrate 110 is often an opaque substance such as silicon, so removing the first substrate 110 may improve the light emitting efficiency of the light emitting chip 120. It will be appreciated by those skilled in the art that when removing the first substrate 110, a mechanical polishing method may be used, i.e., the first substrate 110 is polished in a coarser manner.

In step S720, the second current diffusion layer is used to diffuse the current to other locations of the first dielectric layer 150 away from the surface of the driving substrate 200, similar to the first current diffusion layer 130. Likewise, the second current spreading layer may be grown by electron beam evaporation or other methods on the surface of the first dielectric layer 150 remote from the driving substrate 200 and/or on the N-type semiconductor layer 120-a. The material of the second current spreading layer may also include indium tin oxide, nickel, platinum, or other metals that may form good ohmic contact with the N-type semiconductor layer 120-a.

Also, similar to the first current spreading layer 130, an annealing process may be performed after forming the second current spreading layer.

Referring to fig. 8, in step S730, a second electrode 180 may be formed on the second current diffusion layer between the adjacent N-type semiconductor layers 120-a using a magnetron sputtering deposition method. Specifically, the material of the second electrode 180 may include metal materials such as cobalt, nickel, titanium, tungsten, tantalum titanate, tungsten nitride, copper, and aluminum, and the second electrode 180 may include structures such as titanium/aluminum/titanium, or titanium/aluminum/titanium nitride.

The second electrodes 180 may form a mesh structure on the second current diffusion layer, so that in case that any one of the second electrodes 180 has a voltage, the rest of the second electrodes 180 may obtain the voltage through the mesh structure, thereby improving luminous efficiency.

In another embodiment, a groove may be formed between the adjacent N-type semiconductor layers 120-a, and the groove is filled to form the second electrode 180, so that the second electrode 180 may also be connected to the driving back plate when the driving back plate is bonded, i.e., a loop may be formed between the first electrode 170, the second electrode 180, and the driving back plate. The light emitting chip 120 may emit light when a voltage is applied to the driving back plate.

In one embodiment, step S500 includes:

step S510: a growth barrier layer is formed on the bottom and sidewalls of the electrode recess 160.

Step S520: a first electrode 170 is formed on the growth barrier layer.

In step S510, in order to avoid that the more active electrode metal enters the first dielectric layer 150 and affects the light emitting effect of the light emitting chip 120, a growth blocking layer may be formed on the bottom and the sidewall of the electrode groove 160. As an example, a chemical vapor deposition process may be used to form the growth barrier layer. The material of the growth barrier layer may include titanium, titanium nitride, tantalum, or a layered metal.

In step S520, after the first electrode 170 is formed on the growth blocking layer, the electrode metal is difficult to diffuse, so that the first electrode 170 can obtain a better conductive effect.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.

Based on the same inventive concept, referring to fig. 8, in one embodiment, a semiconductor structure is provided, comprising: the light emitting chip 120, the first electrode 170, the second electrode 180, and the driving substrate 200.

The light emitting chip 120 includes an N-type semiconductor layer 120-a, a light emitting layer 120-b, and a P-type semiconductor layer 120-c formed in this order. The light emitting chips 120 are disposed at intervals, and the first dielectric layer 150 covers the light emitting chips 120 and is filled between the adjacent light emitting chips 120.

The first electrode 170 is disposed in the first dielectric layer 150 and is connected to the P-type semiconductor layer 120-c, i.e., the first electrode 170 is an anode. By way of example, the material of the first electrode 170 includes copper and the material of the first dielectric layer 150 includes silicon oxide, and a damascene process may also be used to form the first electrode 170.

The driving substrate 200 is bonded to the light emitting chip 120 through the first dielectric layer 150 and the first electrode 170. In the case where the driving substrate 200 applies a voltage to the light emitting chip 120, the light emitting chip 120 may emit light.

The second electrode 180 is located on the side of the first dielectric layer 150 away from the driving substrate 200 and is electrically connected to the N-type semiconductor layer 120-a, i.e. the second electrode 180 is a cathode.

In the above semiconductor structure, a current loop is formed between the driving substrate 200, the first electrode 170 and the second electrode 180, and the driving substrate 200 can drive the light emitting chip 120 to emit light. The driving substrate 200 is bonded to the light emitting chip 120 through the first dielectric layer 150 and the first electrode 170, so that the light emitting efficiency of the light emitting chip 120 can be further improved.

In one embodiment, referring to fig. 8, a semiconductor structure includes: a first current spreading layer 130, an etch stop layer 140.

The first current diffusion layer 130 is located on the P-type semiconductor layer 120-c. The first current diffusion layer 130 is used for diffusing the received current to the P-type semiconductor layer 120-c, so as to facilitate improving the light emitting efficiency of the light emitting chip 120. As an example, electron beam evaporation or other means may be used to grow the entire first current spreading layer 130 on the P-type semiconductor layer 120-c. The material of the first current diffusion layer 130 may include indium tin oxide, nickel, platinum, or other metals that may form good ohmic contact with the P-type semiconductor layer 120-c.

An etch stop layer 140 is located on the first current spreading layer 130. The etch stopper 140 may prevent over-etching when the electrode groove 160 is formed by subsequent etching, and protect the first current diffusion layer 130 and the light emitting chip 120. As an example, the material of the etch stop layer 140 may include silicon nitride.

In one embodiment, a semiconductor structure includes: and a second current diffusion layer.

The second current spreading layer is located on the surface of the first dielectric layer 150 near the N-type semiconductor layer 120-a and on the surface of the N-type semiconductor layer 120-a. Similar to the first current spreading layer 130, the second current spreading layer is used to spread the current to other locations of the first dielectric layer 150 away from the surface of the drive substrate 200. Likewise, the second current spreading layer may be grown by electron beam evaporation or other methods on the surface of the first dielectric layer 150 remote from the driving substrate 200 and/or on the N-type semiconductor layer 120-a. The material of the second current spreading layer may also include indium tin oxide, nickel, platinum, or other metals that may form good ohmic contact with the N-type semiconductor layer 120-a.

In one embodiment, the second electrode 180 is electrically connected to the second current diffusion layer between the adjacent N-type semiconductor layers 120-a.

After forming the second current diffusion layer on the first dielectric layer 150, the second electrode 180 may be disposed on the second current diffusion layer, so that the second electrode 180 may be electrically connected to the adjacent N-type semiconductor layer 120-a.

In the above embodiment, the second electrode 180 is electrically connected to the adjacent N-type semiconductor layer 120-a, and each light emitting chip 120 has the first electrode 170, so that each light emitting chip 120 has an anode, and the adjacent light emitting chips 120 share a cathode, thereby reducing the manufacturing cost of the semiconductor structure.

In one embodiment, referring to fig. 8, the driving substrate 200 includes: the second dielectric layer 230 and the driving electrode 240.

The driving electrode 240 is located in the second dielectric layer 230, and the driving electrode 240 is bonded to the first electrode 170, and the second dielectric layer 230 is bonded to the first dielectric layer 150.

The driving substrate 200 may further include a second substrate 210 and a driving chip 220. As an example, the second substrate 210 may include a driving chip 220, a second dielectric layer 230, which are sequentially formed thereon. Also, the second electrode 180 may be electrically connected to the driving chip 220.

In one embodiment, referring to fig. 8 and 9, adjacent light emitting chips 120 are spaced apart, i.e., the N-type semiconductor layer 120-a is discontinuous. The second electrode 180 may be disposed on the first dielectric layer 150 between the adjacent N-type semiconductor layers 120-a, and form a mesh structure on a surface of the first dielectric layer 150 remote from the driving back plate.

In one embodiment, a semiconductor structure includes: and growing a barrier layer.

A growth barrier layer is positioned between the first electrode 170 and the first dielectric layer 150 to prevent electrode metal from entering the first dielectric layer 150. As an example, a chemical vapor deposition process may be used to form the growth barrier layer. The material of the growth barrier layer may include titanium, titanium nitride, tantalum, or a layered metal.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims (10)

1. A semiconductor structure, comprising:

the light-emitting chips comprise an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer which are sequentially formed;

a first dielectric layer covering the light emitting chip;

the first electrode is positioned in the first dielectric layer and connected with the P-type semiconductor layer;

a driving substrate bonded to the first dielectric layer and the first electrode;

and the second electrode is positioned on one side of the first dielectric layer far away from the driving substrate and is electrically connected with the N-type semiconductor layer.

2. The semiconductor structure of claim 1, wherein the semiconductor structure comprises:

and the first current diffusion layer is positioned on the P-type semiconductor layer.

3. The semiconductor structure of claim 2, wherein the semiconductor structure comprises:

and the etching barrier layer is positioned on the first current diffusion layer.

4. The semiconductor structure of claim 1, wherein the semiconductor structure comprises:

and a growth blocking layer positioned between the first electrode and the first dielectric layer.

5. The semiconductor structure of claim 1, wherein adjacent ones of the light emitting chips are spaced apart.

6. The semiconductor structure of claim 1, wherein the semiconductor structure comprises:

and the second current diffusion layer is positioned on the surface of the first dielectric layer close to the N-type semiconductor layer and the surface of the N-type semiconductor layer.

7. The semiconductor structure of claim 6, wherein the second electrode is electrically connected to the second current spreading layer between adjacent N-type semiconductor layers.

8. The semiconductor structure of claim 7, wherein the second electrode is located on the second current spreading layer between adjacent N-type semiconductor layers.

9. The semiconductor structure of claim 1, wherein the drive substrate comprises:

the driving electrode is positioned in the second dielectric layer; the driving electrode is bonded with the first electrode, and the second dielectric layer is bonded with the first dielectric layer.

10. The semiconductor structure of claim 1, wherein the material of the first electrode comprises copper.