CN219998199U - Packaging structure - Google Patents
Packaging structure Download PDFInfo
- Publication number
- CN219998199U CN219998199U CN202321331190.6U CN202321331190U CN219998199U CN 219998199 U CN219998199 U CN 219998199U CN 202321331190 U CN202321331190 U CN 202321331190U CN 219998199 U CN219998199 U CN 219998199U
- Authority
- CN
- China
- Prior art keywords
- chip
- retaining wall
- substrate
- passive element
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000000945 filler Substances 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000002955 isolation Methods 0.000 abstract description 13
- 230000000903 blocking effect Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A package structure includes: the substrate has a first surface; the chip is arranged on the first surface of the substrate and is electrically connected with the substrate; at least one passive element is arranged on the first surface of the substrate, and a set distance is reserved between the passive element and the chip; the retaining wall is arranged on the first surface of the substrate and is positioned between the chip and all the passive elements, the retaining wall is of an intermittent structure, the filling body is filled in a gap between the chip and the substrate and covers at least part of the side face of the chip, the filling body is also filled in the gap between the retaining wall and the chip, and the retaining wall is used for isolating the filling body and the passive elements. In the packaging structure, the retaining wall is arranged between the chip and the passive element, so that when the filling isolation material is filled to form a filling body, the isolation material is blocked by the retaining wall and cannot spread to the passive element, and the formed filling body is only arranged between the retaining wall and the chip and is not contacted with the passive element, so that the reliability of the packaging structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor packaging, and particularly to a packaging structure.
Background
With the development of 5G technology, electronic devices have increasingly higher requirements for multifunction and miniaturization, and the types and numbers of chips that need to be integrally packaged together have also increased. For some packaging structures, passive components (e.g., capacitors, resistors, inductors, etc.) are integrated at the same time as the chip. However, to meet the miniaturization demand, the distance between the chip and the passive element is getting closer and closer, resulting in that the underfill of the chip is liable to contact the passive element, causing reliability failure.
Therefore, how to avoid the contact of the chip underfill with the passive components has become an important research content.
Disclosure of Invention
The utility model aims to solve the technical problem of providing a packaging structure which can prevent a filling body from contacting a passive element and improve the reliability of the packaging structure.
In order to solve the above problems, the present utility model provides a package structure, comprising:
a substrate having a first surface;
a chip disposed on the first surface of the substrate and electrically connected to the substrate;
at least one passive element arranged on the first surface of the substrate, wherein a set distance is reserved between the passive element and the chip;
the retaining wall is arranged on the first surface of the substrate, is positioned between the chip and all the passive elements, and is of an intermittent structure.
The filling body is filled in the gap between the chip and the substrate and covers at least part of the side face of the chip, the filling body is also filled in the gap between the retaining wall and the chip, and the retaining wall is used for isolating the filling body and the passive element.
In an embodiment, the retaining wall includes one or more sub-retaining walls, each of the sub-retaining walls is disposed between at least one of the passive components and the chip, and the sub-retaining walls are not connected.
In an embodiment, the sub-retaining wall is a strip structure, and two ends of the strip structure protrude from the passive element isolated by the strip structure by a set distance from the passive element located at the edge.
In an embodiment, the sub-retaining wall is a concave structure, the passive element is disposed in a groove of the concave structure, and an opening of the concave structure faces a direction away from the filling body.
In an embodiment, the orthographic projection of the passive element on the substrate is surrounded by the orthographic projection of the sub-retaining wall on the substrate.
In an embodiment, the retaining wall and the filling body are of the same material structure.
In one embodiment, the top surface of the retaining wall is higher than the bottom surface of the chip.
In one embodiment, the retaining wall protrudes from the filler at a point where the filler contacts the retaining wall.
In an embodiment, a conductive solder ball is disposed between the chip and the substrate, the chip is electrically connected to the substrate through the conductive solder ball, and the filler encapsulates the conductive solder ball.
In the packaging structure provided by the embodiment of the utility model, the retaining wall is arranged between the chip and the passive element, so that when the isolating material is filled to form the filler, the isolating material is blocked by the retaining wall and cannot spread to the passive element, and the formed filler is only arranged between the retaining wall and the chip and is not contacted with the passive element, thereby improving the reliability of the packaging structure.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present utility model and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1A is a schematic top view of a conventional package structure;
FIG. 1B is a schematic cross-sectional view taken along line A-A1 of FIG. 1A;
FIG. 2 is a schematic top view of a package structure according to an embodiment of the present utility model;
FIG. 3 is a schematic cross-sectional view taken along line A-A1 of FIG. 2;
FIG. 4 is a schematic top view of a package structure according to another embodiment of the present utility model;
fig. 5 is a schematic diagram of a relationship between the passive component and the orthographic projection of the sub-barrier wall on the substrate in the package structure according to another embodiment of the utility model.
Detailed Description
The following describes in detail the embodiments of the package structure provided by the present utility model with reference to the accompanying drawings.
Fig. 1A is a schematic top view of a conventional package structure, and fig. 1B is a schematic cross-sectional view taken along line A-A1 in fig. 1A, referring to fig. 1A and 1B, in the package structure, when the distance between the chip 100 and the passive element 110 is relatively short, when the chip 100 is underfilled with the isolation material, the isolation material easily spreads to the passive element 110, so that the finally formed filling body 120 contacts the passive element 110, and the reliability failure of the package structure is triggered.
In view of this, the embodiment of the utility model provides a packaging structure, which can avoid the contact between the filling body and the passive element and improve the reliability of the packaging structure.
Fig. 2 is a schematic top view of a package structure according to an embodiment of the present utility model, and fig. 3 is a schematic cross-sectional view taken along a line A-A1 in fig. 2, referring to fig. 2 and 3, the package structure includes: a substrate 230 having a first surface 230A; a chip 200 disposed on the first surface 230A of the substrate 230 and electrically connected to the substrate 230; at least one passive element 210 disposed on the first surface 230A of the substrate 230, and having a set distance between the passive element 210 and the chip 200 in a direction parallel to the first surface 230A of the substrate 230; the retaining wall 260 is disposed on the first surface 230A of the substrate 230 and located between the chip 200 and all the passive components 210, and the retaining wall 260 is an intermittent structure. And a filler 220 filled in a gap between the chip 200 and the substrate 230 and covering at least a portion of the side surface of the chip 200, wherein the filler 220 is further filled in the gap between the retaining wall 260 and the chip 200, and the retaining wall 260 is used for isolating the filler 220 from the passive element 210.
In the package structure provided by the embodiment of the utility model, the retaining wall 260 is arranged between the chip 200 and all the passive elements 210, so that when the spacer material is filled to form the filler 220, the spacer material is blocked by the retaining wall 260 and cannot spread to the passive elements 210, and the formed filler 220 is only arranged between the retaining wall 260 and the chip 200 and is not in contact with the passive elements 210, thereby improving the reliability of the package structure.
The substrate 230 has relatively flat upper and lower surfaces with electrically conductive traces therebetween to enable electrical connection between the chip 200 and the passive component 210 and electrical connection between the chip 200 and the passive component 210 through the substrate 230 and external circuitry. In this embodiment, the upper surface of the substrate 230 is used as the first surface 230A of the substrate 230. In some embodiments, the substrate 230 may be a multi-layer PCB board, a ceramic substrate, or an organic substrate, and in this embodiment, the substrate 230 is illustrated as a multi-layer PCB board.
In this embodiment, the chip 200 is flip-chip disposed on the first surface 230A of the substrate 230, and is electrically connected to the substrate 230 through conductive solder balls 250. Specifically, a conductive solder ball 250 is disposed between the chip 200 and the substrate 230, and the chip 200 is electrically connected to the substrate 230 through the conductive solder ball 250. In one embodiment, the conductive solder balls 250 are electrically connected to pads on the first surface 230A of the substrate 230, which are electrically connected to conductive traces within the substrate 230.
The passive elements (Passive Components) 210 include, but are not limited to, capacitance, inductance, resistance, and the like. In this embodiment, the passive element 210 is taken as an example of a capacitor. In some embodiments, the package structure includes a plurality of passive elements 210, the passive elements 210 are disposed around the chip 200, and each passive element 210 has a set distance from the chip 200, that is, each passive element 210 is not contacted to the chip 200, and a space is provided between each passive element 210 and the chip 200.
The discontinuous structure of the retaining wall 260 means that the retaining wall 260 is discontinuous at the periphery of the chip 200, that is, the retaining wall 260 is not a closed structure surrounding the periphery of the chip 200, but a void (as indicated by a dotted line box B in fig. 2) exists, which allows the isolation material to overflow into the passive element region, so as to prevent the isolation material from spreading to the passive element 210 beyond the retaining wall 260 due to the blocking of the retaining wall 260.
In some embodiments, the retaining wall 260 includes one or more sub-retaining walls, each of the sub-retaining walls is disposed between at least one of the passive components 210 and the chip 200, and the sub-retaining walls are not connected.
For example, in some embodiments, the retaining wall 260 includes a plurality of sub-retaining walls 240, and one sub-retaining wall 240 is disposed between a plurality of the passive elements 210 and the chip 200, that is, one sub-retaining wall 240 simultaneously isolates a plurality of the passive elements 210 from the filler 220, and a plurality of sub-retaining walls 240 isolate all of the passive elements 210 from the filler 220. Specifically, in the present embodiment, the retaining wall 260 includes four sub-retaining walls 240 disposed on four sides of the chip 200, and the four sub-retaining walls 240 are not connected, and each sub-retaining wall 240 is disposed between one side of the chip 200 and the passive elements 210 located on one side of the side. For another example, in other embodiments (as shown in fig. 4), the retaining wall 260 includes a plurality of sub-retaining walls 340, one of the sub-retaining walls 340 being disposed between one of the passive components 210 and the chip 200.
In some embodiments, the retaining wall 260 and the filler 220 are of the same material structure, and have high compatibility, so that the problem of detachment does not exist, and the reliability of the package structure is further improved.
In some embodiments, in order to ensure package reliability, the filler 220 needs to fill the area between the bottom surface of the chip 200 and the first surface 230A of the substrate 230, so that when filling the spacer material to form the filler 220, the spacer material surface is required to be at least higher than the bottom surface of the chip 200. In view of this, in order to further avoid spreading of the isolation material, the top surface of the retaining wall 260 is higher than the bottom surface of the chip 200, so that the blocking effect of the retaining wall 260 can be further improved, and the retaining wall 260 blocks the isolation material, so that the isolation material spreads toward the area between the bottom surface of the chip 200 and the first surface 230A of the substrate 230, thereby further ensuring the reliability of the package structure.
In some embodiments, at the contact point between the filling body 220 and the retaining wall 260, the retaining wall 260 protrudes from the filling body 220, so that the filling body 220 and the passive component 210 can be effectively isolated, and the reliability of the package structure can be further improved.
Further, in some embodiments, the sub-retaining wall 240 is a strip structure, and two ends of the strip structure protrude from the passive element 210 at the edge of the passive element 210, respectively, by a set distance, that is, by increasing the distance between the passive element at the edge and the end of the sub-retaining wall 240, it is further ensured that the filler 220 cannot overflow to the passive element 210 by bypassing the side surface of the sub-retaining wall 240. The set distances from the two ends of the strip-shaped structure to the passive element 210 at the edge of the passive element 210 isolated by the strip-shaped structure may be equal or unequal, and the set distances may be set to a value capable of avoiding the filler 220 from overflowing to the passive element 210 by bypassing the side surfaces of the sub-retaining wall 240.
Specifically, referring to fig. 2 and 3, in the present embodiment, the sub-retaining wall 240 has a strip structure, a first end thereof protrudes from the passive element 210A located at the edge of the passive element 210 isolated therefrom by a set distance H1, and a second end thereof protrudes from the passive element 210B located at the edge of the passive element 210 isolated therefrom by a set distance H2, wherein the set distance H1 is equal to the set distance H2. In other embodiments, the set distance H1 and the set distance H2 may not be equal.
Further, in other embodiments, the sub-retaining wall 240 has a concave structure, the passive component 210 is disposed in a groove of the concave structure, and an opening of the concave structure faces away from the filler 220, so that a blocking capability of the retaining wall 260 can be further increased, and the filler 220 is prevented from spreading from a side surface of the sub-retaining wall 240 to the passive component 210.
Specifically, referring to fig. 4, fig. 4 is a schematic top view of a package structure according to another embodiment of the utility model, in which the retaining wall 260 includes a plurality of sub-retaining walls 340, each sub-retaining wall 340 has a concave structure, one passive element 210 is disposed in a groove of the concave structure, and an opening of the concave structure faces away from the filling body 220, so as to further prevent the filling body 220 from spreading from a side surface of the sub-retaining wall 340 to the passive element 210.
In some embodiments, the orthographic projection of the passive element on the substrate 230 is surrounded by the orthographic projection of the sub-retaining wall 240 on the substrate 230, that is, the passive element is located entirely within the range of the sub-retaining wall 240, so as to further enhance the blocking effect of the retaining wall 260 and avoid the filler 220 from spreading from the side surface of the sub-retaining wall 340 to the passive element 210. Please refer to fig. 5, which is a schematic diagram illustrating the relationship between the passive component and the front projection of the sub-barrier 340 on the substrate 230, wherein the front projection 500 of the passive component on the substrate 230 is located within the enclosure of the front projection 510 of the sub-barrier 340 on the substrate 230, and the upper edge of the front projection 500 of the passive component on the substrate 230 is lower than the connection line C of the upper edge of the front projection 510 of the sub-barrier 340 on the substrate 230.
In the package structure provided by the embodiment of the utility model, the filler 220 is only arranged between the retaining wall and the chip 200 and is not contacted with the passive element 210, so that the reliability of the package structure is improved.
The utility model also provides a forming method of the packaging structure. The method comprises the following steps:
the chip 200 and the passive element 210 are disposed on the first surface 230A of the substrate 230. The chip 200 may be electrically connected to the substrate 230 through conductive solder balls 250, and the passive element 210 may be connected to the substrate 230 through an adhesive film or the like.
A retaining wall 260 is formed on the first surface 230A of the substrate 230. In this step, the retaining wall 260 may be formed by dispensing, etc., and baked and cured.
An isolation material is filled in the gap between the chip 200 and the substrate 230 and the gap between the retaining wall 260 and the chip 200, and the retaining wall 260 is used for isolating the isolation material from the passive element 210, so that the isolation material can be prevented from spreading to the passive element 210.
Baking and curing the isolation material to form the filler 220.
It should be noted that the terms "comprising" and "having" and their variants are referred to in the document of the present utility model and are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. The term "one or more" depends at least in part on the context and may be used to describe a feature, structure, or characteristic in a singular sense or may be used to describe a feature, structure, or combination of features in a plural sense. The term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but may instead, also depend at least in part on the context, allow for other factors to be present that are not necessarily explicitly described. In addition, the embodiments of the present utility model and the features in the embodiments may be combined with each other without collision. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present utility model. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
The foregoing is merely a preferred embodiment of the present utility model and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present utility model, which are intended to be comprehended within the scope of the present utility model.
Claims (9)
1. A package structure, comprising:
a substrate having a first surface;
a chip disposed on the first surface of the substrate and electrically connected to the substrate;
at least one passive element arranged on the first surface of the substrate, wherein a set distance is reserved between the passive element and the chip;
the retaining wall is arranged on the first surface of the substrate, is positioned between the chip and all the passive elements, and is of an intermittent structure;
the filling body is filled in the gap between the chip and the substrate and covers at least part of the side face of the chip, the filling body is also filled in the gap between the retaining wall and the chip, and the retaining wall is used for isolating the filling body and the passive element.
2. The package structure of claim 1, wherein the retaining wall comprises one or more sub-retaining walls, each of the sub-retaining walls being disposed between at least one of the passive components and the chip and being unconnected between the plurality of sub-retaining walls.
3. The package structure according to claim 2, wherein the sub-retaining wall is a strip structure, and two ends of the strip structure protrude from the passive element isolated by the strip structure by a set distance from the passive element located at the edge.
4. The package structure of claim 2, wherein the sub-retaining wall is a concave structure, the passive element is disposed in a groove of the concave structure, and an opening of the concave structure faces away from the filler.
5. The package structure of claim 4, wherein an orthographic projection of the passive component onto the substrate is surrounded by an orthographic projection of the sub-barrier wall onto the substrate.
6. The package structure according to any one of claims 1 to 5, wherein the retaining wall and the filler are of the same material structure.
7. The package structure of any one of claims 1 to 5, wherein a top surface of the retaining wall is higher than a bottom surface of the chip.
8. The package structure according to any one of claims 1 to 5, wherein the retaining wall protrudes from the filler at a point where the filler contacts the retaining wall.
9. The package structure according to any one of claims 1 to 5, wherein a conductive solder ball is disposed between the chip and the substrate, the chip is electrically connected to the substrate through the conductive solder ball, and the filler encapsulates the conductive solder ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321331190.6U CN219998199U (en) | 2023-05-29 | 2023-05-29 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321331190.6U CN219998199U (en) | 2023-05-29 | 2023-05-29 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219998199U true CN219998199U (en) | 2023-11-10 |
Family
ID=88611819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321331190.6U Active CN219998199U (en) | 2023-05-29 | 2023-05-29 | Packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219998199U (en) |
-
2023
- 2023-05-29 CN CN202321331190.6U patent/CN219998199U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7884460B2 (en) | Integrated circuit packaging system with carrier and method of manufacture thereof | |
| US8329507B2 (en) | Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same | |
| KR100493063B1 (en) | BGA package with stacked semiconductor chips and manufacturing method thereof | |
| US8541260B1 (en) | Exposed die overmolded flip chip package and fabrication method | |
| US8963299B2 (en) | Semiconductor package and fabrication method thereof | |
| US10361177B2 (en) | Semiconductor package having a molding layer including a molding cavity and method of fabricating the same | |
| US8982577B1 (en) | Electronic component package having bleed channel structure and method | |
| US7629677B2 (en) | Semiconductor package with inner leads exposed from an encapsulant | |
| CN104241255B (en) | Electronic component module and its manufacture method | |
| US20100059873A1 (en) | Ball grid array package stacking system | |
| KR20190004964A (en) | Semiconductor packages | |
| KR20150016711A (en) | Multi-chip package | |
| CN111341753A (en) | Embedded type packaging device | |
| US8703535B2 (en) | Integrated circuit packaging system with warpage preventing mechanism and method of manufacture thereof | |
| US7902664B2 (en) | Semiconductor package having passive component and semiconductor memory module including the same | |
| CN219998199U (en) | Packaging structure | |
| US20040217451A1 (en) | Semiconductor packaging structure | |
| US8502083B2 (en) | Mounting substrate and electronic device | |
| CN113327918A (en) | Multi-chip packaging structure and packaging method | |
| KR100895815B1 (en) | Semiconductor package and method of manufacturing theereof | |
| TW202137425A (en) | Chip package structure and manufacturing method thereof | |
| KR102400533B1 (en) | Electronic component module and manufacturing method thereof | |
| TWI748189B (en) | Structure of system in package module and method of packaging system in package module | |
| KR20140027800A (en) | Stack package of electronic device and method for manufacturing the same | |
| JP2630294B2 (en) | Hybrid integrated circuit device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |