CN219997453U

CN219997453U - Array substrate, display panel and display device

Info

Publication number: CN219997453U
Application number: CN202321294443.7U
Authority: CN
Inventors: 李阳; 袁海江
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2023-05-25
Filing date: 2023-05-25
Publication date: 2023-11-10
Anticipated expiration: 2033-05-25

Abstract

The utility model provides an array substrate, a display panel and a display device. The array substrate includes: the pixel unit groups are arranged in an array mode, and at least comprise adjacent first pixel units and second pixel units, and the first pixel units and the second pixel units display the same color; the thin film transistor group comprises a first thin film transistor and a second thin film transistor, and the drain electrode of the first thin film transistor and the drain electrode of the second thin film transistor are electrically connected to the same data line; the storage capacitor group comprises a first storage capacitor and a second storage capacitor, wherein the first storage capacitor is electrically connected with the source electrode of the first thin film transistor, the second storage capacitor is electrically connected with the source electrode of the second thin film transistor, the first storage capacitor has a first capacitance value, the second storage capacitor has a second capacitance value, and the first capacitance value is larger than or smaller than the second capacitance value, so that the picture display effect of the display panel and the display device is improved.

Description

Array substrate, display panel and display device

Technical Field

The present utility model relates to the field of display technologies, and in particular, to an array substrate, a display panel and a display device.

Background

The liquid crystal display (Liquid Crystal Display, LCD) has many advantages of thin body, power saving, no radiation, etc., and is widely used in various scenes. Such as: liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computer screens, notebook computer screens, etc., and are dominant in the field of flat panel displays.

The pixel unit design modes of the liquid crystal display often adopt a structure of 4 domains (4 domains) or 8 domains (8 domains), and compared with the pixel unit structural design of 8 domains (8 domains), the pixel unit structural design of 4 domains (4 domains) has a higher aperture ratio, but has to be improved in the aspects of improving the color cast of the liquid crystal display and improving the visual angle display effect of the liquid crystal display.

Disclosure of Invention

In view of the above, the present utility model provides an array substrate, a display panel and a display device, so as to improve the display effect of the display panel and the display device.

In a first aspect, the present utility model provides an array substrate, including:

the pixel unit groups are arranged in an array, different pixel unit groups are connected to different data lines, the pixel unit groups comprise a first pixel unit and a second pixel unit, the first pixel unit and the second pixel unit are positioned in two adjacent rows, the first pixel unit and the second pixel unit are respectively connected with different grid lines and the same data line, and the first pixel unit and the second pixel unit display the same color;

the thin film transistor group comprises a first thin film transistor and a second thin film transistor, the first thin film transistor is used for controlling the first pixel unit to work and operate, the second thin film transistor is used for controlling the second pixel unit to work and operate, and the drain electrode of the first thin film transistor and the drain electrode of the second thin film transistor are electrically connected to the same data line;

the storage capacitor group comprises a first storage capacitor and a second storage capacitor, wherein the first storage capacitor is electrically connected with the source electrode of the first thin film transistor, the second storage capacitor is electrically connected with the source electrode of the second thin film transistor, the first storage capacitor has a first capacitance value, the second storage capacitor has a second capacitance value, and the first capacitance value is larger than or smaller than the second capacitance value.

The array substrate further comprises a gate line group, the gate line group comprises a first gate line and a second gate line, the first gate line is electrically connected to the gate of the first thin film transistor and transmits a first gate signal to the first thin film transistor, the second gate line is electrically connected to the gate of the second thin film transistor and transmits a second gate signal to the second thin film transistor, and the first gate signal and the second gate signal are used for controlling the first thin film transistor and the second thin film transistor to be simultaneously turned on.

The first gate line and the second gate line are electrically connected to the same control signal terminal.

The array substrate further comprises a first liquid crystal capacitor and a second liquid crystal capacitor, wherein the first liquid crystal capacitor is electrically connected with the source electrode of the first thin film transistor, and the second liquid crystal capacitor is electrically connected with the source electrode of the second thin film transistor.

Wherein, the array substrate still includes:

a first pixel electrode and a first common electrode, the first pixel electrode and the first common electrode forming the first storage capacitor; a kind of electronic device with high-pressure air-conditioning system

The second pixel electrode and the second common electrode form the second storage capacitor.

Wherein the area of the first common electrode is larger or smaller than the area of the second common electrode.

In a second aspect, the present utility model further provides a display panel, where the display panel includes a color film substrate, a liquid crystal layer, and the array substrate, and the liquid crystal layer is sandwiched between the color film substrate and the array substrate.

Wherein, the display panel still includes:

the first pixel electrode and the third common electrode are oppositely arranged, and form a first liquid crystal capacitor; a kind of electronic device with high-pressure air-conditioning system

And a second pixel electrode and a fourth common electrode which are oppositely arranged, wherein the second pixel electrode and the fourth common electrode form a second liquid crystal capacitor.

The third common electrode and the fourth common electrode are arranged on the color film substrate, and the area of the third common electrode is equal to that of the fourth common electrode.

In a third aspect, the present utility model further provides a display device, where the display device includes a backlight module and a display panel, and the backlight module is configured to provide a surface light source to the display panel. The display panel can display different brightness effects between the first pixel unit and the second pixel unit by designing the first capacitance value inconsistent with the second capacitance value, so that the pixel unit of the display panel can have a display effect similar to an 8-domain structure when the pixel unit is in a 4-domain structure, and the display panel can have a better display view angle while having an opening ratio.

Drawings

In order to more clearly illustrate the technical solutions of the present utility model, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained by those skilled in the art without the inventive effort.

Fig. 1 is a schematic structural diagram of a first pixel unit according to an embodiment of the utility model;

fig. 2 is a schematic structural diagram of a pixel unit group according to a first embodiment of the present utility model;

fig. 3 is a schematic circuit structure diagram corresponding to a first pixel unit according to an embodiment of the utility model;

fig. 4 is a schematic circuit structure diagram corresponding to a second pixel unit according to an embodiment of the utility model;

fig. 5 is a schematic circuit structure diagram corresponding to a pixel unit group according to an embodiment of the utility model;

fig. 6 is a schematic structural diagram of a pixel unit cell according to a comparative embodiment of the present utility model;

fig. 7 is a schematic structural diagram of a pixel unit group according to a second embodiment of the present utility model;

fig. 8 is a schematic circuit diagram of a pixel unit group according to a second embodiment of the present utility model;

fig. 9 is a schematic structural view of a display device according to an embodiment of the present utility model;

fig. 10 is a partial schematic structural view of the display device provided in fig. 9 in a section along A-A line.

Reference numerals illustrate:

1-display device, 10-display panel, 20-backlight module, 11-pixel unit group, 12-storage capacitor group, 13-grid line group, 14-color film substrate, 15-array substrate, 16-liquid crystal layer, 17-data line, 111-first pixel unit, 112-second pixel unit, 121-first storage capacitor, 122-second storage capacitor, 131-first grid line, 132-second grid line, 133-third grid line, 151-first common electrode, 152-second common electrode, 161-first pixel electrode, 162-second pixel electrode.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, are intended to fall within the scope of the present utility model.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" or "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 2, fig. 3, fig. 4, fig. 6 and fig. 9, fig. 1 is a schematic structural diagram of a first pixel unit according to an embodiment of the present utility model, fig. 2 is a schematic structural diagram of a pixel unit group according to a first embodiment of the present utility model, fig. 3 is a schematic circuit structure corresponding to the first pixel unit according to an embodiment of the present utility model, fig. 4 is a schematic circuit structure corresponding to a second pixel unit according to an embodiment of the present utility model, fig. 6 is a schematic structural diagram of a pixel unit group according to a comparative embodiment of the present utility model, and fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present utility model. The present embodiment provides an array substrate 15, where the array substrate 15 includes a plurality of pixel unit groups 11, a thin film transistor group and a storage capacitor group 12, the plurality of pixel unit groups 11 are arranged in an array, and different pixel unit groups 11 are connected to different data lines 17, the pixel unit groups 11 include adjacent first pixel units 111 and second pixel units 112, the first pixel units 111 and the second pixel units 112 are located in two adjacent rows, the first pixel units 111 and the second pixel units 112 are respectively connected with different gate lines and connected with the same data line 17, and the first pixel units 111 and the second pixel units 112 display the same color. The thin film transistor group includes a first thin film transistor T1 and a second thin film transistor T2, the first thin film transistor T1 is used for controlling the first pixel unit 111 to operate, the second thin film transistor T2 is used for controlling the second pixel unit 112 to operate, and the drain electrode of the first thin film transistor T1 and the drain electrode of the second thin film transistor T2 are electrically connected to the same DL. The storage capacitor set 12 includes a first storage capacitor 121 (CST 1) and a second storage capacitor 122 (CST 2), wherein the first storage capacitor 121 (CST 1) is electrically connected to a source of the first thin film transistor T1, the second storage capacitor 122 (CST 2) is electrically connected to a source of the second thin film transistor T2, and the first storage capacitor 121 (CST 1) has a first capacitance value, and the second storage capacitor 122 (CST 2) has a second capacitance value, and the first capacitance value is greater than or less than the second capacitance value.

The array substrate 15 may be applied to the display panel 10, and the display panel 10 may be, but is not limited to, a liquid crystal display panel (Liquid Crystal Display, LCD) or an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel, etc.

The array substrate 15 may include a plurality of the pixel unit groups 11 arranged in an array. The array substrate 15 may include a plurality of columns of the pixel cell groups 11, and different pixel cell groups are electrically connected to different Data Lines (DL). The pixel unit group 11 includes the adjacent first pixel unit 111 and the adjacent second pixel unit 112. The first pixel unit 111 and the second pixel unit 112 are located in two rows that are vertically adjacent. The first pixel unit 111 and the second pixel unit 112 may be electrically connected to different gate lines, and the first pixel unit 111 and the second pixel unit 112 may be, but are not limited to, electrically connected to the same data line.

The first pixel unit 111 may be, but not limited to, displaying red (R), green (G), blue (B), etc., and it is understood that the first pixel unit 111 may also display other colors. The first pixel unit 111 may be, but not limited to, a 4-domain structure, an 8-domain structure, or the like.

The second pixel unit 112 may be, but is not limited to, displaying red (R), green (G), blue (B), etc., and it is understood that the second pixel unit 112 may also display other colors. The second pixel unit 112 may display the same color as the first pixel unit 111. The second pixel unit 112 may be, but is not limited to, a 4-domain structure, an 8-domain structure, or the like.

A thin film transistor (Thin Film Transistor, TFT) may be used to drive the operational operation of the pixel cell. In the embodiment of the present utility model, the thin film transistor group includes a first thin film transistor T1 and a second thin film transistor T2, where the first thin film transistor T1 is used for driving and controlling the first pixel unit 111 to operate, and the second thin film transistor T2 is used for driving and controlling the second pixel unit 112 to operate.

The storage capacitor set 12 includes a first storage capacitor 121 (CST 1) and a second storage capacitor 122 (CST 2). The first storage capacitor 121 (CST 1) may be, but is not limited to, a source or a drain electrically connected to the first thin film transistor T1. The first storage capacitor 121 (CST 1) has a first capacitance value, which may be, but is not limited to, a value calculated according to an actual application or experimental simulation. And the first capacitance value may be, but is not limited to, a value preset during the manufacturing process of the display panel 10.

The second storage capacitor 122 (CST 2) is electrically connected to a source or drain of the second thin film transistor T2. The second storage capacitor 122 (CST 2) has a second capacitance value, which may be, but is not limited to, calculated according to actual application or experimental simulation. And the second capacitance value may be, but is not limited to, a value preset during the manufacturing process of the display panel 10.

The first capacitance value may be, but is not limited to being, greater than or less than the second capacitance value, as long as the first capacitance value and the second capacitance value are not consistent in size. Specifically, when the first capacitance value is inconsistent with the second capacitance value, the first pixel unit 111 and the second pixel unit 112 display different brightness due to the inconsistent first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2) when the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on, that is, the first pixel unit 111 and the second pixel unit 112 simultaneously operate, so that the display viewing angle of the display panel 10 is improved. In an embodiment of the present utility model, the first pixel unit 111 may be a 4-domain (4 domain) structural design, the second pixel unit 112 may be a 4-domain (4 domain) structural design, and by designing the first storage capacitor 121 (CST 1) and the second storage capacitor 122 (CST 2) to have different capacitance values, different brightness effects may be displayed between the first pixel unit 111 and the second pixel unit 112, so that the display panel 10 may also have a display effect of approximately 8 domains (8 domains), so that the display panel 10 may have a better display viewing angle while having an aperture ratio.

Further, the difference between the first capacitance value and the second capacitance value may be, but not limited to, an adjustment according to an actual display effect of the display panel 10, so that the display panel 10 may also consider a clear display effect of resolution while improving a display viewing angle.

Further, the pixel unit group may further include a plurality of adjacent first pixel units 111 and second pixel units 112. In one embodiment of the present utility model (fig. 2), the pixel unit group includes three first pixel units 111 and three second pixel units, where the three first pixel units 111 may respectively display red (R), green (G) and blue (B), and the three second pixel units 112 may respectively display red (R), green (G) and blue (B). And the capacitance difference between the pixel units displaying different colors can be the same or different, which is not limited by the utility model.

In a comparison embodiment of the present utility model (fig. 5), the first storage capacitor 121 of the first pixel unit 111 and the second storage capacitor 122 of the second pixel unit 112 have the same capacitance value, so that the first pixel unit 111 and the second pixel unit 112 maintain the same brightness when they are lit, which is disadvantageous for improving color cast of the display panel and enlarging display viewing angle.

In summary, the display panel 10 according to the embodiment of the utility model includes the pixel unit group 11, the thin film transistor group and the storage capacitor group 12, wherein the pixel unit group 11 includes at least a first pixel unit 111 and a second pixel unit 112 that are adjacent to each other, and the first pixel unit 111 and the second pixel unit 112 display the same color. The storage capacitor set 12 includes a first storage capacitor 121 (CST 1) and a second storage capacitor 122 (CST 2), where the first storage capacitor 121 (CST 1) has a first capacitance value, the second storage capacitor 122 (CST 2) has a second capacitance value, and the first capacitance value is greater than or less than the second capacitance value, i.e., the magnitude of the first capacitance value is inconsistent with the magnitude of the second capacitance value, so that different brightness effects can be displayed between the first pixel unit 111 and the second pixel unit 112, and thus, when the pixel unit of the display panel 10 has a structure of 4 domains (4 domains), the display effect of approximately 8 domains (8 domains) can be achieved, so that the display panel 10 has an aperture ratio and simultaneously can also perform color shift reduction, and has a better display viewing angle.

Please refer to fig. 1, 2, 3 and 4 again. The array substrate 15 further includes a gate line group 13, where the gate line group 13 includes a first gate line 131 (GL 1) and a second gate line 132 (GL 2), the first gate line 131 (GL 1) is electrically connected to the gate of the first thin film transistor T1 and transmits a first gate signal to the first thin film transistor T1, the second gate line 132 (GL 2) is electrically connected to the gate of the second thin film transistor T2 and transmits a second gate signal to the second thin film transistor T2, and the first gate signal and the second gate signal are used for controlling the first thin film transistor T1 and the second thin film transistor T2 to be turned on simultaneously.

In one embodiment of the present utility model, the first pixel unit 111 and the second pixel unit 112 are each illustrated as a 4-domain (4 domian) structure.

Specifically, the first pixel unit 111 and the second pixel unit 112 are controlled by different gate lines, the first gate line 131 (GL 1) is electrically connected to the gate of the first thin film transistor T1, and transmits a first gate signal to the first thin film transistor T1, where the first gate signal may be used to control the on of the first thin film transistor T1, and further, may control the lighting of the first pixel unit 111.

The second gate line 132 (GL 2) is electrically connected to the gate electrode of the second thin film transistor T2, and transmits a second gate signal to the second thin film transistor T2, which may be used to control the turn-on of the second thin film transistor T2, and further, may control the turn-on of the second pixel unit 112.

In a preferred embodiment of the present utility model, the display panel 10 may employ a Dual Line Gate (DLG) technology, that is, the first Gate Line 131 (GL 1) and the second Gate Line 132 (GL 2) may be turned on simultaneously, so that the first Gate signal and the second Gate signal control the first thin film transistor T1 and the second thin film transistor T2 to be turned on simultaneously, and further, the first pixel unit 111 and the second pixel unit 112 in the display panel 10 may be turned on simultaneously, so that the refresh rate of the display panel 10 may be doubled within the same time, that is, the display panel 10 may achieve high-brush performance.

Referring to fig. 5, fig. 5 is a schematic circuit structure diagram corresponding to a pixel unit group according to an embodiment of the utility model. The first gate line 131 (GL 1) and the second gate line 132 (GL 2) are electrically connected to the same control signal terminal CS.

The first gate line 131 (GL 1) and the second gate line 132 (GL 2) are electrically connected to the same control signal terminal CS, so that the first gate line 131 (GL 1) and the second gate line 132 (GL 2) can simultaneously respond to the control signal terminal CS and output a first gate signal and a second gate signal to the first thin film transistor T1 and the second thin film transistor T2, so as to control the first thin film transistor T1 and the second thin film transistor T2 to be simultaneously turned on, and further, the first pixel unit 111 and the second pixel unit 112 in the display panel 10 can be simultaneously turned on, so that the refresh rate of the display panel 10 is improved within the same time, and the display panel 10 achieves high-brush performance.

Please refer to fig. 1, 2, 3 and 4 again. The array substrate 15 further includes a first liquid crystal capacitor Clc1 and a second liquid crystal capacitor Clc2, wherein the first liquid crystal capacitor Clc1 is electrically connected to the source of the first thin film transistor T1, and the second liquid crystal capacitor Clc2 is electrically connected to the source of the second thin film transistor T2.

One end of the first liquid crystal capacitor Clc1 may be, but is not limited to, a source electrode or a drain electrode electrically connected to the first thin film transistor T1, and in one embodiment of the present utility model, the first liquid crystal capacitor Clc1 is illustrated as being electrically connected to the source electrode of the first thin film transistor T1.

One end of the second liquid crystal capacitor Clc2 may be, but is not limited to, a source electrode or a drain electrode electrically connected to the second thin film transistor T2, and in one embodiment of the present utility model, the second liquid crystal capacitor Clc2 is illustrated as being electrically connected to the source electrode of the second thin film transistor T2.

The capacitance value of the first liquid crystal capacitor Clc1 and the capacitance value of the second liquid crystal capacitor Clc2 may be, but are not limited to, uniform or non-uniform. In one embodiment of the present utility model, the capacitance of the first lc capacitor Clc1 is identical or approximately identical to the capacitance of the second lc capacitor Clc2, so that the brightness difference between the first pixel unit 111 and the second pixel unit 112 can be conveniently controlled by adjusting the capacitance difference between the first storage capacitor 121 (CST 1) and the second storage capacitor 122 (CST 2), thereby improving the display effect and the display yield of the display panel 10.

Please refer to fig. 1, 2, 3 and 4 again. The array substrate 15 further includes a first pixel electrode 161 and a first common electrode 151, and the first pixel electrode 161 and the first common electrode 151 form the first storage capacitor 121 (CST 1). The array substrate 15 further includes a second pixel electrode 162 and a second common electrode 152, and the second pixel electrode 162 and the second common electrode 152 form the second storage capacitor 122 (CST 2).

The first common electrode 151 may be, but is not limited to, a load array substrate common voltage signal ACOM1. The first pixel electrode 161 and the first common electrode 151 may be, but not limited to, disposed on the array substrate 15, and a portion of the first pixel electrode 161 overlapping the first common electrode 151 may constitute the first storage capacitor 121 (CST 1).

The second common electrode 152 may be, but is not limited to, a load array substrate common voltage signal ACOM2. The second pixel electrode 162 and the second common electrode 152 may be, but not limited to, disposed on the array substrate 15, and a portion of the second pixel electrode 162 overlapping the second common electrode 152 may form the second storage capacitor 122 (CST 2).

The capacitance value of the first storage capacitor 121 (CST 1) may be changed by adjusting the area of the first common electrode 151, the capacitance value of the second storage capacitor 122 (CST 2) may be changed by adjusting the area of the second common electrode 152, and when the capacitance value of the first storage capacitor 121 (CST 1) and the capacitance value of the second storage capacitor 122 (CST 2) are different, the difference in brightness between the first pixel unit 111 and the second pixel unit 112 may be controlled, thereby adjusting the display effect of the display panel 10.

Please refer to fig. 2 and 6 again. The area of the first common electrode 151 is larger or smaller than that of the second common electrode 152.

Specifically, the area of the first common electrode 151 may refer to the area of the surface of the first common electrode 151 facing the display surface of the display panel 10. The area of the second common electrode 152 may refer to the area of the surface of the second common electrode 152 facing the display surface of the display panel 10.

The area of the first common electrode 151 may be larger than the area of the second common electrode 152, or may be smaller than the area of the second common electrode 152, as long as the area size of the first common electrode 151 is not consistent with the area size of the second common electrode 152. In the schematic diagram of the present embodiment (fig. 2), the area of the first common electrode 151 is smaller than the area of the second common electrode 152, so that the capacitance value of the first storage capacitor 121 (CST 1) is smaller than the capacitance value of the second storage capacitor 122 (CST 2), and the brightness of the first pixel unit 111 and the brightness of the second pixel unit 112 are inconsistent, so that the display panel 10 has a better display effect.

In a comparative example of the present utility model (fig. 6), an example is shown in which the area of the first common electrode is equal to the area of the second common electrode, and the capacitance value of the first storage capacitor is equal to the capacitance value of the second storage capacitor, so that the brightness of the first pixel unit is consistent with the brightness of the second pixel unit, and the viewing angle of the display panel cannot be improved.

Referring to fig. 9 and 10, fig. 10 is a schematic view of a portion of the display device provided in fig. 9 along a line A-A. The utility model also provides a display panel 10, wherein the display panel 10 comprises a color film substrate 14, an array substrate 15 and a liquid crystal layer 16, and the liquid crystal layer 16 is sandwiched between the color film substrate 14 and the array substrate 15.

The display panel 10 may be, but is not limited to, a liquid crystal display panel 10, or an organic light emitting diode display panel 10, or a field emission display panel 10, or a plasma display panel 10, or a curved panel, etc. The liquid crystal display panel 10 may be, but is not limited to, a thin film transistor liquid crystal display panel 10, a TN panel (TN), a VA panel (VA), an IPS Panel (IPS). It should be understood that the functional type of the display panel 10 should not be limited to the display panel 10 provided in this embodiment.

Preferably, the display panel 10 may be manufactured by using a less Gate Driver (GDL) technology, in which the driving circuit of the horizontal scan line is manufactured on the substrate around the display area by using the original array process of the display panel 10, so that the driving circuit can replace the external integrated circuit board (Integrated Circuit, IC) to complete the driving of the horizontal scan line. The GDL technology can reduce the soldering (bonding) process of the external integrated circuit, has the opportunity to increase the productivity of the display panel 10 and reduce the manufacturing cost thereof, and can make the display panel 10 more suitable for manufacturing display products with narrow frames or without frames.

Preferably, the display panel 10 may also be manufactured by a Dual Line Gate (DLG) technology, where the DLG technology means that Gate lines (gates) corresponding to two adjacent rows of pixel units are turned on simultaneously, so that two adjacent rows of pixel units in the display panel 10 can be turned on simultaneously, and thus the refresh rate of the display panel 10 is doubled in the same time.

Specifically, the Color Filter substrate 14 (CF) may be, but not limited to, for performing Color filtering, and greatly improving the Color performance of the display panel. The Array substrate 15 (Array) may be, but is not limited to, a substrate for controlling the deflection of liquid crystal molecules in the liquid crystal layer. In some embodiments of the present utility model, the filtering unit of the color filter substrate 14 may be integrated with the array substrate 15 for setting, which is not limited in the present utility model.

In the display panel 10 according to the present embodiment, the display brightness of the first pixel unit 111 and the second pixel unit 112 may be further adjusted by adjusting the first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2) in the array substrate 15, so that the display viewing angle of the display panel is improved by the brightness difference between the first pixel unit 111 and the second pixel unit 112.

Please refer to fig. 2, 3 and 4 again. The display panel 10 further includes a first pixel electrode 161 and a third common electrode CFCOM1 disposed opposite to each other, and the first pixel electrode 161 and the third common electrode CFCOM1 form a first liquid crystal capacitor Clc1. The display panel 10 further includes a second pixel electrode 162 and a fourth common electrode CFCOM2 disposed opposite to each other, and the second pixel electrode 162 and the fourth common electrode CFCOM2 form a second liquid crystal capacitor Clc2.

The third common electrode CFCOM1 may be, but is not limited to, a common voltage signal for loading the color film substrate. The third common electrode CFCOM1 may be disposed on the color film substrate 14, the first pixel electrode 161 may be disposed on the array substrate 15, and the first pixel electrode 161 may be disposed opposite to the third common electrode CFCOM1 and form the first liquid crystal capacitor Clc1.

The fourth common electrode CFCOM2 may be, but is not limited to, a common voltage signal for loading the color film substrate. The fourth common electrode CFCOM2 may be disposed on the color film substrate 14, the second pixel electrode 162 may be disposed on the array substrate 15, and the second pixel electrode 162 may be disposed opposite to the fourth common electrode CFCOM2 and form the first liquid crystal capacitor Clc2.

Further, the capacitance values of the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 may be, but are not limited to be, equal or approximately equal, so that accurate control of the brightness of the first pixel unit 111 and the second pixel unit 112 may be achieved by adjusting only the first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2).

Referring to fig. 2, 3 and 4 again, the third common electrode CFCOM1 and the fourth common electrode CFCOM2 are disposed on the color film substrate 14, and the area of the third common electrode CFCOM1 is equal to the area of the fourth common electrode CFCOM 2.

The third common electrode CFCOM1 may be disposed on the color film substrate 14 and used for loading a color film substrate common voltage signal. The fourth common electrode CFCOM2 may be disposed on the color film substrate 14 and used for loading a color film substrate common voltage signal.

Further, the area of the surface of the third common electrode CFCOM1 facing the first pixel electrode 161 may be, but is not limited to, equal to the area of the surface of the fourth common electrode CFCOM2 facing the second pixel electrode 162, so that the capacitance value of the first liquid crystal capacitor Clc1 is equal to the capacitance value of the second liquid crystal capacitor Clc2. Further, by adjusting the first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2), the brightness of the first pixel unit 111 and the brightness of the second pixel unit 112 can be precisely controlled, and thus the display effect of the display panel 10 can be precisely adjusted.

Referring to fig. 7 and 8, fig. 7 is a schematic structural diagram of a pixel unit group according to a second embodiment of the present utility model, and fig. 8 is a schematic circuit structure corresponding to the pixel unit group according to the second embodiment of the present utility model. The display panel 10 further includes a third gate line 133 (GL 3), and the third gate line 133 (GL 3) is electrically connected to the gate electrode of the first thin film transistor T1 and the gate electrode of the second thin film transistor T2.

In one embodiment of the present utility model, the pixel unit structure of the first pixel unit 111 and the second pixel unit 112 that together form an 8domain (8 domain) is illustrated as an example.

The gate electrode of the first thin film transistor T1 and the gate electrode of the second thin film transistor T2 may be, but are not limited to, electrically connected to the same third gate line 133 (GL 3), such that the third gate line 133 (GL 3) may simultaneously transmit gate signals to the first pixel unit 111 and the second pixel unit 112, and may be used to control the lighting of the first pixel unit 111 and the second pixel unit 112.

When the first pixel unit 111 and the second pixel unit 112 together form an 8-domain (8 domain) pixel unit structure, the first pixel unit 111 may be, but is not limited to, a Main pixel (main_pixel), and the second pixel unit 112 may be, but is not limited to, a sub-pixel (sub_pixel). The first thin film transistor T1 may be, but is not limited to, a main_pixel TFT, and the second thin film transistor T2 may be, but is not limited to, a sub_pixel TFT.

In one embodiment of the present utility model, the first pixel unit 111 (main_pixel) and the second pixel unit 112 (sub_pixel) may have brightness of the first pixel unit 111 and brightness of the second pixel unit 112 inconsistent by adjusting the difference between the first storage capacitor 121 (CST 1) and the second storage capacitor 122 (CST 2), that is, by designing the first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2) to be different in magnitude. The number of the pixel unit groups 11 formed by the first pixel units 111 and the second pixel units 112 may be plural, the plurality of pixel unit groups 11 may be arranged in an array in the display panel 10, and the brightness of the first pixel units 111 and the brightness of the second pixel units 112 are alternated, so that the display viewing angle and the display effect of the display panel 10 may be effectively improved.

Please refer to fig. 7 and 8. The display panel 10 further includes a third thin film transistor T3 and a fifth common electrode SCOM, wherein a gate electrode of the third thin film transistor T3 is electrically connected to the third gate line 133 (GL 3), a drain electrode of the third thin film transistor T3 is electrically connected to a source electrode of the second thin film transistor T2, and a source electrode of the third thin film transistor T3 is electrically connected to the fifth common electrode SCOM.

Further, when the first pixel unit 111 and the second pixel unit 112 together form an 8-domain (8 domain) pixel unit structure, the circuit structure between the first pixel unit 111 and the second pixel unit 112 may be, but is not limited to, a circuit structure further including a third thin film transistor T3 and a fifth common electrode SCOM.

Specifically, the gate electrode of the third thin film transistor T3 is electrically connected to the third gate line 133 (GL 3). The drain electrode of the third thin film transistor T3 is electrically connected to the source electrode of the second thin film transistor T2, and the third thin film transistor T3 may be, but is not limited to being, electrically connected to the second storage capacitor 122 (CST 2) and electrically connected to one end of the second thin film transistor T2.

The fifth common electrode SCOM may be, but is not limited to, a (SCOM), and the fifth common electrode SCOM may be, but is not limited to, a source electrode electrically connected to the third thin film transistor T3, and provides a ground signal to the third thin film transistor T3.

In this embodiment, when the third gate line 133 (GL 3) transmits the gate signals to the first pixel unit 111 and the second pixel unit 112, the first capacitance value of the first storage capacitor 121 (CST 1) and the second capacitance value of the second storage capacitor 122 (CST 2) are not identical due to the third thin film transistor T3 and the fifth common electrode SCOM, so that the first pixel unit 111 (main_pixel) and the second pixel unit 112 (sub_pixel) are different in brightness, and the display panel 10 has a better display effect and a wider viewing angle.

Please refer to fig. 9 again. The embodiment of the utility model further provides a display device 1, the display device 1 includes a backlight module 20 and the display panel 10, and the backlight module 20 is used for providing a surface light source for the display panel 10.

The display device 1 may be, but is not limited to, a thin film transistor liquid crystal display device 1 (Thin Film Transistor Liquid Crystal Display, TFT-LCD), a sub-millimeter light emitting diode (Mini Light Emitting Diode, mini LED) display device 1, a Micro light emitting diode (Micro Light Emitting Diode, micro LED) display device 1, or the like, and it is understood that the display device 1 may be a display device 1 of other structures.

The display device 1 may be, but is not limited to, a device having a display function applied to a smart phone, a portable phone, a navigation device, a Television (TV), a car audio body, a laptop, a tablet, a Portable Multimedia Player (PMP), a Personal Digital Assistant (PDA), and the like, and it is understood that an application scenario of the display device 1 should not be limited to the display device 1 provided in this embodiment.

The backlight module 20 may be, but is not limited to, disposed away from the display surface of the display panel 10, and provides a surface light source to the display panel 10.

In the display device 1 according to the embodiment of the present utility model, the display panel 10 includes the first storage capacitor 121 (CST 1) and the second storage capacitor 122 (CST 2) that are different in magnitude by adjusting the first capacitance, so that different brightness effects are displayed between the first pixel unit 111 and the second pixel unit 112, and further, the display panel 10 and the display device 1 can have a wider viewing angle, thereby improving the user experience.

Reference in the specification to "an embodiment," "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the described embodiments of the utility model may be combined with other embodiments. Furthermore, it should be understood that the features, structures or characteristics described in the embodiments of the present utility model may be combined arbitrarily without any conflict with each other, to form yet another embodiment without departing from the spirit and scope of the present utility model.

Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present utility model and not for limiting the same, and although the present utility model has been described in detail with reference to the above-mentioned preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present utility model without departing from the spirit and scope of the technical solution of the present utility model.

Claims

1. An array substrate, characterized in that the array substrate comprises:

2. The array substrate of claim 1, further comprising a gate line group including a first gate line electrically connected to a gate of the first thin film transistor and transmitting a first gate signal to the first thin film transistor, and a second gate line electrically connected to a gate of the second thin film transistor and transmitting a second gate signal to the second thin film transistor, the first gate signal and the second gate signal being used to control the first thin film transistor and the second thin film transistor to be turned on simultaneously.

3. The array substrate of claim 2, wherein the first gate line and the second gate line are electrically connected to a same control signal terminal.

4. The array substrate of claim 2, further comprising a first liquid crystal capacitor electrically connected to the source of the first thin film transistor and a second liquid crystal capacitor electrically connected to the source of the second thin film transistor.

5. The array substrate of claim 1, further comprising:

6. The array substrate of claim 5, wherein an area of the first common electrode is greater than or less than an area of the second common electrode.

7. A display panel, comprising a color film substrate, a liquid crystal layer and an array substrate according to any one of claims 1 to 6, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.

8. The display panel of claim 7, wherein the display panel further comprises:

9. The display panel of claim 8, wherein the third common electrode and the fourth common electrode are disposed on the color film substrate, and an area of the third common electrode is equal to an area of the fourth common electrode.

10. A display device, wherein the display device comprises a backlight module and the display panel according to claim 7, and the backlight module is used for providing a surface light source for the display panel.