CN219978417U - Virtual soldering detection circuit of chip IO point - Google Patents
Virtual soldering detection circuit of chip IO point Download PDFInfo
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- CN219978417U CN219978417U CN202223415524.6U CN202223415524U CN219978417U CN 219978417 U CN219978417 U CN 219978417U CN 202223415524 U CN202223415524 U CN 202223415524U CN 219978417 U CN219978417 U CN 219978417U
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- 238000001514 detection method Methods 0.000 title claims abstract description 25
- 230000003321 amplification Effects 0.000 claims abstract description 47
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 47
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 238000003466 welding Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The utility model relates to the technical field of welding spot detection, and discloses a virtual welding detection circuit of a chip IO point, which comprises a constant current source unit, a differential amplification unit, a first comparison unit, a second comparison unit and a light-emitting diode, wherein the constant current source unit comprises a reference voltage generation unit and a load unit; when in actual use, the first input end and the second input end of the differential amplifying unit are connected to two nodes to be detected, and the virtual welding detection can be realized through whether the light emitting diode is lightened or not, so that the operation is simple and convenient, the efficiency is high, and the cost is low because large-scale test equipment is not needed; in addition, the virtual welding detection is realized by detecting the connection states of the two ends of the diode, so that the virtual welding detection device can be used for detecting whether the diode on the circuit is abnormal or not, and the practicability is high.
Description
Technical Field
The utility model relates to the technical field of welding spot detection, in particular to a virtual welding detection circuit of a chip IO point.
Background
For electronic products, circuit boards are an important component, and circuits on the circuit boards are the main bodies for realizing functions. However, if the connection relation of the devices of the circuit is abnormal, the normal use of the circuit is affected. For example, if the IO point of the control chip is in a cold joint, the IO point of the chip cannot be normally connected with an external device, and thus the IO point of the chip cannot drive an external load or cannot receive a signal input by the external device.
For circuit board manufacturers, because the quality of the circuit board needs to be ensured, large-scale test equipment is adopted to test the circuit board after the circuit board is produced, so that abnormal circuit boards are deleted. However, for the circuit debugging engineer, due to the lack of special detection equipment, if the connection abnormality occurs between the IO port of the chip on the circuit board and the external device, the debugging engineer can hardly detect the suspected cold joint in time.
Referring to fig. 1, the IO structure of the conventional chip includes a diode D1 and a diode D2, a connection point of the IO structure and the circuit board, i.e., a Y point, is electrically connected to an anode of the diode D1 and a cathode of the diode D2, the cathode of the diode D1 is connected to a power source VCC, and the anode of the diode D2 is grounded, so that whether a dummy solder exists at a connection point of the IO interface of the chip and the circuit board can be detected by detecting a diode characteristic of the diode D1 and a diode characteristic of the diode D2.
Disclosure of Invention
In view of the shortcomings of the background technology, the utility model provides a virtual bonding detection circuit for IO points of a chip, which detects whether the IO points of the chip are virtual bonding or not by detecting whether the characteristics of diodes in the IO structure of the chip are normal or not.
In order to solve the technical problems, the utility model provides the following technical scheme: the virtual welding detection circuit of the chip IO point comprises a constant current source unit, a differential amplification unit, a first comparison unit, a second comparison unit and a light emitting diode, wherein the constant current source unit comprises a reference voltage generation unit and a load unit, and the reference voltage output by the reference voltage generation unit is input to the load unit so that the load unit generates constant current;
the first input end of the differential amplifying unit is configured to input a set voltage, the second input end of the differential amplifying unit is electrically connected with the reference voltage generating unit, and the reference voltage output by the reference voltage generating unit is used as a differential amplifying input; the output end of the differential amplification unit is electrically connected with the first input end of the first comparison unit and the first input end of the second comparison unit respectively, the second input end of the first comparison unit is configured to input a second reference voltage, the second input end of the second comparison unit is configured to input a third reference voltage, the output end of the first comparison unit is electrically connected with the negative electrode of the light emitting diode, and the output end of the second comparison unit is electrically connected with the positive electrode of the light emitting diode.
In one embodiment, the reference voltage generating unit includes a voltage dividing unit and an operational amplifying unit, the voltage dividing unit includes an input terminal, a voltage dividing terminal and a ground terminal, the input terminal is configured to be connected to a power source, the voltage dividing terminal is electrically connected to the operational amplifying unit, and the operational amplifying unit amplifies a voltage of the voltage dividing terminal and outputs a reference voltage.
Further, the operational amplification unit is a voltage follower.
In an embodiment, the load unit includes a resistor R10, the reference voltage output by the reference voltage generating unit is input to one end of the resistor R10, and the other end of the resistor R10 is grounded.
In one embodiment, the first input terminal of the differential amplifying unit is electrically connected to one section of a resistor R2, and the other end of the resistor R2 is configured to be connected to a power supply.
In a certain embodiment, the differential amplifying unit includes a second operational amplifying unit, a third operational amplifying unit, a fourth operational amplifying unit, a resistor R3, and a resistor R5;
the positive input end of the second operational amplification unit is configured to input the set voltage, and the output end of the second operational amplification unit is electrically connected with the positive input end of the fourth operational amplification unit through a resistor R3;
the positive input end of the third operational amplification unit is electrically connected with the reference voltage generation unit, the output end of the third operational amplification unit is electrically connected with the negative input end of the fourth operational amplification unit through a resistor R5, and the output end of the fourth operational amplification unit is the output end of the differential amplification unit.
Further, the second operational amplifying unit and the third operational amplifying unit are both voltage followers.
In an embodiment, the second input end of the first comparing unit is electrically connected to a second voltage dividing unit, the second voltage dividing unit includes a second input end, a second voltage dividing end and a second grounding end, the second input end is configured to be connected to a power supply, the second voltage dividing end is electrically connected to the second input end of the first comparing unit, and the second grounding end is grounded.
In a certain embodiment, the second input end of the second comparing unit is electrically connected to a third voltage dividing unit, the third voltage dividing unit includes a third input end, a third voltage dividing end and a third grounding end, the third input end is configured to be connected to a power supply, the third voltage dividing end is electrically connected to the second input end of the second comparing unit, and the third grounding end is grounded.
In practical use, the first input end and the second input end of the differential amplifying unit are respectively and electrically connected with the Y node and the VCC end in fig. 1, or the first input end and the second input end of the differential amplifying unit are respectively and electrically connected with the GND end and the Y node in fig. 1, and taking the first connection mode of this section of content as an example, after the power supply is connected to the present utility model, if the connection states of the Y node and the VCC end are inconsistent, the differential voltage input by the differential amplifying unit is also inconsistent, the output voltage of the differential amplifying unit is also inconsistent, and the output voltage of the differential amplifying unit is compared by the first comparing unit and the second comparing unit, so that the light emitting diode can display different states when the connection between the Y node and the VCC end is normal and when the connection between the Y node and the VCC end is abnormal (open circuit and short circuit occur), thereby realizing the detection of the cold joint.
Compared with the prior art, the utility model has the following beneficial effects: when in actual use, the first input end and the second input end of the differential amplifying unit are connected to two nodes to be detected, and the virtual welding detection can be realized through whether the light emitting diode is lightened or not, so that the operation is simple and convenient, the efficiency is high, and the cost is low because large-scale test equipment is not needed; in addition, the virtual welding detection is realized by detecting the connection states of the two ends of the diode, so that the virtual welding detection device can be used for detecting whether the diode on the circuit is abnormal or not, and the practicability is high.
Drawings
FIG. 1 is a schematic diagram of an IO structure of a conventional chip;
FIG. 2 is a block diagram of the present utility model in an embodiment;
fig. 3 is a circuit diagram of the constant current source unit in the embodiment;
fig. 4 is a circuit diagram of a differential amplifying unit in the embodiment;
fig. 5 is a circuit diagram of the first comparing unit, the second voltage dividing unit, and the third voltage dividing unit in the embodiment.
Detailed Description
The utility model will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the utility model and therefore show only the structures which are relevant to the utility model.
As shown in fig. 2, a dummy solder detection circuit for a chip IO point includes a constant current source unit 1, a differential amplifying unit 2, a first comparing unit 3, a second comparing unit 4, and a light emitting diode LED1, wherein the constant current source unit 1 includes a reference voltage generating unit 10 and a load unit 11, and a reference voltage output by the reference voltage generating unit 10 is input to the load unit 11 to cause the load unit 11 to generate a constant current;
a first input terminal of the differential amplifying unit 2 is configured to input a set voltage, a second input terminal of the differential amplifying unit 2 is electrically connected with the reference voltage generating unit 10, and a reference voltage output by the reference voltage generating unit 10 is used as a differential amplifying input; the output end of the differential amplifying unit 2 is electrically connected with the first input end of the first comparing unit 3 and the first input end of the second comparing unit 4 respectively, the second input end of the first comparing unit 3 is configured to input the second reference voltage, the second input end of the second comparing unit 4 is configured to input the third reference voltage, the output end of the first comparing unit 3 is electrically connected with the cathode of the light emitting diode LED1, and the output end of the second comparing unit 4 is electrically connected with the anode of the light emitting diode LED 1.
In actual use, taking fig. 1 as an example, when it is required to detect whether there is a cold joint at the IO point of the chip, if it is the detection diode D1, the Y point is electrically connected to the first input terminal of the differential amplifying unit 2, the VCC terminal is electrically connected to the second input terminal of the differential amplifying unit 2, if it is the detection diode D2, the GND terminal is electrically connected to the first input terminal of the differential amplifying unit 2, and the Y point is electrically connected to the second input terminal of the differential amplifying unit 2.
Taking the first connection mode as an example, a set voltage is provided to the first input terminal of the differential amplifying unit 2, when the Y point and the VCC point are connected to the first input terminal and the second input terminal of the differential amplifying unit 2, if the Y point and the VCC point are connected normally, the first input terminal of the differential amplifying unit 2 is electrically connected through the diode D1 and the load unit 11, since the current flowing through the load unit 11 is constant, the current flowing through the diode D1 is constant, the voltage difference value of the input of the differential amplifying unit 2 is the voltage drop of the diode D1, assuming that the voltage drop of the diode D1 is Vba, the value of Vba is related to the material of the diode D1 at this time, if the diode D1 is a silicon tube, vba is between 0.5V and 0.7V, if the diode D1 is a germanium tube, vba is between 0.1V and 0.3V, and the output voltage amplitude of the differential amplifying unit 2 is in the first state;
if the Y point is connected with the VCC end and short-circuited, the input voltage difference value of the differential amplification unit 2 is 0V, and the output voltage amplitude of the differential amplification unit 2 is in a second state;
if the connection of the Y point and the VCC end is broken, the voltage difference value of the input of the differential amplifying unit 2 is the difference value between the set voltage and the reference voltage, and the output voltage amplitude of the differential amplifying unit 2 is in a third state;
therefore, when the Y-point is different from the connection state of the VCC terminal, the output voltage amplitude of the differential amplifying unit 2 is different. By setting the first comparing unit 3 and the second comparing unit 4 to compare the output voltages of the differential amplifying unit 2, the light emitting diode LED1 can display different states when the connection between the Y node and the VCC terminal is normal and when the connection between the Y node and the VCC terminal is abnormal (open circuit and short circuit occur), thereby realizing the detection of the cold joint.
The following is a detailed description of the circuitry shown in fig. 3, 4 and 5.
As shown in fig. 3, the reference voltage generating unit 10 includes a voltage dividing unit 100 and an operational amplifying unit 101.
The voltage unit 100 includes a resistor R4 and a resistor R5, wherein one end of the resistor R4 connected with the resistor R5 is a voltage division end of the voltage division unit, the voltage division end is electrically connected with the operational amplification unit 101, the other end of the resistor R4 is an input end, the input end is configured to be connected with a power supply VDD, in this embodiment, the voltage of the power supply VDD is 3.3V, the voltage is provided by a battery B1, the other end of the resistor R5 is a ground end, and the ground end is grounded.
The operational amplifier unit 101 includes an operational amplifier U3, a resistor R6, and a MOS transistor Q1, and the operational amplifier U3, the resistor R6, and the MOS transistor Q1 form a voltage follower.
In actual use, the power supply VDD is divided by the resistor R4 and the resistor R7 and then input to the operational amplifier U3, and the output voltage of the operational amplifier U3 generates a constant current on the resistor R10, wherein the calculation formula of the constant current I is as follows: i=vref 1/R10
VREF1＝VDD*R7/(R4+R7)
I＝VDD*R7/((R4+R7)*R10)
The magnitude of the current I can be adjusted by adjusting the resistance values of the resistor R4 and the resistor R7, in this embodiment, i=0.946 mA.
Referring to fig. 4, in the present embodiment, the differential amplifying unit 2 includes a second operational amplifying unit 20, a third operational amplifying unit 21, a fourth operational amplifying unit 22, a resistor R1, and a resistor R3;
the positive input end of the second operational amplification unit 20 is configured to input a set voltage, and the output end of the second operational amplification unit 20 is electrically connected with the positive input end of the fourth operational amplification unit 22 through a resistor R3;
the positive input end of the third operational amplification unit 21 is electrically connected with the reference voltage generation unit 10, the output end of the third operational amplification unit 21 is electrically connected with the negative input end of the fourth operational amplification unit 22 through a resistor R5, and the output end of the fourth operational amplification unit is the output end of the differential amplification unit.
Specifically, in the present embodiment, the positive input terminal of the second operational amplification unit 20 is electrically connected to the power supply VDD through the resistor R2, the power supply VDD supplies the setting voltage to the second operational amplification unit 20 through the resistor R2, and the power supply VDD is supplied by the battery B1 and is 3.3V.
Specifically, in the present embodiment, the second operational amplification unit 20 and the third operational amplification unit 21 are both voltage followers.
Specifically, in this embodiment, the fourth operational amplification unit 22 includes an operational amplifier U2, a resistor R1 and a resistor R9, the positive electrode of the operational amplifier U2 is the positive input end of the fourth operational amplification unit 22, the positive input end of the operational amplifier U2 is grounded through the resistor R1, and the negative input end of the operational amplifier U2 is electrically connected to the output end of the operational amplifier U2 through the resistor R9.
In this embodiment, assuming that the amplification ratio of the differential amplification unit 2 is 1 and the output voltage of the differential amplification unit 2 is Vg, since the current I flowing through the resistor R11 is set to 0.946mA, when the Y-point is normally connected to the VCC terminal according to the volt-ampere characteristic curve of the diode D1, the voltage drop Vba generated by the current I on the diode D1 is between 0.096V and 0.996V, no matter the diode D1 is a silicon tube or a germanium tube, at this time, the voltage difference of the input voltage of the differential amplification unit 2 is between 0.096V and 0.996V, and the voltage Vg is also between 0.096V and 0.996V;
when the Y point is short-circuited with the VCC end, the voltage difference value input by the differential amplification unit 2 is 0V, and Vg is 0V;
when the Y point is short-circuited with the VCC terminal, the voltage difference value input by the differential amplifying unit 2 is Vb-Va and 3.3V, and the voltage output by the differential amplifying unit 2 is 3.3V.
Referring to fig. 5, in the present embodiment, the second input end of the first comparing unit 3 is electrically connected to the second voltage dividing unit 5, the second voltage dividing unit 5 includes a resistor R8 and a resistor R11, one end of the resistor R8 electrically connected to the resistor R11 is the second voltage dividing end, the second voltage dividing end is electrically connected to the second input end of the first comparing unit 3, the other end of the resistor R8 is the second input end, the second input end is electrically connected to the power VDD, the other end of the resistor R11 is the second ground end, and the second ground end is grounded.
In practical use, the power supply VDD is divided by the resistor R8 and the resistor R11 to provide the second reference voltage VREF2 to the first comparing unit 3, and in this embodiment, the second reference voltage VREF2 is set to be 0.996V according to the maximum voltage drop of the diode D1.
The second input end of the second comparison unit 4 is electrically connected with a third voltage division unit 6, the third voltage division unit comprises a resistor R12 and a resistor R14, one end of the resistor R12, which is electrically connected with the resistor R14, is a third voltage division end, the third voltage division end is electrically connected with the second input end of the second comparison unit 6, the other end of the resistor R12 is a third input end, the second input end is electrically connected with a power supply VDD, the other end of the resistor R14 is a third grounding end, and the third grounding end is grounded.
In practical use, the power supply VDD is divided by the resistor R12 and the resistor R14 to provide the third reference voltage VREF3 to the second comparing unit 4, and in this embodiment, the third reference voltage VREF3 is set to be 0.096V according to the minimum voltage drop of the diode D1.
The cold joint detection display state of the present utility model will now be described:
according to the circuit arrangement of fig. 3, 4 and 5, the current I flowing through the resistor R10 is 0.946mA, and for fig. 1, when the Y-point is normally connected to the VCC terminal, the voltage drop Vba generated by the current I on the diode D1 is between 0.096V and 0.996V, the second reference voltage VREF2 is 0.996V, and the third reference voltage VREF3 is 0.096V.
When the first input end of the differential amplification unit 2 is electrically connected with the Y point and the second input end of the differential amplification unit is electrically connected with the VCC end, if the Y point is normally connected with the VCC end, vg is between 0.096V and 0.996V, then the first comparison unit 3 outputs a low-level signal, the second comparison unit 4 outputs a high-level signal, and the light emitting diode LED1 lights to prompt;
if the Y point is short-circuited with the VCC end, vg is 0V, the first comparison unit 3 outputs a low-level signal, the second comparison unit 4 outputs a low-level signal, and the light emitting diode LED1 does not lighten;
if the Y point is disconnected from the VCC terminal, vg is 3.3V, the first comparing unit 3 outputs a high level signal, the second comparing unit 4 outputs a high level signal, and the light emitting diode LED1 does not illuminate.
Therefore, whether the connection state between the Y point and the VCC end is normal or not can be detected by the lighting of the light emitting diode LED1, and the principle of detecting the connection state between the GND end and the Y point is the same as above.
In summary, in practical use, the first input end and the second input end of the differential amplification unit 2 are connected to two nodes to be detected, and the virtual welding detection can be realized by whether the light emitting diode LED1 is lightened or not, so that the operation is simple and convenient, the efficiency is high, and the cost is low because large-scale test equipment is not needed; in addition, the virtual welding detection is realized by detecting the connection states of the two ends of the diode, so that the virtual welding detection device can be used for detecting whether the diode on the circuit is abnormal or not, and the practicability is high.
The present utility model has been made in view of the above-described circumstances, and it is an object of the present utility model to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present utility model. The technical scope of the present utility model is not limited to the description, but must be determined according to the scope of claims.
Claims (9)
1. The virtual welding detection circuit of the chip IO point is characterized by comprising a constant current source unit, a differential amplification unit, a first comparison unit, a second comparison unit and a light emitting diode, wherein the constant current source unit comprises a reference voltage generation unit and a load unit, and the reference voltage output by the reference voltage generation unit is input to the load unit so that the load unit generates constant current;
the first input end of the differential amplifying unit is configured to input a set voltage, the second input end of the differential amplifying unit is electrically connected with the reference voltage generating unit, and the reference voltage output by the reference voltage generating unit is used as a differential amplifying input; the output end of the differential amplification unit is electrically connected with the first input end of the first comparison unit and the first input end of the second comparison unit respectively, the second input end of the first comparison unit is configured to input a second reference voltage, the second input end of the second comparison unit is configured to input a third reference voltage, the output end of the first comparison unit is electrically connected with the negative electrode of the light emitting diode, and the output end of the second comparison unit is electrically connected with the positive electrode of the light emitting diode.
2. The circuit for detecting the cold joint of the chip IO point according to claim 1, wherein the reference voltage generating unit comprises a voltage dividing unit and an operational amplifying unit, the voltage dividing unit comprises an input end, a voltage dividing end and a grounding end, the input end is configured to be connected with a power supply, the voltage dividing end is electrically connected with the operational amplifying unit, and the operational amplifying unit amplifies the voltage of the voltage dividing end and outputs the reference voltage.
3. The circuit of claim 2, wherein the operational amplifier unit is a voltage follower.
4. The circuit according to claim 1, wherein the load unit comprises a resistor R10, the reference voltage output from the reference voltage generating unit is input to one end of the resistor R10, and the other end of the resistor R10 is grounded.
5. The circuit of claim 1, wherein the first input terminal of the differential amplifying unit is electrically connected to a section of a resistor R2, and the other end of the resistor R2 is configured to be connected to a power supply.
6. The circuit for detecting a cold joint at a chip IO point according to any one of claims 1 to 5, wherein the differential amplifying unit includes a second operational amplifying unit, a third operational amplifying unit, a fourth operational amplifying unit, a resistor R3, and a resistor R5;
the positive input end of the second operational amplification unit is configured to input the set voltage, and the output end of the second operational amplification unit is electrically connected with the positive input end of the fourth operational amplification unit through a resistor R3;
the positive input end of the third operational amplification unit is electrically connected with the reference voltage generation unit, the output end of the third operational amplification unit is electrically connected with the negative input end of the fourth operational amplification unit through a resistor R5, and the output end of the fourth operational amplification unit is the output end of the differential amplification unit.
7. The circuit of claim 6, wherein the second and third operational amplifier units are voltage followers.
8. The circuit of claim 1, wherein the second input terminal of the first comparing unit is electrically connected to a second voltage dividing unit, the second voltage dividing unit includes a second input terminal, a second voltage dividing terminal, and a second ground terminal, the second input terminal is configured to be connected to a power supply, the second voltage dividing terminal is electrically connected to the second input terminal of the first comparing unit, and the second ground terminal is grounded.
9. The circuit of claim 1, wherein the second input terminal of the second comparing unit is electrically connected to a third voltage dividing unit, the third voltage dividing unit includes a third input terminal, a third voltage dividing terminal, and a third ground terminal, the third input terminal is configured to be connected to a power supply, the third voltage dividing terminal is electrically connected to the second input terminal of the second comparing unit, and the third ground terminal is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223415524.6U CN219978417U (en) | 2022-12-20 | 2022-12-20 | Virtual soldering detection circuit of chip IO point |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223415524.6U CN219978417U (en) | 2022-12-20 | 2022-12-20 | Virtual soldering detection circuit of chip IO point |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219978417U true CN219978417U (en) | 2023-11-07 |
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ID=88579461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223415524.6U Active CN219978417U (en) | 2022-12-20 | 2022-12-20 | Virtual soldering detection circuit of chip IO point |
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| Country | Link |
|---|---|
| CN (1) | CN219978417U (en) |
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2022
- 2022-12-20 CN CN202223415524.6U patent/CN219978417U/en active Active
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