CN219875098U - Chip power supply circuit and operation circuit - Google Patents
Chip power supply circuit and operation circuit Download PDFInfo
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- CN219875098U CN219875098U CN202321023160.9U CN202321023160U CN219875098U CN 219875098 U CN219875098 U CN 219875098U CN 202321023160 U CN202321023160 U CN 202321023160U CN 219875098 U CN219875098 U CN 219875098U
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- 239000003990 capacitor Substances 0.000 claims abstract description 258
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Abstract
The utility model provides a chip power supply circuit and an operation circuit. The chip power supply circuit comprises a direct current power supply circuit and at least two capacitor banks. At least two capacitor banks are connected in series. At least two capacitance sets correspond to a plurality of voltage domains. One end of at least two capacitor banks connected in series is connected with a direct current power supply circuit. Each of the at least two capacitor banks includes at least one capacitor. The utility model improves the operation performance of the operation chip.
Description
Technical Field
The present utility model relates to the field of electronic circuits, and in particular, but not exclusively, to a chip power supply circuit and an arithmetic circuit.
Background
The arithmetic chip is usually powered by a direct current circuit. The operational chip in operation generates voltage ripple. When the voltage ripple is large, the operation performance of the chip is affected. In particular, in the case of supplying power to a plurality of operation chips, voltage ripples of the operation chips may be superimposed, resulting in larger voltage ripples.
In view of this, the problem of the present utility model is how to effectively suppress the voltage ripple of the operation chip.
Disclosure of Invention
The utility model provides a chip power supply circuit and an operation circuit, which are used for inhibiting voltage ripple so as to improve the operation performance of an operation chip.
In a first aspect, the present utility model provides a chip power supply circuit. The chip power supply circuit comprises a direct current power supply circuit and at least two capacitor banks. At least two capacitor banks are connected in series. At least two capacitance sets correspond to a plurality of voltage domains. One end of at least two capacitor banks connected in series is connected with a direct current power supply circuit. Each of the at least two capacitor banks includes at least one capacitor.
In some possible embodiments, one of the at least two capacitor banks may comprise a plurality of capacitors. The plurality of capacitors are connected in parallel.
In some possible embodiments, each capacitor bank can be connected in parallel with an arithmetic chip. The arithmetic chip operates in a voltage domain corresponding to each capacitor bank.
In some possible embodiments, the at least two capacitor banks may include a first capacitor bank and a second capacitor bank. The first end of the first capacitor bank is connected with the direct current power supply circuit. The second end of the first capacitor bank is connected to the first end of the second capacitor bank.
In some possible embodiments, the number of at least one capacitor in each capacitor bank may be determined by the magnitude of the voltage variation allowed by the arithmetic chip to which each capacitor bank is capable of being connected in parallel, the magnitude of the current ripple of the arithmetic chip, the frequency of the current ripple, and the impedance of the capacitors in each capacitor bank at the frequency of the current ripple.
In some possible embodiments, the number of at least one capacitor in each capacitor bank may be determined by the following formula: n=u/(a×r (K)); where N represents the number of at least one capacitor, U represents the magnitude of the voltage variation allowed by the operation chip, a represents the magnitude of the current ripple of the operation chip, K represents the frequency of the current ripple, and r (K) represents the impedance of each capacitor in each capacitor bank at the frequency K of the current ripple. At least one capacitor in each capacitor bank has equal impedance at the frequency of the current ripple.
In some possible embodiments, the number of the at least one capacitor in each capacitor bank may be determined by the magnitude of the voltage variation allowed by the arithmetic chip to which each capacitor bank can be connected in parallel, the magnitude of the current ripple of the arithmetic chip, the frequency of the current ripple, and the capacitance of the respective capacitors in each capacitor bank.
In some possible embodiments, the number of at least one capacitor in each capacitor bank may be determined by the following formula: n=a/(u×k×c (K)); where N represents the number of at least one capacitor, U represents the magnitude of the voltage variation allowed by the operation chip, a represents the magnitude of the current ripple of the operation chip, K represents the frequency of the current ripple, and C (K) represents the capacitance of each capacitor in each capacitor bank at the frequency K of the current ripple. At least one capacitor in each capacitor bank has equal capacitance at the frequency of the current ripple.
In a second aspect, the present utility model provides an arithmetic circuit. The arithmetic circuit comprises a plurality of arithmetic chips and a chip power supply circuit as described in the first aspect. The plurality of arithmetic chips includes at least two arithmetic chip sets. At least two operation chip sets are connected in series. Each of the at least two capacitor banks in the chip power supply circuit is connected in parallel with one of the at least two operation chip banks.
In some possible implementations, at least a plurality of the arithmetic chips operate in a plurality of voltage domains.
In the utility model, at least two capacitor banks which are connected in series are arranged in the chip power supply circuit and correspond to a plurality of voltage domains respectively, so that at least part of alternating current components in direct current power supply current of an operation chip can be filtered through the filtering action of each capacitor bank, thereby realizing the suppression of voltage ripple between adjacent voltage domains.
In addition, the chip power supply circuit can realize power supply to a plurality of operation chips by adopting a serial power supply mode only by using one direct current power supply circuit. On the one hand, the reduction of the number of the direct current power supply circuits saves the complexity of peripheral circuits of an operation chip, and reduces the design cost and the manufacturing cost. On the other hand, the serial connection of the plurality of arithmetic chips requires a significant increase in the output voltage of the dc power supply circuit, thereby improving the energy conversion efficiency of the dc power supply circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and together with the description, serve to explain the principles of the utility model.
Fig. 1 is a schematic diagram of a chip power supply circuit adopting a parallel power supply mode in the related art.
Fig. 2 is a schematic diagram of a first embodiment of a chip power supply circuit according to an embodiment of the utility model.
Fig. 3 is a schematic diagram of a first exemplary embodiment of a chip power supply circuit in an embodiment of the utility model.
Fig. 4 is a schematic diagram of a second exemplary embodiment of a chip power supply circuit in an embodiment of the utility model.
Fig. 5 is a schematic diagram of a third exemplary embodiment of a chip power supply circuit in an embodiment of the utility model.
Fig. 6 is a schematic diagram of a second embodiment of a chip power supply circuit according to an embodiment of the utility model.
Fig. 7 is a schematic diagram of a fourth exemplary embodiment of a chip power supply circuit in an embodiment of the utility model.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the architecture, devices, and techniques in order to provide a thorough understanding of the embodiments of the present utility model. It will be apparent, however, to one skilled in the art that the present utility model may be practiced in other embodiments, which depart from these specific details. In other instances, detailed descriptions of well-known structures, devices, and methods are omitted so as not to obscure the description of the embodiments of the present utility model with unnecessary detail.
The arithmetic chip is usually powered by a direct current circuit. In operation, signal inversion and intermittent operation in the operation chip cause large current fluctuation, so that voltage ripple occurs. When the voltage ripple is large, the operation performance of the operation chip is affected.
In the related art, a parallel power supply mode is often used to supply power to a plurality of operation chips. Fig. 1 is a schematic diagram of a chip power supply circuit adopting a parallel power supply mode in the related art. As shown in fig. 1, the chip power supply circuit 100 includes a plurality of dc power supply circuits 20. The plurality of dc power supply circuits 20 are respectively connected to the plurality of computing chips 10 to supply power to the corresponding computing chips 10. In the chip power supply circuit 100 shown in fig. 1, each of the dc power supply circuits 20 is configured to supply power to a single one of the arithmetic chips 10. The parallel power supply mode can reduce voltage ripple of the operation circuit to the greatest extent. However, since a plurality of dc power supply circuits are employed, the design cost and the manufacturing cost of the circuits are increased. In addition, when the voltage output by the dc power supply circuit is low, the energy conversion efficiency of the dc power supply circuit is also reduced, which in turn results in energy waste of the entire operation circuit.
In addition, in the case of supplying power to a plurality of arithmetic chips by a serial power supply method, the plurality of arithmetic chips are connected in series, and one direct current power supply circuit is used to supply power to the plurality of arithmetic chips. However, the series connection causes the voltage ripple of the operation chip to be amplified, which may seriously affect the operation performance of the operation chip.
In view of the above, the problem of the embodiments of the present utility model is how to effectively suppress the voltage ripple of the operation chip.
In order to solve the above problems, an embodiment of the present utility model provides a chip power supply circuit. The chip power supply circuit is capable of powering a plurality of chips in an electronic device. In practice, the chip power supply circuit may supply power to an arithmetic chip such as a central processing unit (central processing unit, CPU), a graphics processing unit (graphics processing unit, GPU). These arithmetic chips tend to have a large power and generate significant voltage ripple during operation. It should be noted that, the chip power supply circuit may also supply power to other types of chips, which is not particularly limited in the embodiment of the present utility model.
Fig. 2 is a schematic diagram of a first embodiment of a chip power supply circuit according to an embodiment of the utility model. As shown in fig. 2, the chip power supply circuit 200 includes a dc power supply circuit 20 and at least two capacitor banks 30. At least two capacitor banks 30 correspond to a plurality of voltage domains. One end of at least two capacitor banks 30 connected in series is connected to the dc power supply circuit 20. Each capacitor bank 30 of the at least two capacitor banks 30 comprises at least one capacitor 31.
Specifically, a first end of the first capacitor bank 30 is connected to the dc power supply circuit 20, and a second end of the first capacitor bank 30 is connected to a first end of the second capacitor bank 30; the second end of the second capacitor bank 30 is connected to the first end of the third capacitor bank 30; and so on, at least two capacitor banks 30 are connected in series in turn.
In one embodiment, the second end of the last capacitor bank 30 may be directly or indirectly grounded. For example, the second end of the last capacitor bank 30 may be electrically grounded. For another example, the second end of the last capacitor bank 30 may be grounded via a resistor or the like.
As shown in fig. 2, the chip power supply circuit 200 is used to supply power to a plurality of arithmetic chips 10. In one embodiment, each capacitor bank 30 may be used in parallel with one of the arithmetic chips 10. The number of capacitor banks 30 is equal to the number of arithmetic chips 10. The plurality of arithmetic chips 10 are connected in series and correspond to a plurality of voltage domains. Each of the arithmetic chips 10 operates in a corresponding voltage domain.
In an embodiment, the plurality of voltage domains may have the same or different voltage values. For example, the voltage values of the plurality of voltage domains are different from each other. For another example, the voltage values of at least two of the plurality of voltage domains are the same.
In an embodiment, the capacitor bank 30 may have one or more capacitors 31. For example, the capacitor bank 30 may have one capacitor 31. For another example, the capacitor bank 30 may have a plurality of capacitors 31. A plurality of capacitors 31 in the same capacitor bank 30 are connected in parallel. In an embodiment, the capacitors 31 in the capacitor bank 30 may have the same or different parameters. Parameters of capacitor 31 include, but are not limited to, capacitance, voltage rating, impedance. In general, parameters such as capacitance and impedance of the capacitor 31 change with a change in the operating frequency of the capacitor 31. For example, the parameters of the capacitors 31 in the capacitor bank 30 may be identical. As another example, the parameters of the capacitors 31 in the capacitor bank 30 may be partially identical. As another example, the parameters of the capacitors 31 in the capacitor bank 30 may be completely different.
In an embodiment, the number of capacitors 31 in different capacitor banks 30 may be the same or different. For example, different capacitor banks 30 may have different numbers of capacitors 31. As another example, different capacitor banks 30 may have the same number of capacitors 31.
In practical applications, the number of capacitors 31 in one capacitor bank 30 may be set as desired.
In an embodiment, the number of capacitors 31 in one capacitor bank 30 may be determined according to the following parameters: the magnitude of the voltage variation allowed by the operation chip 10 connected in parallel with the capacitor bank 30, the magnitude of the current fluctuation of the operation chip 10, the frequency of the current fluctuation, and the impedance of each capacitor 31 at the frequency of the current fluctuation.
In one example, the number of capacitors 31 may be determined in the following manner: the total impedance R of all the capacitors 31 in the capacitor bank 30 is calculated as follows: r=u/a, where U represents the magnitude of the voltage variation allowed by the operation chip 10, and a represents the magnitude of current fluctuation when the operation chip 10 operates; and, the number N of capacitors 31 in the capacitor bank 30 is calculated as follows: n=r/R (K); where r (K) represents the impedance of each capacitor 31 at the frequency K of the current ripple. In the above manner, the number of capacitors 31, i.e., n=u/(a×r (K)), can be determined. Note that the manner of calculating the number of capacitors 31 in this example is applicable to the case where the capacitors 31 in the capacitor bank 30 have the same impedance at the frequency K of the current fluctuation.
In an embodiment, the number of capacitors 31 in one capacitor bank 30 may be determined according to the following parameters: the magnitude of the voltage variation allowed by the operation chip 10 connected in parallel with the capacitor bank 30, the magnitude of the current fluctuation of the operation chip 10, the frequency of the current fluctuation, and the capacitance of each capacitor 31.
In one example, the number of capacitors 31 may be determined in the following manner: the charge amount Q required for current compensation of current fluctuation within the amplitude of voltage variation allowed by the operation chip 10 is calculated as follows: q=a/K, where a represents the amplitude of current fluctuation when the operation chip 10 operates, and K represents the frequency of current fluctuation when the chip 10 operates; calculating the total capacity C of the capacitor 31 required for current compensation of current ripple T The following are provided: c (C) T =q/U, where U represents the magnitude of the voltage variation allowed by the arithmetic chip 10; and, the number N of capacitors 31 in the capacitor bank 30 is calculated as follows: n=c T C, wherein C (K) represents the capacitance of each capacitor 31 at the frequency K of the current ripple. In the above manner, the number of capacitors 31, i.e., n=a/(u×k×c (K)), can be determined. Note that the manner of calculating the number of capacitors 31 in this example is applicable to the case where the capacitors 31 in the capacitor bank 30 have the same capacitance at the frequency K of the current fluctuation.
It will be appreciated that the magnitude of the voltage variation allowed by the arithmetic chip 10 connected in parallel with the capacitor bank 30 may be regarded as the magnitude of the voltage variation allowed in this voltage domain. In addition, the current ripple of the operation chip 10 may refer to the current ripple generated by the operation chip 10 when the chip power supply circuit 200 is used to supply power to the operation chip 10.
It should be noted that the number of the capacitors 31 in the capacitor bank 30 in the embodiment of the present utility model may be determined in other manners, which is not particularly limited in the embodiment of the present utility model.
In one embodiment, the DC power supply circuit 20 may be a DC-DC power supply circuit. The DC-DC power supply circuit is used for converting the electric energy of one voltage value into the electric energy of the other voltage value. The output voltage of the dc power supply circuit 20 may be the sum of voltages of the voltage domains where the plurality of operation chips 10 are located.
Fig. 3 is a schematic diagram of a first exemplary embodiment of a chip power supply circuit in an embodiment of the utility model. As shown in fig. 3, the chip power supply circuit 300 may include one dc power supply circuit 20 and two capacitor banks 30. The two capacitor banks 30 include a first capacitor bank 30A and a second capacitor bank 30B. The first capacitor bank 30A includes one capacitor 31. The second capacitor bank 30B includes one capacitor 31. A first terminal of the first capacitor bank 30A is connected to the dc power supply circuit 20. The first end of the second capacitor bank 30B is connected to the second end of the first capacitor bank 30A. A second terminal of the second capacitor bank 30B may be grounded (not shown). The chip power supply circuit 300 may be used to power two arithmetic chips 10. The two arithmetic chips 10 may be connected in series to the dc power supply circuit 20. The two arithmetic chips 10 include a first arithmetic chip 10A and a second arithmetic chip 10B. The first capacitor bank 30A is used for parallel connection with the first arithmetic chip 10A. The second capacitor bank 30B is used for parallel connection with the second arithmetic chip 10B. As such, the first arithmetic chip 10A can operate in a first voltage domain, and the second arithmetic chip 10B can operate in a second voltage domain.
Fig. 4 is a schematic diagram of a second exemplary embodiment of a chip power supply circuit in an embodiment of the utility model. As shown in fig. 4, the chip power supply circuit 400 may include one dc power supply circuit 20 and two capacitor banks 30. The two capacitor banks 30 include a first capacitor bank 30A and a second capacitor bank 30B. The first capacitor bank 30A includes two capacitors 31. The second capacitor bank 30B includes two capacitors 31. The two capacitors 31 in each capacitor bank 30 are connected in parallel. A first terminal of the first capacitor bank 30A is connected to the dc power supply circuit 20. The first end of the second capacitor bank 30B is connected to the second end of the first capacitor bank 30A. A second terminal of the second capacitor bank 30B may be grounded (not shown). The chip power supply circuit 400 may be used to power two arithmetic chips 10. The two arithmetic chips 10 may be connected in series to the dc power supply circuit 20. The two arithmetic chips 10 include a first arithmetic chip 10A and a second arithmetic chip 10B. The first capacitor bank 30A is used for parallel connection with the first arithmetic chip 10A. The second capacitor bank 30B is used for parallel connection with the second arithmetic chip 10B. As such, the first arithmetic chip 10A can operate in a first voltage domain, and the second arithmetic chip 10B can operate in a second voltage domain.
Fig. 5 is a schematic diagram of a third exemplary embodiment of a chip power supply circuit in an embodiment of the utility model. As shown in fig. 5, the chip power supply circuit 500 may include one dc power supply circuit 20 and three capacitor banks 30. The three capacitor banks 30 include a first capacitor bank 30A, a second capacitor bank 30B, and a third capacitor bank 30C. The first capacitor bank 30A includes one capacitor 31. The second capacitor bank 30B includes two capacitors 31. Two capacitors 31 in the second capacitor bank 30B are connected in parallel. The third capacitor bank 30C includes three capacitors 31. Three capacitors 31 in the third capacitor bank 30C are connected in parallel. A first terminal of the first capacitor bank 30A is connected to the dc power supply circuit 20. The first end of the second capacitor bank 30B is connected to the second end of the first capacitor bank 30A. The first end of the third capacitor bank 30C is connected to the second end of the second capacitor bank 30B. A second terminal of the third capacitor bank 30C may be grounded (not shown). The chip power supply circuit 500 may be used to power three arithmetic chips 10. Three arithmetic chips 10 may be connected in series to the dc power supply circuit 20. The three arithmetic chips 10 include a first arithmetic chip 10A, a second arithmetic chip 10B, and a third arithmetic chip 10C. The first capacitor bank 30A is used for parallel connection with the first arithmetic chip 10A. The second capacitor bank 30B is used for parallel connection with the second arithmetic chip 10B. The third capacitor bank 30C is used for parallel connection with the third arithmetic chip 10C. As such, the first arithmetic chip 10A can operate in a first voltage domain, the second arithmetic chip 10B can operate in a second voltage domain, and the third arithmetic chip 10C can operate in a third voltage domain.
In the embodiment shown in fig. 2 to 5, one arithmetic chip 10 operates in one voltage domain, and one capacitor bank 30 is used for parallel connection with one arithmetic chip 10. In some cases, one capacitor bank 30 may be used to connect in parallel with a plurality of the arithmetic chips 10.
Fig. 6 is a schematic diagram of a second embodiment of a chip power supply circuit according to an embodiment of the utility model. As shown in fig. 6, the chip power supply circuit 600 includes the dc power supply circuit 20 and at least two capacitor banks 30. At least two capacitor banks 30 correspond to a plurality of voltage domains. One end of at least two capacitor banks 30 connected in series is connected to the dc power supply circuit 20. Each capacitor bank 30 of the at least two capacitor banks 30 comprises at least one capacitor 31.
Specifically, a first end of the first capacitor bank 30 is connected to the dc power supply circuit 20, and a second end of the first capacitor bank 30 is connected to a first end of the second capacitor bank 30; the second end of the second capacitor bank 30 is connected to the first end of the third capacitor bank 30; and so on, at least two capacitor banks 30 are connected in series in turn.
In one embodiment, the second end of the last capacitor bank 30 may be directly or indirectly grounded. For example, the second end of the last capacitor bank 30 may be electrically grounded. For another example, the second end of the last capacitor bank 30 may be grounded via a resistor or the like.
As shown in fig. 6, the chip power supply circuit 600 is used to supply power to the plurality of arithmetic chips 10. In an embodiment, each capacitor bank 30 may be adapted to be connected in parallel with at least one of the arithmetic chips 10. For example, the number of capacitor banks 30 is smaller than the number of arithmetic chips 10. At least one capacitor bank 30 is used for parallel connection with the plurality of arithmetic chips 10. At least two capacitor banks 30 correspond to a plurality of voltage domains. At least one arithmetic chip 10 operates in each voltage domain.
In an embodiment, the plurality of voltage domains may have the same or different voltage values. For example, the voltage values of the plurality of voltage domains are different from each other. For another example, the voltage values of at least two of the plurality of voltage domains are the same.
It will be appreciated that the specific technical details of the chip power supply circuit 600 shown in fig. 6 may refer to the embodiments of fig. 1 to 5, and are not described herein.
Fig. 7 is a schematic diagram of a fourth exemplary embodiment of a chip power supply circuit in an embodiment of the utility model. As shown in fig. 7, the chip power supply circuit 700 may include one dc power supply circuit 20 and two capacitor banks 30. The two capacitor banks 30 include a first capacitor bank 30A and a second capacitor bank 30B. The first capacitor bank 30A includes two capacitors 31. The second capacitor bank 30B includes two capacitors 31. The two capacitors 31 in each capacitor bank 30 are connected in parallel. A first terminal of the first capacitor bank 30A is connected to the dc power supply circuit 20. The first end of the second capacitor bank 30B is connected to the second end of the first capacitor bank 30A. A second terminal of the second capacitor bank 30B may be grounded (not shown). The chip power supply circuit 700 may be used to power four arithmetic chips 10. The four arithmetic chips 10 may be connected in series to the dc power supply circuit 20. The four arithmetic chips 10 include two first arithmetic chips 10A and two second arithmetic chips 10B. The two first arithmetic chips 10A are connected in parallel. The two second arithmetic chips 10B are connected in parallel. The first capacitor bank 30A is used for parallel connection with the two first arithmetic chips 10A. The second capacitor bank 30B is used for parallel connection with the two second arithmetic chips 10B. As such, the two first arithmetic chips 10A can operate in the first voltage domain, and the two second arithmetic chips 10B can operate in the second voltage domain.
Based on the same concept, and with continued reference to fig. 2-7, an embodiment of the present utility model also provides an arithmetic circuit. The arithmetic circuit includes a plurality of arithmetic chips 10 and the chip power supply circuits 200, 300, 400, 500, 600, 700 provided in one or more of the embodiments described above. The plurality of operation chips 10 includes at least two operation chip sets 10A, 10B, 10C. At least two arithmetic chip sets 10A, 10B, 10C are connected in series. Each capacitor bank 30 of the at least two capacitor banks 30 in the chip power supply circuit 200, 300, 400, 500, 600, 700 is connected in parallel with an arithmetic chip set 10A, 10B, 10C.
In one embodiment, the plurality of arithmetic chips 10 operate in a plurality of voltage domains.
In the embodiment of the utility model, at least two capacitor banks which are connected in series are arranged in the chip power supply circuit and correspond to a plurality of voltage domains respectively, so that at least part of alternating current components in direct current power supply current of an operation chip can be filtered through the filtering action of each capacitor bank, and the suppression of voltage ripple between adjacent voltage domains is realized.
In addition, since the serial power supply mode is adopted, the chip power supply circuit in the embodiment of the utility model can realize power supply to a plurality of operation chips only by using one direct current power supply circuit. On the one hand, the reduction of the number of the direct current power supply circuits saves the complexity of peripheral circuits of an operation chip, and reduces the design cost and the manufacturing cost. On the other hand, the serial connection of the plurality of arithmetic chips requires a significant increase in the output voltage of the dc power supply circuit, thereby improving the energy conversion efficiency of the dc power supply circuit.
The above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the present utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, it will be appreciated by those skilled in the art that variations may be made to the embodiments described or equivalents may be substituted for elements thereof. Such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.
Claims (10)
1. A chip power supply circuit, comprising:
a direct current power supply circuit; and
at least two capacitor banks, wherein the at least two capacitor banks are connected in series, the at least two capacitor banks correspond to a plurality of voltage domains, one end of the at least two capacitor banks connected in series is connected with the direct current power supply circuit, and each of the at least two capacitor banks includes at least one capacitor.
2. The chip power supply circuit of claim 1, wherein one of the at least two capacitor banks comprises a plurality of capacitors connected in parallel.
3. The chip power supply circuit of claim 1, wherein each capacitor bank is connectable in parallel with an arithmetic chip operating in a voltage domain corresponding to each capacitor bank.
4. The chip power supply circuit of claim 1, wherein the at least two capacitor banks include a first capacitor bank and a second capacitor bank;
the first end of the first capacitor bank is connected with the direct current power supply circuit, and the second end of the first capacitor bank is connected with the first end of the second capacitor bank.
5. The chip power supply circuit according to any one of claims 1 to 4, wherein the number of the at least one capacitor in each capacitor bank is determined by the magnitude of voltage variation allowed by the arithmetic chip to which each capacitor bank can be connected in parallel, the magnitude of current fluctuation of the arithmetic chip, the frequency of the current fluctuation, and the impedance of each capacitor in each capacitor bank at the frequency of the current fluctuation.
6. The chip power supply circuit of claim 5, wherein the number of said at least one capacitor in each capacitor bank is determined by the following equation:
N＝U/(A×r(K))；
wherein N represents the number of the at least one capacitor, U represents the magnitude of the voltage variation allowed by the operation chip, a represents the magnitude of the current fluctuation of the operation chip, K represents the frequency of the current fluctuation, and r (K) represents the impedance of each capacitor in each capacitor group at the frequency K of the current fluctuation;
wherein the impedance of said at least one capacitor in each capacitor bank is equal at the frequency of said current ripple.
7. The chip power supply circuit according to any one of claims 1 to 4, wherein the number of the at least one capacitor in each capacitor bank is determined by the magnitude of voltage variation allowed by the operation chips to which each capacitor bank can be connected in parallel, the magnitude of current fluctuation of the operation chips, the frequency of the current fluctuation, and the capacitance of each capacitor in each capacitor bank.
8. The chip supply circuit of claim 7 wherein the number of said at least one capacitor in each capacitor bank is determined by the formula:
N＝A/(U×K×C(K))；
wherein N represents the number of the at least one capacitor, U represents the magnitude of the voltage variation allowed by the operation chip, a represents the magnitude of the current fluctuation of the operation chip, K represents the frequency of the current fluctuation, and C (K) represents the capacitance of each capacitor in each capacitor group at the frequency K of the current fluctuation;
wherein the capacitance of the at least one capacitor in each capacitor bank is equal at the frequency of the current ripple.
9. An arithmetic circuit, comprising:
a plurality of arithmetic chips, wherein the plurality of arithmetic chips comprises at least two arithmetic chip sets, the at least two arithmetic chip sets being connected in series; and
the chip supply circuit of any one of claims 1 to 8, wherein each of the at least two capacitor banks in the chip supply circuit is connected in parallel with one of the at least two arithmetic chipsets.
10. The arithmetic circuit of claim 9, wherein the plurality of arithmetic chips operate in a plurality of voltage domains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321023160.9U CN219875098U (en) | 2023-04-28 | 2023-04-28 | Chip power supply circuit and operation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321023160.9U CN219875098U (en) | 2023-04-28 | 2023-04-28 | Chip power supply circuit and operation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219875098U true CN219875098U (en) | 2023-10-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321023160.9U Active CN219875098U (en) | 2023-04-28 | 2023-04-28 | Chip power supply circuit and operation circuit |
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| CN (1) | CN219875098U (en) |
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- 2023-04-28 CN CN202321023160.9U patent/CN219875098U/en active Active
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