CN219873162U - Capacitor and capacitor module - Google Patents
Capacitor and capacitor module Download PDFInfo
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- CN219873162U CN219873162U CN202321042808.7U CN202321042808U CN219873162U CN 219873162 U CN219873162 U CN 219873162U CN 202321042808 U CN202321042808 U CN 202321042808U CN 219873162 U CN219873162 U CN 219873162U
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- capacitor
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- metal layer
- arrays
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- 239000003990 capacitor Substances 0.000 title claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000003491 array Methods 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000012545 processing Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 67
- 238000010586 diagram Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model provides a capacitor and a capacitor module, wherein the capacitor comprises: a substrate having a plurality of trench arrays in a front side of the substrate; the groove arrays are formed by arranging grooves at intervals along at least two different directions; the bottoms, the side walls and the surfaces of the substrates between the adjacent grooves are provided with dielectric layers; and the electrode layer is positioned on the surface of the dielectric layer and covers the bottoms and the side walls of the plurality of grooves and the surface of the substrate between the adjacent grooves. The capacitor provided by the utility model has the advantages that the front surface of the substrate of the capacitor is internally provided with the plurality of groove arrays which are arranged along different directions, the electrode layer is covered on the groove arrays, and the plurality of groove arrays which are arranged along different directions can realize larger capacitance in a limited area, can offset stress in the processing process and improve the success rate of capacitor processing.
Description
Technical Field
The present utility model relates to the field of semiconductor technologies, and in particular, to a capacitor and a capacitor module.
Background
Capacitors are a common basic element in electronic circuits for energy storage, filtering, bypass, coupling, decoupling, etc. Silicon capacitors have better stability due to the use of silicon materials compared to conventional capacitors such as tantalum capacitors and multilayer ceramic capacitors (MLCCs, multilayer Ceramic Capacitor). Meanwhile, the silicon capacitor has smaller size and larger capacitance by adopting a Metal-Oxide-Semiconductor Field-Effect Transistor (Metal-Oxide-semiconductor field effect transistor) process. The high-frequency high-speed antenna has lower equivalent series resistance (ESR, equivalent Series Resistance) and equivalent series inductance (ESL, equivalent Series inductance) in electrical property, so that the high-frequency high-speed antenna has lower insertion loss and better performance in the aspect of high-frequency high-speed application, is suitable for the fields of mobile phones, communication, automobiles, medical treatment, aerospace and the like, and has an application range which is continuously expanded along with the development of technology and market.
In the prior art, a silicon capacitor is generally manufactured by forming a plurality of holes in a silicon substrate by photolithography or etching, and then forming a dielectric layer and an electrode layer on the inner side of the holes and the surface of the substrate. The maximum capacitance of such silicon capacitors within a limited size is limited and the success rate during processing is not high enough.
Disclosure of Invention
The utility model aims to overcome the defects that the maximum capacitance value of a silicon capacitor in a limited size in the prior art is limited and the success rate is not high enough in the processing process.
The utility model solves the technical problems by the following technical scheme:
the present utility model provides a capacitor comprising:
a substrate having a plurality of trench arrays in a front side of the substrate; the groove arrays are formed by arranging grooves at intervals along at least two different directions; the bottoms, the side walls and the surfaces of the substrates between the adjacent grooves are provided with dielectric layers;
and the electrode layer is positioned on the surface of the dielectric layer and covers the bottoms and the side walls of the plurality of grooves and the surface of the substrate between the adjacent grooves.
Preferably, the plurality of grooves are arranged alternately along two directions perpendicular to each other to form the plurality of groove arrays.
Preferably, each trench array is formed from the same number of trench arrangements.
Preferably, the groove arrays with the same arrangement direction are not adjacent; and/or the number of the groups of groups,
the front surface of the substrate is internally provided with a plurality of groove arrays with mutually perpendicular arrangement directions.
Preferably, the capacitor further comprises:
the first metal layer is positioned on the electrode layer and covers part of the electrode layer and is used for leading out the electrode layer;
and the second metal layer is used for leading out the substrate.
Preferably, the first metal layer covers all of the preselected areas of the trench array; and/or the number of the groups of groups,
the second metal layer is positioned on the back surface of the substrate; and/or the number of the groups of groups,
the second metal layer is located on the trench sidewall of the outermost periphery of the capacitor.
Preferably, the capacitor comprises a silicon capacitor;
the substrate comprises a silicon substrate.
The utility model also provides a capacitor module, which comprises a preset number of capacitors as described above.
Preferably, the predetermined number of capacitors are arranged in a capacitor cell array to form the capacitor module.
Preferably, adjacent capacitors share the outermost trench sidewall.
The utility model has the positive progress effects that:
the capacitor provided by the utility model has the advantages that the front surface of the substrate of the capacitor is internally provided with the plurality of groove arrays which are arranged along different directions, the electrode layer is covered on the groove arrays, and the plurality of groove arrays which are arranged along different directions can realize larger capacitance in a limited area, can offset stress in the processing process and improve the success rate of capacitor processing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is apparent that the drawings in the following description are only some examples or embodiments of the present specification, and it is possible for those of ordinary skill in the art to apply the present specification to other similar situations according to the drawings without inventive effort. Unless otherwise apparent from the context of the language or otherwise specified, like reference numerals in the figures refer to like structures or operations.
Fig. 1 is a first schematic structure of a capacitor in embodiment 1 of the present utility model.
Fig. 2 is a second structural schematic diagram of the capacitor in embodiment 1 of the present utility model.
Fig. 3 is a third structural schematic diagram of the capacitor in embodiment 1 of the present utility model.
Fig. 4 is a fourth structural diagram of the capacitor in embodiment 1 of the present utility model.
Fig. 5 is a schematic diagram of an equivalent circuit of a capacitor in embodiment 1 of the present utility model.
Fig. 6 is a schematic structural diagram of a capacitor module in embodiment 2 of the present utility model.
Fig. 7 is a schematic diagram of an equivalent circuit of a capacitor module in embodiment 2 of the present utility model.
Detailed Description
The utility model is further illustrated by means of the following examples, which are not intended to limit the scope of the utility model.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
It will be appreciated that "system," "apparatus," "unit" and/or "module" as used herein is one method for distinguishing between different components, elements, parts, portions or assemblies of different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.
As used herein, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly indicates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.
The terms "having," "can have," "including," or "can include," as used herein, are intended to refer to the existence of a corresponding function, operation, element, etc. herein and are not intended to limit the existence of other one or more functions, operations, elements, etc. Furthermore, it should be understood that the terms "comprises" or "comprising," as used herein, are intended to specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
The term "a or B", "at least one of a and/or B" or "one or more of a and/or B" as used herein includes any and all combinations of words listed therewith. For example, "a or B", "at least one of a and B" or "at least one of a or B" means (1) including at least one a, (2) including at least one B, or (3) including both at least one a and at least one B.
The definitions of the first and second, etc. herein are provided herein for the purpose of illustration and distinction of descriptive objects only, without order division, and without implying any particular limitation on the number of devices herein, and without any limitation herein. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
Example 1
Please refer to fig. 1, which is a schematic diagram of a first structure of a capacitor in the present embodiment, which is a top view of the capacitor. Specifically, as shown in fig. 1, the capacitor includes:
a substrate 1 having a plurality of trench arrays 2 in a front surface of the substrate 1; the plurality of groove arrays 2 are formed by arranging a plurality of grooves 3 alternately along at least two different directions; specifically, within one trench array 2, a plurality of silicon bodies 13 of the substrate 1 constitute sidewalls of a plurality of trenches 3 to partition the plurality of trenches 3; the bottoms, the side walls and the surfaces of the substrates between the adjacent grooves are provided with dielectric layers; preferably, the depth of the grooves is in the range of 20-500 microns and the openings are in the range of 0.2-20 microns; the thickness of the dielectric layer ranges from 10 nanometers to 10 micrometers, and the dielectric layer can be made of silicon oxide, silicon nitride, a silicon oxide/silicon nitride/silicon oxide (ONO, oxide-nitride-oxide) composite structure or other single-layer or composite dielectric.
The electrode layer 4 is located on the dielectric layer surface of the substrate 1 and covers the bottoms, sidewalls and surfaces of the substrate between adjacent trenches. In this embodiment, the electrode layer 4 may be located in a preselected area in the middle of the capacitor, the electrode layer 4 covering the dielectric layer, while the electrode of the substrate may be led out through the sidewall via 12 of the capacitor preselection trench. Preferably, the electrode layer may be made of polysilicon or metal, and the thickness of the uppermost electrode layer is in the range of 0.2 micrometers to 20 micrometers.
In this embodiment, the capacitor includes a silicon capacitor; the substrate comprises a silicon substrate. Preferably, the width of the silicon body is 0.2 to 20 microns.
In an alternative embodiment, a plurality of grooves 3 are arranged alternately in two directions perpendicular to each other to form a plurality of groove arrays 2, each groove array 2 being formed by arranging the same number of grooves 3. As shown in fig. 1, the plurality of trenches 3 are alternately arranged in two directions perpendicular to each other to form the first trench array 21 and the second trench array 22, respectively, so that the edge region in the capacitor can be utilized to the maximum extent.
In another alternative embodiment, a plurality of trench arrays 2 are arranged in a direction perpendicular to each other in one surface of the substrate 1, and the trench arrays 2 in the same direction are not adjacent. By arranging the groove arrays 2 mutually perpendicular at intervals, the stresses in the processing process are offset to the greatest extent.
Furthermore, the capacitor further includes:
a first metal layer 5, which is located on the electrode layer and covers part of the uppermost electrode layer, and is used for leading out the electrode layer; a second metal layer 6 located in the through hole 12 on the sidewall of the trench preselected for the capacitor for extracting the substrate 1; the first metal layer is electrically insulated from the second metal layer.
In this embodiment, the first metal layer 5 covers all preselected areas of the trench array 2; the second metal layer 6 is located on the trench sidewalls at the outermost periphery of the capacitor.
The structure of the capacitor is further illustrated by way of example.
Please refer to fig. 2, which is a second schematic structure diagram of the capacitor in the present embodiment, which is a cross-sectional view of the capacitor. Specifically, as shown in fig. 2, in an alternative embodiment, the first metal layer 5 is located on the electrode layer 4 and covers a part of the electrode layer 4, for extracting the electrode layer 4; the second metal layer 6 is positioned on the side wall of the groove at the outermost periphery of the capacitor, and the second metal layer 6 is used for leading out the substrate 1; the electrode layer 4 is electrically insulated from the substrate 1 by a dielectric layer 11.
In addition, a barrier layer 7 is provided between the first metal layer 5 and the second metal layer 6 to electrically insulate between the first metal layer 5 and the second metal layer 6. Preferably, the thickness of the barrier layer can be in the range of 100 nanometers to 10 micrometers, and the material of the barrier layer can be silicon oxide, silicon nitride, other dielectric layers and composite structures formed by the silicon oxide, the silicon nitride and the other dielectric layers.
Please refer to fig. 3, which is a third schematic diagram of a capacitor in the present embodiment, which is a top view of the capacitor. Specifically, as shown in fig. 3, in another alternative embodiment, the substrate electrode may also be led out through the metal layer on the back side of the substrate, where there is no need to provide a via and a metal layer on the trench sidewalls of the capacitor. Please refer to fig. 4, which is a fourth schematic diagram of the capacitor in the present embodiment, which is a cross-sectional view of the capacitor. Specifically, as shown in fig. 4, the first metal layer 5 is located on the electrode layer 4 and covers a part of the electrode layer 4, for extracting the electrode layer 4; the second metal layer 6 is positioned on the back surface of the substrate 1, and the second metal layer 6 is used for leading out the substrate 1; the electrode layer 4 is electrically insulated from the substrate 1 by a dielectric layer 11.
Please refer to fig. 5, which is a schematic diagram of an equivalent circuit of the capacitor in the present embodiment. Specifically, as shown in fig. 5, the electrode layer 4 is electrically insulated from the substrate 1 by the dielectric layer 11 to constitute a capacitor. By increasing the thickness of the dielectric layer, the capacitance of the capacitor can be increased.
In the present embodiment, the specific position of the second metal layer is not specifically limited, but the distribution of the second metal layer is described only by taking the case where the second metal layer is located on the trench sidewall at the outermost periphery of the capacitor and the back surface of the substrate as an example, but this is not intended to limit the specific idea of the embodiment of the present utility model.
The above-described embodiments are merely preferred embodiments of the present utility model, and are not intended to limit the present utility model in any way.
The capacitor provided by the embodiment has the advantages that the plurality of groove arrays arranged in different directions are arranged in one surface of the substrate of the capacitor, the electrode layer is covered on the surface of the substrate, the plurality of groove arrays arranged in different directions can realize larger capacitance in a limited area, and the stress in the processing process can be mutually offset, so that the success rate of capacitor processing is improved.
Example 2
Fig. 6 is a schematic structural diagram of a capacitor module according to the present embodiment. Specifically, as shown in fig. 6, the capacitor module includes a preset number of capacitors in embodiment 1.
In an alternative embodiment, a predetermined number of capacitors are arranged in an array of capacitive cells to form a capacitive module.
In addition, adjacent capacitors share the outermost trench sidewalls.
Please refer to fig. 7, which is a schematic diagram of an equivalent circuit of the capacitor module in the present embodiment. Specifically, as shown in fig. 7, by increasing the number of capacitors in the capacitor unit array, the number of capacitors connected in parallel can be increased, thereby increasing the capacitance of the capacitor module.
The capacitor module provided in this embodiment is arranged into a capacitor unit array by using the capacitor in embodiment 1, so that a larger capacitance value can be realized in a limited area, and the stress in the processing process can be mutually offset, so that the success rate of capacitor processing is improved, and the capacitance value of the capacitor module can be increased by increasing the number of capacitors, so that the capacitor module has a larger capacitance value change interval.
While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the utility model is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the utility model, but such changes and modifications fall within the scope of the utility model.
Claims (10)
1. A capacitor, the capacitor comprising:
a substrate having a plurality of trench arrays in a front side of the substrate; the groove arrays are formed by arranging grooves at intervals along at least two different directions; the bottoms, the side walls and the surfaces of the substrates between the adjacent grooves are provided with dielectric layers;
and the electrode layer is positioned on the surface of the dielectric layer and covers the bottoms and the side walls of the plurality of grooves and the surface of the substrate between the adjacent grooves.
2. The capacitor of claim 1 wherein said plurality of trenches are arranged in two directions perpendicular to each other to form said plurality of trench arrays.
3. A capacitor as claimed in claim 1 or claim 2, wherein each trench array is formed from the same number of trench arrangements.
4. A capacitor as claimed in any one of claims 1 to 3, wherein the arrays of trenches having the same alignment direction are not adjacent; and/or the number of the groups of groups,
the front surface of the substrate is internally provided with a plurality of groove arrays with mutually perpendicular arrangement directions.
5. The capacitor of any one of claims 1-4, further comprising:
the first metal layer is positioned on the electrode layer and covers part of the electrode layer and is used for leading out the electrode layer;
and the second metal layer is used for leading out the substrate.
6. The capacitor of claim 5 wherein said first metal layer covers all of the preselected areas of said trench array; and/or the number of the groups of groups,
the second metal layer is positioned on the back surface of the substrate; and/or the number of the groups of groups,
the second metal layer is located on the trench sidewall of the outermost periphery of the capacitor.
7. The capacitor of any one of claims 1-6, wherein the capacitor comprises a silicon capacitor;
the substrate comprises a silicon substrate.
8. A capacitive module comprising a predetermined number of capacitors as claimed in any one of claims 1-7.
9. The capacitor module of claim 8, wherein the predetermined number of capacitors are arranged in an array of capacitor cells to form the capacitor module.
10. A capacitor module as claimed in claim 8 or 9, wherein adjacent ones of said capacitors share outermost trench sidewalls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321042808.7U CN219873162U (en) | 2023-04-28 | 2023-04-28 | Capacitor and capacitor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321042808.7U CN219873162U (en) | 2023-04-28 | 2023-04-28 | Capacitor and capacitor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219873162U true CN219873162U (en) | 2023-10-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321042808.7U Active CN219873162U (en) | 2023-04-28 | 2023-04-28 | Capacitor and capacitor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219873162U (en) |
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2023
- 2023-04-28 CN CN202321042808.7U patent/CN219873162U/en active Active
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