CN219872882U - content addressable memory - Google Patents

Abstract

The utility model provides a content addressable memory. The content addressable memory comprises a write control circuit, a memory cell array and an addressing control circuit, and is characterized in that memory cells in the memory cell array are latches, a plurality of memory cells corresponding to the same data form a memory cell word line, write data ports of the memory cells are connected to different bits of write data ports of the memory cell word line, write effective ports of the memory cells are connected to write effective ports of the memory cell word line, search data ports of the memory cells are connected to different bits of search data ports of the memory cell word line, read data ports of the memory cells are connected to different bits of read data ports of the memory cell word line, data matching ports of the memory cells are connected to different input ports of an AND gate, and output ports of the AND gate are connected to data matching ports of the memory cell word line.

Description

Content addressable memory

Technical Field

The present utility model relates to the field of integrated circuits, and more particularly to the field of memory.

Background

A content addressable memory (Content Addressable Memory, CAM) is a memory device that not only can access data, but also has a lookup function. The query function is to compare the input query data with all the internal data and determine whether the query data exists in the memory; if the query data already exists in the memory, the address where the query data is located in the memory is output. The content addressable memory can complete the comparison search operation of data in parallel in a single clock period, has higher search efficiency compared with other search systems based on hardware or software, and is widely applied to various fields.

In the existing mainstream technical scheme, the content addressable memory uses an analog circuit to build a memory unit, and the method of adding a plurality of transistors into a single SRAM unit is used for comparing the current input data with preset data and outputting a comparison result.

The disadvantage of the existing main-stream technology scheme, i.e. the content addressable memory built by using the analog circuit, is that the development period is long, the development cost is high, and the development needs to be re-performed during the replacement process. To solve this problem, a content addressable memory constituted by digital circuit units has been developed. For convenience of description, the content addressable memory constituted by digital circuit units is referred to as DCAM (DigitalCAM).

In the prior art, the DCAM uses a trigger as a storage unit, so that the area of the DCAM is larger and the power consumption is higher.

Disclosure of Invention

The present utility model provides a content addressable memory that addresses the problems of the prior art. The content addressable memory comprises a write control circuit, a memory cell array and an addressing control circuit, wherein each part of the content addressable memory is composed of digital circuit units, the memory cells in the memory cell array are latches (1 atch), and the content addressable memory composed of the digital circuit units is called DCAM for convenience of description.

The write control circuit described above includes a write data register and a write address decoder.

The addressing control circuit described above includes a lookup data register, a match line encoder, and a lookup address register.

In yet another embodiment of the present utility model, the DCAM described above further includes a read control circuit.

The read control circuit described above includes a read data register and a read address decoder.

In yet another embodiment of the present utility model, the write control circuit further includes a data gate circuit.

Compared with the content addressable memory mainly composed of analog circuits in the prior main stream technical scheme, the utility model has the advantages that the main development work of DCAM is irrelevant to the process, and the development cost is reduced; compared with the existing DCAM, the utility model provides the DCAM which uses the latch as the storage unit, and can reduce the power consumption and the area of the DCAM; the utility model also provides the DCAM containing the data gate control circuit, and the power consumption of the DCAM is further reduced.

Drawings

FIG. 1 is an exemplary diagram of a memory cell of a DCAM including a flip-flop

FIG. 2 is an exemplary diagram of a memory cell of a novel DCAM including a latch

FIG. 3 is an exemplary diagram of a memory word line of a novel DCAM

FIG. 4 is an exemplary diagram of a novel DCAM

FIG. 5 is an exemplary diagram of a novel DCAM including a data gating circuit

Detailed Description

Aiming at the problems existing in the prior art, an embodiment of the utility model provides a novel DCAM, which is specifically as follows.

In one embodiment of the present utility model, latches are used as the memory cells. The specific structure and connection relationship are as follows.

Fig. 2 is an exemplary diagram of one memory cell in a DCAM. The write data port is connected to the D port of the latch; the write active port is connected to the EN port of the latch; the Q port and the search data signal of the latch are connected to two input ports of the exclusive-OR gate; the output port of the exclusive OR gate is connected to the data matching port after being inverted; the Q port of the latch is connected to the read data port. Each memory cell may store one bit.

In a DCAM with a data bit width of N, each data bit includes N bits, and N memory cells corresponding to the N bits constitute one memory cell word line. Fig. 3 is an exemplary diagram of one memory cell word line in a DCAM. The write data ports of memory cells 301 are connected to different bits of the write data ports of the memory cell word lines; the write-active port of the memory cell 301 is connected to the write-active port of the memory cell word line; the look-up data port of memory cell 301 is connected to different bits of the look-up data port of the memory cell word line; the read data port of memory cell 301 is connected to different bits of the read data port of the memory cell word line; the data matching ports of the memory unit 301 are connected to different input ports of the and gate; the output port of the AND gate is connected to the data match port of the memory cell word line.

Fig. 4 is an exemplary diagram of a DCAM. The DCAM is composed of a memory cell array 410 and peripheral control circuits. The memory cell array 410 is composed of a plurality of memory cell word lines 401.

The write control circuit of the DCAM includes a write data register 403 and a write address decoder 402, and the connection relationship is as follows: the write data port of the DCAM is connected to the input of the write data register 403; the output of the write data register 403 is connected to the write data ports of all memory cell word lines 401; the write address port of the DCAM is connected to the input of the write address decoder 402; the output of the write address decoder 402 is connected to the write enable ports of all memory cell word lines 401. When data is written into the DCAM, the memory cell word line 401 corresponding to the write address is selected, the write enable port value of the selected memory cell word line 401 is valid, and the write enable port values of the rest memory cell word lines 401 are invalid; the write data port values of all memory cell word lines 401 are the values of the write data.

The read control circuit of the DCAM includes a read data register 405 and a read address decoder 404, and the connection relationship is as follows: the read address port of the DCAM is connected to the input of the read address decoder 404; the read data port of memory cell word line 401 is connected to different inputs of read address decoder 404; an output of the read address decoder 404 is connected to an input of a read data register 405; the output of the read data register 405 is connected to the read data port of the DCAM. When data is read from the DCAM, the memory cell word line 401 corresponding to the read address is selected, and the read address decoder 404 outputs the value of the read data port of the selected memory cell word line 401 to the DCAM read data port.

The addressing control circuit of the DCAM includes a lookup data register 408, a match line encoder 406, and a lookup address register 407, connected as follows: the look-up data port of the DCAM is connected to the input of the look-up data register 408; the output of the look-up data register 408 is connected to the look-up data port of the memory cell word line 401; the data match port of memory cell word line 401 is connected to the input port of match line encoder 406; the output port of the match line encoder 406 is connected to the input port of the lookup address register 407; the output port of the lookup address register 407 is connected to the lookup address port of the DCAM. When searching for data from the DCAM, the memory cell word line 401 containing the search data is selected, and the match line encoder 406 calculates the address of the selected memory cell word line 401 and outputs the result from the search address port of the DCAM.

The DCAM is optimized by using latches instead of flip-flops: the latch area is lower than the trigger, so that the area of DCAM is reduced; the latches do not need to be connected with clock signals which are turned frequently, so that the power consumption of the DCAM is reduced.

In yet another embodiment of the present utility model, an exemplary diagram of a DCAM is shown in FIG. 5.

Unlike fig. 4, the write control circuit of the DCAM of fig. 5 includes a write data register 403, a write address decoder 402, and a data gating circuit 409, and the connection relationship is as follows: the write data port of the DCAM is connected to the input of the write data register 403; an output of the write data register 403 is connected to an input of the data gating circuit 409; the write address port of the DCAM is connected to the input of the write address decoder 402; an output terminal of the write address decoder 402 is connected to a write enable port of all memory cell word lines 401 and another input terminal of the data gate circuit 409; the outputs of the data gate 409 are respectively connected to the write data ports of the memory cell word lines 401. When data is written into the DCAM, the memory cell word line 401 corresponding to the write address is selected, the write enable port value of the selected memory cell word line 401 is valid, and the write enable port values of the rest memory cell word lines 401 are invalid; the write data port value of the selected memory cell word line 401 is the value of the write data, and the write data port value of the selected memory cell word line 401 is a preset set value.

By adding the data gate control circuit 409 module, only the value of the write data port of the selected memory cell word line 401 changes when data is written into the DCAM, and the number of times of changing the value of the write data port of the memory cell word line 401 is reduced, so that the power consumption of the DCAM is reduced.

In yet another embodiment of the present utility model, the DCAM is not provided with a function of reading data, and the read data correlation circuit may be deleted from the DCAM: the read data port may be deleted from the memory cell illustrated in fig. 2; the read data port may be deleted from the memory cell word line illustrated in fig. 3; the read address field port, read data port, read address decoder, and read data register may be deleted from the DCAM illustrated in fig. 4 or 5.

Under the situation that data is not required to be read through an address, deleting the circuit related to the read data does not affect the correct work of other functions, and the area of the circuit can be further reduced.

Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the utility model. Any and all equivalents and alternatives falling within the scope of the claims are intended to be embraced therein.

Claims (4)

1. The content addressable memory comprises a write control circuit, a memory cell array and an addressing control circuit, and is characterized in that memory cells in the memory cell array are latches, a plurality of memory cells corresponding to the same data form a memory cell word line, a write data port of the memory cells is connected to different bits of a write data port of the memory cell word line, a write effective port of the memory cells is connected to the write effective port of the memory cell word line, a search data port of the memory cells is connected to different bits of a search data port of the memory cell word line, a read data port of the memory cells is connected to different bits of a read data port of the memory cell word line, a data matching port of the memory cells is connected to different input ports of an AND gate, and an output port of the AND gate is connected to the data matching port of the memory cell word line.

2. The content addressable memory of claim 1, wherein the portions are comprised of digital circuit elements.

3. The content addressable memory according to claim 1 or 2, wherein the content addressable memory comprises a read control circuit.

4. The content addressable memory according to claim 1 or 2, wherein the write control circuit comprises a data gating circuit.