CN219871656U - Radio frequency chip test system - Google Patents
Radio frequency chip test system Download PDFInfo
- Publication number
- CN219871656U CN219871656U CN202321032419.6U CN202321032419U CN219871656U CN 219871656 U CN219871656 U CN 219871656U CN 202321032419 U CN202321032419 U CN 202321032419U CN 219871656 U CN219871656 U CN 219871656U
- Authority
- CN
- China
- Prior art keywords
- test
- switch
- radio frequency
- module
- path switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 269
- 230000008878 coupling Effects 0.000 claims description 17
- 238000010168 coupling process Methods 0.000 claims description 17
- 238000005859 coupling reaction Methods 0.000 claims description 17
- 238000001914 filtration Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 3
- 238000012805 post-processing Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005405 multipole Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
The utility model discloses a radio frequency chip test system which comprises a test signal input end, a first test module, a test board, a control module, a second test module and a test signal output end, wherein the control module is used for controlling the first test module and the second test module to be switched to corresponding front-stage test channels and rear-stage test channels, and the operation of manually replacing a radio frequency wire selection test end by utilizing a plurality of front-stage test channels in the first test module and a plurality of rear-stage test channels in the second test module is utilized, so that the test efficiency and the test stability are improved.
Description
Technical Field
The utility model relates to the technical field of chips, in particular to a radio frequency chip testing system.
Background
After the design of the radio frequency chip is completed, the chip needs to be tested to judge whether the radio frequency chip meets the design requirement. Because the radio frequency chip generally comprises a plurality of ports, each port needs to be tested correspondingly during testing, in a related test system, because the test system only supports the testing of a single port, when the radio frequency chip is tested, the radio frequency wire needs to be manually replaced to be connected with a second port for sequential testing after one port is tested, thus the test efficiency is lower, and other interference factors are easy to be introduced during the manual replacement of the radio frequency wire, so that the test result is inaccurate.
Therefore, in order to solve the above problems, the present utility model provides a radio frequency chip test system with high test efficiency and stability.
Disclosure of Invention
The utility model provides a radio frequency chip test system, which aims to solve the problems of lower test efficiency and poorer test stability of the existing test link.
In order to solve the above technical problems, the present utility model provides a radio frequency chip testing system, including: the device comprises a test signal input end, a first test module, a test board, a control module, a second test module and a test signal output end, wherein the first end of the first test module is connected with the test signal input end, the second end of the second test module is connected with the input end of the test board, the first test module comprises M front-stage test channels, the M front-stage test channels are used for receiving first radio frequency signals input by the test signal input end and inputting the first radio frequency signals to the input end of the test board, and M is more than or equal to 2; the first end of the second test module is connected with the output end of the test board, the second end of the second test module is connected with the test signal output end, the second test module comprises N rear-stage test channels, the N rear-stage test channels are used for receiving second radio frequency signals of the output end of the test board and inputting the second radio frequency signals to the test signal output end, and N is more than or equal to 2; the control module is connected with the control ends of the first test module and the second test module and is used for controlling the first test module and the second test module to be switched to corresponding front-stage test channels and rear-stage test channels.
Further, the first test module comprises a first multi-way change-over switch, the moving end of the first multi-way change-over switch is connected with the input end of the test signal, the fixed end of the first multi-way change-over switch is connected with the input end of the test board, and M front-stage test channels are formed between the fixed end of the first multi-way change-over switch and the input end of the test board.
Further, the first test module comprises a first multi-path change-over switch, a filtering unit, a first impedance matching unit, a second multi-path change-over switch, a first coupling unit and a third multi-path change-over switch which are sequentially connected, wherein the fixed end of the first multi-path change-over switch is connected with the input end of the test signal, the fixed end of the third multi-path change-over switch is connected with the input end of the test board, and the first multi-path change-over switch, the filtering unit, the first impedance matching unit, the second multi-path change-over switch, the first coupling unit and the third multi-path change-over switch form M front-stage test channels.
Further, the filtering unit comprises a circulator and a band-pass filter, a first end of the circulator is connected with the fixed end of the first multi-way change-over switch, a second end of the circulator is connected with the first end of the band-pass filter, and a second end of the band-pass filter is connected with the fixed end of the second multi-way change-over switch.
Further, the first impedance matching unit comprises a first duplexer and a first load, a first end of the first duplexer is connected with a second end of the filtering unit, a second end of the first duplexer is connected with the first load, and a third end of the first duplexer is connected with one fixed end of the second multiplexing switch.
Further, the radio frequency chip test system further comprises a first power meter, the first coupling unit comprises a first low intermodulation coupler, a first end of the first low intermodulation coupler is connected with a moving end of the second multi-way change-over switch, a second end of the first low intermodulation coupler is connected with a moving end of the third multi-way change-over switch, and a third end of the first low intermodulation coupler is connected with the first power meter.
Further, the second test module includes a fourth multi-path switch, an attenuation unit, a fifth multi-path switch, a second impedance matching unit and a sixth multi-path switch, wherein the fourth multi-path switch, the attenuation unit, the fifth multi-path switch, the second impedance matching unit and the sixth multi-path switch are sequentially connected, the fixed end of the fourth multi-path switch is connected with the output end of the test board, the movable end of the sixth multi-path switch is connected with the output end of the test signal, and the fourth multi-path switch, the attenuation unit, the fifth multi-path switch, the second impedance matching unit and the sixth multi-path switch form the N post-stage test channels.
Further, the second impedance matching unit includes a second duplexer and a second load, a first end of the second duplexer is connected with a stationary end of the fifth multi-path switch, a second end of the second duplexer is connected with the second load, and a third end of the second duplexer is connected with the stationary end of the sixth multi-path switch.
Further, the radio frequency chip test system further comprises a second coupling unit, wherein the second coupling unit comprises a second low intermodulation coupler, and a first end of the second low intermodulation coupler is connected between the attenuation unit and a moving end of the fifth multiplexing switch.
Further, the radio frequency chip test system further comprises a second power meter connected with the second end of the second low intermodulation coupler.
According to the radio frequency chip test system disclosed by the utility model, the first test module and the second test module are controlled to be switched to the corresponding front-stage test channel and rear-stage test channel by the control module, and the operation of manually replacing the radio frequency wire selection test end by utilizing the plurality of front-stage test channels in the first test module and the plurality of rear-stage test channels in the second test module is replaced, so that the test efficiency and the test stability are improved. The radio frequency chip test system disclosed by the utility model solves the problems of lower test efficiency and poorer test stability of the conventional test system.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a RF chip testing system according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a radio frequency chip testing system according to another embodiment of the present utility model;
FIG. 3 is a schematic diagram of a radio frequency chip testing system according to another embodiment of the present utility model;
reference numerals: 11. a first test module; 12. a second test module; 13. a test board; 14. a control module; 111. a filtering unit; 112. a first impedance matching unit; 113. a first coupling unit; 114. a first power meter; 121. a second impedance matching unit; 122. an attenuation unit; 123. a second coupling unit; 124. and a second power meter.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise; as used in the present specification and the appended claims, directional terms such as "above," "below," "sideways," and the like are used generally with respect to the orientation of the drawing figures or as normal usage relative to the user, unless the context clearly dictates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
FIG. 1 is a schematic diagram of a RF chip testing system according to an embodiment of the present utility model; FIG. 2 is a schematic diagram of a radio frequency chip testing system according to another embodiment of the present utility model; fig. 3 is a schematic diagram of a radio frequency chip testing system according to another embodiment of the present utility model. As shown in fig. 1 to 3, the radio frequency chip test system of the present embodiment includes a test signal input end, a first test module 11, a test board 13, a control module 14, a second test module 12, and a test signal output end, where a first end of the first test module 11 is connected to the test signal input end, a second end of the second test module 12 is connected to the input end of the test board 13, the first test module 11 includes M front-stage test channels, and the M front-stage test channels are configured to receive a first radio frequency signal input by the test signal input end and input the first radio frequency signal to the input end of the test board 13, where M is greater than or equal to 2; the first end of the second test module 12 is connected with the output end of the test board 13, the second end of the second test module 12 is connected with the test signal output end, the second test module 12 comprises N post-stage test channels, the N post-stage test channels are used for receiving the second radio frequency signal of the output end of the test board 13 and inputting the second radio frequency signal to the test signal output end, and N is more than or equal to 2; the control module 14 is connected to the control ends of the first test module 11 and the second test module 12, and is used for controlling the first test module 11 and the second test module 12 to switch to corresponding front-stage test channels and rear-stage test channels. In this embodiment, the control module 14 controls the first test module 11 and the second test module 12 to switch to the corresponding pre-stage test channel and post-stage test channel, and the multiple pre-stage test channels in the first test module 11 and the multiple post-stage test channels in the second test module 12 replace the operation of manually replacing the radio frequency line selection test end, so that the test efficiency and the test stability are improved.
In one embodiment, the test signal input end is configured to receive an external test signal, where the test signal may be set according to actual requirements, for example: as shown in fig. 1, the test signal may be a radio frequency signal directly sent by the signal source, or may be a radio frequency signal amplified by the power amplifier as shown in fig. 2, and it is understood that the radio frequency signal directly sent by the signal source and the radio frequency signal amplified by the power amplifier in this embodiment are both referred to as the first radio frequency signal.
In one embodiment, the test board 13 is used for carrying a chip to be tested, and the chip to be tested may be connected to the test board 13 by soldering, or may be connected by providing a test base on the test board 13.
In a certain embodiment, the test board 13 is provided with a plurality of input ends and a plurality of output ends, the chip to be tested is provided with a plurality of input ports and a plurality of output ports, and each input end and each output end on the test board 13 are correspondingly connected with each corresponding input port and each output port on the chip to be tested.
In one embodiment, the test signal output end is configured to input the second video signal to the external display device for display, so as to determine whether the design parameter of the tested chip meets the design index. In a certain embodiment, the external display device may be a spectrometer.
In one embodiment, as shown in fig. 2, the first test module 11 includes a first multiple-way switch, a moving end of the first multiple-way switch is connected to the test signal input end, a stationary end of the first multiple-way switch is connected to the input end of the test board 13, and the M front-stage test channels are formed between the stationary end of the first multiple-way switch and the input end of the test board 13.
In an embodiment, as shown in fig. 2 and fig. 3, the second test module 12 includes a fourth multi-path switch, an attenuation unit 122, a fifth multi-path switch, a second impedance matching unit 121, and a sixth multi-path switch that are sequentially connected, where a stationary end of the fourth multi-path switch is connected to an output end of the test board 13, a moving end of the sixth multi-path switch is connected to the test signal output end, and the fourth multi-path switch, the attenuation unit 122, the fifth multi-path switch, the second impedance matching unit 121, and the sixth multi-path switch form the N later test channels.
In an embodiment, as shown in fig. 3, the radio frequency chip test system includes three post-stage test channels, a first post-stage test channel is used for processing radio frequency signals of a low frequency band, a second post-stage test channel is used for processing radio frequency signals of a medium frequency band, and a third post-stage test channel is used for processing radio frequency signals of a high frequency band.
In this embodiment, the radio frequency chip test system can control the multi-path switch to a proper test channel according to the test requirement, so as to test the tested chip, thereby improving the test efficiency and avoiding the problem of inaccurate test caused by manually replacing the test channel.
In an embodiment, as shown in fig. 2, the radio frequency chip test system includes three rear test channels, the first multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch all include one active end and six inactive ends, only three inactive ends are shown in fig. 1, the other three inactive ends are not shown in the drawings, the test board 13 includes six input ends and six output ends, the six inactive ends of the first multi-way switch are connected to the six input ends of the test board 13 in a one-to-one correspondence, and the six output ends of the test board 13 are connected to the six inactive ends of the fourth multi-way switch in a one-to-one correspondence, for each rear test channel, and are connected between one inactive end of the fifth multi-way switch and one inactive end of the sixth multi-way switch. It is to be understood that, in other embodiments, the number of the stationary ends in the first multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch is not specifically limited, and is set according to actual requirements; the number of the input ends and the output ends of the test board 13 is not particularly limited, and is set according to actual requirements.
In an embodiment, as shown in fig. 2 and fig. 3, the second impedance matching unit 121 includes a second duplexer and a second load, a first end of the second duplexer is connected with an inactive end of the fifth multi-path switch, a second end of the second duplexer is connected with the second load, a third end of the second duplexer is connected with an inactive end of the sixth multi-path switch, and understandably, the second duplexer and the second load are respectively connected between the three inactive ends of the fifth multi-path switch and the three inactive ends of the sixth multi-path switch to realize impedance matching, so that the tested chip is better tested in function, and the accuracy of the test is improved.
It should be noted that, in fig. 3, the frequencies of the radio frequency signals processed by each of the post-processing channels are different, and thus, the parameters of the second diplexer in each of the post-processing channels are different.
In one embodiment, as shown in fig. 2, the radio frequency chip testing system further includes a second coupling unit 123, where the second coupling unit 123 includes a second low intermodulation coupler, and a first end of the second low intermodulation coupler is connected between the attenuation unit 122 and a moving end of the fifth multiplexing switch. It should be noted that, the attenuation unit 122 is a low intermodulation attenuator, and the low intermodulation attenuator is used for attenuating a signal entering the subsequent test channel, so as to prevent the damage to the components in the subsequent test channel caused by the excessive signal. It should be further noted that the rf chip testing system further includes a second power meter 124, where the second power meter 124 is connected to the second end of the second low intermodulation coupler, and it is understood that the signal output from the test board 13 may be monitored in real time by the second low intermodulation coupler and the second power meter 124.
In an embodiment, as shown in fig. 3, the first test module 11 includes a first multi-path switch, a filter unit 111, a first impedance matching unit 112, a second multi-path switch, a first coupling unit 113, and a third multi-path switch that are sequentially connected, where a stationary end of the first multi-path switch is connected to the test signal input end, and a stationary end of the third multi-path switch is connected to the input end of the test board 13, and the first multi-path switch, the filter unit 111, the first impedance matching unit 112, the second multi-path switch, the first coupling unit 113, and the third multi-path switch form M pre-stage test channels. It should be noted that, the first multi-way switch, the second multi-way switch and the third multi-way switch all include one moving end and six fixed ends, and only three fixed ends are illustrated in fig. 1.
In one embodiment, the first, second, third, fourth, fifth and sixth multiple switches are high power single pole six throw switches.
In a certain embodiment, the first multi-way switch, the second multi-way switch, the third multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch may be single-pole multi-throw switches or multi-pole multi-throw switches, and the first multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch may be the same type of switch or different types of switches.
In this embodiment, the moving ends of the first, second, third, fourth, fifth and sixth multi-way switches are the moving ends of the switches, and the moving ends of the first, fourth, fifth and sixth multi-way switches are the moving ends of the switches, and it is understood how many moving ends there are the first, second, third, fourth, fifth and sixth multi-way switches.
In one embodiment, as shown in fig. 3, the pre-stage test channel includes a filter unit 111, a first end of the filter unit 111 is connected to one stationary end of the first multiplexing switch, and a second end of the filter unit 111 is connected to one stationary end of the second multiplexing switch. Specifically, the filtering unit 111 includes a circulator and a band-pass filter, a first end of the circulator is connected to one stationary end of the first multiplexing switch, a second end of the circulator is connected to the first end of the band-pass filter, and a second end of the band-pass filter is connected to one stationary end of the second multiplexing switch. Understandably, the signal amplified by the power amplifier may be filtered by the circulator and the band pass filter.
In one embodiment, as shown in fig. 3, the first impedance matching unit 112 includes a first duplexer and a first load, a first end of the first duplexer is connected to the second end of the filtering unit 111, a second end of the first duplexer is connected to the first load, and a third end of the first duplexer is connected to one of the fixed ends of the second multiplexing switch. Understandably, because the first multi-way switch, the second multi-way switch, the third multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch are all high-power radio frequency switches, the introduction of the high-power radio frequency switches can cause the deterioration of the front and back test links of the test board 13, and in order to optimize the test link matching, the first duplexer and the first load are introduced to ensure that the front and back matching of the test board 13 is in a 50 ohm state, thereby ensuring the test accuracy.
It should be noted that, as shown in fig. 3, the parameters of the first diplexer in each pre-stage test channel are different because the frequency of the radio frequency signal of each pre-stage test channel is different.
It should be noted that, as shown in fig. 3, since the rf chip test system includes M pre-stage test channels, the frequency of the rf signal of each pre-stage test channel is different, and thus the parameters of the first diplexer in each pre-stage test channel are different.
In one embodiment, as shown in fig. 3, the radio frequency chip testing system further includes a first power meter 114, the first coupling unit 113 includes a first low intermodulation coupler, a first end of the first low intermodulation coupler is connected to the moving end of the second multiplexing switch, a second end of the first low intermodulation coupler is connected to the moving end of the third multiplexing switch, and a third end of the first low intermodulation coupler is connected to the first power meter 114. Understandably, the signal input to the test board 13 can be monitored in real time by the first low intermodulation coupler and the first power meter 114.
According to the radio frequency chip test system provided by the utility model, the control module is used for controlling the switching of the first multi-way switch, the fourth multi-way switch, the fifth multi-way switch and the sixth multi-way switch, the first multi-way switch is used for replacing the operation of manually replacing a radio frequency line to select a test port, and the signals of the test port are output to the spectrometer for detection through the fourth multi-way switch, the fifth multi-way switch, the sixth multi-way switch, the attenuation unit and a plurality of later test channels, so that the performance of a tested chip is detected; specifically, the radio frequency chip test system further comprises a second multi-path change-over switch, a third multi-path change-over switch, a first coupling unit and a plurality of front-stage test channels which are connected between the first multi-path change-over switch and the test board, so that the tested chip is tested at multiple frequencies, manual disassembly and assembly are avoided, manual frequent line replacement is avoided, and the test efficiency and the test stability are improved. Therefore, the radio frequency chip test system disclosed by the utility model solves the problems of lower test efficiency and poorer test stability of the existing test link.
While the utility model has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
Claims (10)
1. A radio frequency chip test system is characterized by comprising a test signal input end, a first test module, a test board, a control module, a second test module and a test signal output end, wherein,
the first end of the first test module is connected with the test signal input end, the second end of the second test module is connected with the input end of the test board, the first test module comprises M front-stage test channels, the M front-stage test channels are used for receiving first radio frequency signals input by the test signal input end and inputting the first radio frequency signals to the input end of the test board, and M is more than or equal to 2;
the first end of the second test module is connected with the output end of the test board, the second end of the second test module is connected with the test signal output end, the second test module comprises N rear-stage test channels, the N rear-stage test channels are used for receiving second radio frequency signals of the output end of the test board and inputting the second radio frequency signals to the test signal output end, and N is more than or equal to 2;
the control module is connected with the control ends of the first test module and the second test module and is used for controlling the first test module and the second test module to be switched to corresponding front-stage test channels and rear-stage test channels.
2. The system of claim 1, wherein the first test module comprises a first multi-way switch, wherein a movable end of the first multi-way switch is connected with the test signal input end, a stationary end of the first multi-way switch is connected with the input end of the test board, and the M front-stage test channels are formed between the stationary end of the first multi-way switch and the input end of the test board.
3. The radio frequency chip test system according to claim 1, wherein the first test module comprises a first multi-path switch, a filter unit, a first impedance matching unit, a second multi-path switch, a first coupling unit, and a third multi-path switch which are sequentially connected, wherein a stationary end of the first multi-path switch is connected with the test signal input end, a stationary end of the third multi-path switch is connected with the input end of the test board, and the first multi-path switch, the filter unit, the first impedance matching unit, the second multi-path switch, the first coupling unit, and the third multi-path switch form M pre-stage test channels.
4. The system of claim 3, wherein the filter unit comprises a circulator and a band-pass filter, a first end of the circulator is connected to the stationary end of the first multiplexing switch, a second end of the circulator is connected to the first end of the band-pass filter, and a second end of the band-pass filter is connected to the stationary end of the second multiplexing switch.
5. The system of claim 3, wherein the first impedance matching unit comprises a first duplexer and a first load, a first end of the first duplexer is connected to the second end of the filtering unit, a second end of the first duplexer is connected to the first load, and a third end of the first duplexer is connected to one stationary end of the second multiplexing switch.
6. The radio frequency chip test system of claim 3, further comprising a first power meter, the first coupling unit comprising a first low intermodulation coupler, a first end of the first low intermodulation coupler being connected to the moving end of the second multiplexing switch, a second end of the first low intermodulation coupler being connected to the moving end of the third multiplexing switch, a third end of the first low intermodulation coupler being connected to the first power meter.
7. The radio frequency chip test system according to any one of claims 1 to 6, wherein the second test module comprises a fourth multi-path switch, an attenuation unit, a fifth multi-path switch, a second impedance matching unit and a sixth multi-path switch which are sequentially connected, a stationary end of the fourth multi-path switch is connected with an output end of the test board, a moving end of the sixth multi-path switch is connected with the test signal output end, and the fourth multi-path switch, the attenuation unit, the fifth multi-path switch, the second impedance matching unit and the sixth multi-path switch form the N subsequent test channels.
8. The system of claim 7, wherein the second impedance matching unit comprises a second duplexer and a second load, a first end of the second duplexer is connected to the stationary end of the fifth multiplexing switch, a second end of the second duplexer is connected to the second load, and a third end of the second duplexer is connected to the stationary end of the sixth multiplexing switch.
9. The radio frequency chip test system according to claim 8, further comprising a second coupling unit comprising a second low intermodulation coupler, a first end of the second low intermodulation coupler being connected between the attenuation unit and a moving end of the fifth multiplexing switch.
10. The radio frequency chip test system according to claim 9, further comprising a second power meter connected to the second end of the second low intermodulation coupler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321032419.6U CN219871656U (en) | 2023-04-28 | 2023-04-28 | Radio frequency chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321032419.6U CN219871656U (en) | 2023-04-28 | 2023-04-28 | Radio frequency chip test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219871656U true CN219871656U (en) | 2023-10-20 |
Family
ID=88348743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321032419.6U Active CN219871656U (en) | 2023-04-28 | 2023-04-28 | Radio frequency chip test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219871656U (en) |
-
2023
- 2023-04-28 CN CN202321032419.6U patent/CN219871656U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN213661598U (en) | Radio frequency L-PA Mid device, radio frequency transceiving system and communication equipment | |
| CN104519503A (en) | Radio frequency link switching device for mobile communication terminal testing | |
| CN101478353A (en) | Radio frequency unit capable of being used in wireless communication base station radio frequency automatic test | |
| CN111970171B (en) | Automatic test system of radio frequency circuit in terminal equipment | |
| CN111157804A (en) | Radio frequency switch module and antenna test system | |
| CN104880621A (en) | Self calibration passive intermodulation tester | |
| CN105323015A (en) | Device for realizing passive device testing | |
| CN219871656U (en) | Radio frequency chip test system | |
| CN104104407A (en) | Multifunctional microwave transmit-receive front end | |
| CN213460024U (en) | Programme-controlled multichannel microwave device switching equipment | |
| CN210839537U (en) | Split circuit and multi-band communication equipment | |
| KR100531619B1 (en) | Apparatus and method of receiving sensitivity measuring for communication system with receiving only path | |
| CN101710836A (en) | Frequency sweep device and frequency sweep method | |
| CN101183128A (en) | Testing method and apparatus of duplex device power capacity | |
| CN114362774B (en) | 5G NR LFEM out-of-band suppression zero point reconfigurable structure receiver | |
| CN216565121U (en) | S-band and X-band receiving channel gain self-adaptive adjusting system | |
| CN114070219A (en) | Filter network for eliminating electromagnetic wave interference effect | |
| CN109952703B (en) | RF module and method for testing RF module | |
| CN219122317U (en) | Radio frequency device detection system | |
| CN115372690B (en) | Antenna tuner peak voltage measurement system | |
| CN220137397U (en) | Radio frequency front-end circuit and satellite navigation system | |
| CN220693125U (en) | Switch assembly | |
| CN219087140U (en) | Reconfigurable test system | |
| CN217282934U (en) | Radio frequency front end module and system | |
| CN218772103U (en) | Conducted stray test system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |