CN219842810U - Chip test circuit and test device - Google Patents
Chip test circuit and test device Download PDFInfo
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- CN219842810U CN219842810U CN202320780780.0U CN202320780780U CN219842810U CN 219842810 U CN219842810 U CN 219842810U CN 202320780780 U CN202320780780 U CN 202320780780U CN 219842810 U CN219842810 U CN 219842810U
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- 238000012360 testing method Methods 0.000 title claims abstract description 77
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- 239000003990 capacitor Substances 0.000 claims description 10
- 230000032683 aging Effects 0.000 abstract description 6
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- 238000005260 corrosion Methods 0.000 description 1
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Abstract
The utility model discloses a chip test circuit and a test device, which are used for testing a memory chip, wherein the test circuit comprises a driving chip, a first power supply module and an indicator lamp module; the driving chip is connected with the storage chip; the first power supply module is connected with the driving chip; the indicator light module is connected with the driving chip; the indicator light module at least comprises two indicator lights with different colors; the chip test circuit can display different detection results of the detection chip through the indicator lamps with different colors, and compared with a traditional upper computer and a display screen platform, the indicator lamps can reflect the test results more succinctly and clearly during the aging test; and compared with a display screen with a good upper computer, the control logic of the indicator lamp is simple, the cost is lower, and the design cost can be effectively reduced. The utility model can be widely applied to the technical field of memory chip testing.
Description
Technical Field
The utility model relates to the technical field of memory chip testing, in particular to a chip testing circuit and a testing device.
Background
In the semiconductor storage industry, the existing high-low temperature aging test usually tests the service life and corrosion resistance of chips in test boxes in extreme environments, most of the existing schemes are that a test board is added with a communication board and a computer is used for controlling, or the test board is added with the communication board and a display screen is used for controlling, even the existing schemes are added with a full-automatic scheme of a manipulator, the test platform of the schemes is high in cost, devices are aged along with the aging of the chips in the test process, and the reliability and the test efficiency of test results are seriously affected. There is a need for a new test circuit and test apparatus.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems existing in the related art to a certain extent.
Therefore, an object of the embodiments of the present utility model is to provide a chip test circuit, which can display different detection results of a detection chip through indicator lamps with different colors, and compared with a conventional upper computer and a display screen platform, the indicator lamps can reflect the test results more simply and clearly during burn-in test; and compare in display screen and host computer, the control of pilot lamp is simple, and the cost is lower, can effectively reduce the cost of design.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the utility model comprises the following steps:
a chip test circuit is used for testing a memory chip and comprises a driving chip, a first power supply module and an indicator lamp module;
the driving chip is connected with the storage chip; the first power supply module is connected with the driving chip; the indicator light module is connected with the driving chip; the indicator light module at least comprises indicator lights with two different colors.
In addition, the chip test circuit according to the above embodiment of the present utility model may further have the following additional technical features:
optionally, in an embodiment of the present utility model, the chip test circuit further includes a second power module, a USB download interface, an ESD protection module, a trigger start module, and a serial isolation module; the USB download interface is connected with the driving chip and is used for burning a driving program for the driving chip; the ESD protection module is connected with the driving chip and the USB download interface; the trigger starting module is connected with the driving chip; the trigger starting module is connected with the second power supply module; the second power supply module is connected with the memory chip and is used for supplying power to the memory chip and the trigger starting circuit; the serial port isolation module is connected with the driving chip, and the serial port isolation module is connected with the second power supply module.
Optionally, in one embodiment of the present utility model, the indicator light module further includes a protection resistor; the protection resistor is connected with the indicator lamp in series.
Optionally, in one embodiment of the utility model, the ESD protection module comprises an ESD chip; the ESD chip comprises 6 pins, and a fifth pin of the ESD chip is connected with a power supply end of the driving chip; a second pin of the ESD chip is grounded; the sixth pin of the ESD chip is connected with the DM pin of the driving chip; the first pin of the ESD chip is connected with the DP pin of the driving chip.
Optionally, in one embodiment of the present utility model, the trigger-starting module includes a key switch, a current limiting device, and a filtering device; the key switch comprises 4 pins, wherein the first pin and the second pin of the key switch are connected in parallel and then grounded, the third pin of the key switch is connected with the RST pin of the driving chip, and the fourth pin of the key switch is connected with the BOOT pin of the driving chip; one end of the current limiting device is connected with the output end of the second power supply module; the other end of the current limiting device is connected with a third pin of the key switch; one end of the filter device is connected with the third pin of the key switch, and one end of the filter device is grounded.
Optionally, in one embodiment of the present utility model, the second power module includes a voltage conversion chip, and an input end of the voltage conversion chip is connected to the first power module; the output end of the voltage conversion chip is connected with the serial port isolation module; the output end of the voltage conversion chip is connected with the trigger starting module; and the output end of the voltage conversion chip is connected with the storage chip.
Optionally, in an embodiment of the present utility model, the current limiting device includes a resistor or a jumper.
Optionally, in an embodiment of the utility model, the filter device comprises an electrolytic capacitor or a non-polar capacitor.
Optionally, in one embodiment of the present utility model, the indicator light module includes 4 LED lights.
On the other hand, the technical scheme adopted by the embodiment of the utility model further comprises the following steps: a chip testing device comprises a plurality of chip testing circuits and an external power supply, wherein the chip testing circuits are connected in parallel and then connected into the external power supply.
The advantages and benefits of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
The chip test circuit in the embodiment of the utility model can display different detection results of the detection chip through the indicator lamps with different colors by connecting the driving chip with the indicator lamp module, and compared with a traditional upper computer and a display screen platform, the indicator lamp can reflect the test results more succinctly and clearly during aging test, and the test efficiency can be improved; compared with a display screen with a good upper computer, the cost is lower, and the design cost can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a chip test circuit according to the present utility model;
FIG. 2 is a schematic diagram of a pin of a driving chip of a chip test circuit according to the present utility model;
FIG. 3 is a schematic circuit diagram of a serial port isolation module of a chip test circuit according to the present utility model;
FIG. 4 is a schematic circuit diagram of a first power module of a chip test circuit according to the present utility model;
FIG. 5 is a schematic circuit diagram of a trigger start module of a chip test circuit according to the present utility model;
FIG. 6 is a schematic diagram of a circuit structure of an indicator module of a chip test circuit according to the present utility model;
FIG. 7 is a schematic diagram of an ESD protection module of a chip test circuit according to the present utility model;
fig. 8 is a schematic circuit diagram of a second power module of the chip test circuit according to the present utility model.
Detailed Description
Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model.
In the description of the present utility model, it should be understood that the directions or positional relationships indicated by the terms "distance", "upper", "lower", "left", "right", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, features defining "first", "second" may include one or more such features, either explicitly or implicitly. In the description of the present utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present utility model, it should be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Referring to fig. 1, a chip test circuit is provided in an embodiment of the present utility model, which may be used for testing a memory chip, and may include a driving chip 1, a first power module 2, and an indicator light module 3; wherein the driving chip 1 can be connected with the memory chip; the first power supply module 2 is connected with the driving chip 1; the indicator light module 3 can be connected with the driving chip 1; the indicator light module 3 may comprise at least two indicator lights of different colors. The first power module 2 may be a combination of an external power source and a power source interface, or may be a direct power source access circuit.
Further, in some embodiments of the present utility model, the chip test circuit may further include a second power module, a USB download interface, an ESD protection module, a trigger start module, and a serial isolation module; referring to fig. 2-8, in fig. 2-8, the interface names are identical for the ports that are connected together; the USB download interface can be connected with the driving chip and can be used for burning a driving program for the driving chip; the ESD protection module can be connected with the driving chip and the USB download interface; the ESD module reduces the damage of static electricity to the chip and the circuit; the trigger starting module can be connected with the driving chip; the trigger starting module can be connected with the second power supply module; the trigger starting module can be used for starting a test program; the second power supply module can be connected with the memory chip to be tested, the second power supply module can adjust 5v of the first power supply module to 3.3V, and the 3.3V can be used for supplying power to the memory chip and the trigger starting circuit; the serial port isolation module can be connected with the driving chip and can be connected with the second power supply module; the serial port isolation module can reduce serial port communication signal interference, can isolate the high voltage from the low voltage of the power supply, and prevent the main control chip from being damaged when the circuit fails.
Further, in some embodiments of the present utility model, referring to fig. 6, the indicator light module may further include a protection resistor; the protection resistor may be connected in series with the indicator lamp, specifically, in fig. 6, one ends of the protection resistors R1 to R4 are respectively connected with the anodes of the LEDs 1 to LED4, the cathodes of the LEDs 1 to LED4 are all grounded, the other ends of the resistors may be connected with 4 IO ports of the driving chip, and when any one of the 4 IO ports outputs a high level, one of the corresponding LEDs 1 to LED4 may be turned on. It should be noted that, the number of the protection resistors is the same as the number of the indicator lamps, and when the number of the indicator lamps is two, the number of the protection resistors is also two, and the protection resistors are connected in series with the indicator lamps in one-to-one manner, that is, each indicator lamp is connected in series with one protection resistor.
Further, referring to fig. 7, in some embodiments of the utility model, an ESD protection module may include an ESD chip; the type of the ESD chip can be LC0504F, the ESD chip can comprise 6 pins, and a fifth pin of the ESD chip can be connected with a power supply end of the driving chip; the second leg of the ESD chip may be grounded; the sixth pin of the ESD chip is connected with the DM pin of the driving chip; the first pin of the ESD chip can be connected with the DP pin of the driving chip; the third pin and the fourth pin of the ESD chip are suspended.
Further, referring to fig. 5, in some embodiments of the present utility model, the trigger-start module may include a key switch, a current limiting device, and a filtering device; the key switch can comprise 4 pins, the first pin and the second pin of the key switch are connected in parallel and then can be grounded, the third pin of the key switch can be connected with the RST pin of the driving chip, and the fourth pin of the key switch can be connected with the BOOT pin of the driving chip; one end of the current limiting device can be connected with the output end of the second power supply module; the other end of the current limiting device can be connected with a third pin of the key switch; one end of the filter device is connected with the third pin of the key switch, and one end of the filter device is grounded.
Further, referring to fig. 8, in some embodiments of the utility model, the second power module may include a voltage conversion chip, which may be of the type AMS1117; the input end of the voltage conversion chip can be connected with the first power supply module; the output end of the voltage conversion chip can be connected with the serial port isolation module; the output end of the voltage conversion chip can be connected with the trigger starting module; the output end of the voltage conversion chip can be connected with the storage chip;
further, in some embodiments of the present utility model, the current limiting device may include a resistor or a jumper, where the resistor and the jumper are resistive devices, so that the current passing through the chip interface may be effectively reduced, and the chip is protected. It should be noted that in other possible embodiments of the present utility model, the current limiting device may be other resistive devices or resistive integrated modules, such as a resistor-array device.
Further, in some embodiments of the utility model, the filter device may comprise an electrolytic capacitor or a non-polar capacitor; the interference caused by the instability of the circuit can be reduced by filtering the signal fed into the chip through the electrolytic capacitor with polarity or the nonpolar capacitor, and it should be noted that in other feasible embodiments of the utility model, the filtering device can also be other devices with filtering function or integrated modules, such as a plurality of capacitors or a module integrating the electrolytic capacitors.
Further, in some embodiments of the present utility model, referring to fig. 6, the indicator light module may include 4 LED lamps, where the 4 LED lamps may respectively emit four colors of yellow, green, blue and red, and since the chip burn-in test is usually placed in the case, the four colors are used to help the relevant personnel to clearly see the test result corresponding to the LED light emission outside the case.
In addition, the utility model also provides a chip testing device which can comprise a plurality of the chip testing circuits and an external power supply, wherein the chip testing circuits can be connected in parallel and then connected into the external power supply, and the external power supply can supply power to all the testing circuits.
The following describes the use principle of the chip test circuit of the present utility model:
specifically, referring to fig. 2-8, the test circuit includes a driving chip, a first power module, an indicator lamp module, a second power module, a USB download interface, an ESD protection module, a trigger starting module, and a serial port isolation module, where the number of indicator lamps is 4, and the indicator lamps are red, yellow, blue and green.
Firstly, the driving program is downloaded to the driving chip through the USB downloading interface, and the ESD protection module can protect the chip from being damaged by static electricity during downloading, so that the service life of the chip can be prolonged.
Secondly, after the downloading is finished, the internal memory chip can be driven to execute a specific test program by triggering a key of the starting module and then placing the internal memory chip in a high-low temperature environment (industrial grade: minus 40 ℃ to +85 ℃), for example, placing the internal memory chip in an aging box with a temperature adjusting function, starting a test flow. In the aging box, when the test is abnormal or after the test is finished, the driving chip can control the indicator lamp to display red, yellow, green and blue light to inform related personnel of the test completion or test failure.
In the description of the present utility model, it should be noted that, unless explicitly specified and defined otherwise, the term "switching" should be interpreted broadly, and for example, it may be a transformation or a conversion; the specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
In the description of the present specification, reference to the description of terms means that a particular structure or feature described in connection with an embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. The chip test circuit is characterized by comprising a driving chip, a first power supply module and an indicator lamp module, wherein the driving chip is used for testing a storage chip;
the driving chip is connected with the storage chip; the first power supply module is connected with the driving chip; the indicator light module is connected with the driving chip; the indicator light module at least comprises indicator lights with two different colors.
2. The chip test circuit of claim 1, further comprising a second power module, a USB download interface, an ESD protection module, a trigger start module, and a serial isolation module; the USB download interface is connected with the driving chip and is used for burning a driving program for the driving chip; the ESD protection module is connected with the driving chip and the USB download interface; the trigger starting module is connected with the driving chip; the trigger starting module is connected with the second power supply module; the second power supply module is connected with the memory chip and is used for supplying power to the memory chip and the trigger starting module; the serial port isolation module is connected with the driving chip, and the serial port isolation module is connected with the second power supply module.
3. The chip test circuit of claim 1, wherein the indicator light module further comprises a protection resistor;
the protection resistor is connected with the indicator lamp in series.
4. The chip test circuit of claim 2, wherein the ESD protection module comprises an ESD chip; the ESD chip comprises 6 pins, and a fifth pin of the ESD chip is connected with a power supply end of the driving chip; a second pin of the ESD chip is grounded; the sixth pin of the ESD chip is connected with the DM pin of the driving chip; the first pin of the ESD chip is connected with the DP pin of the driving chip.
5. The chip test circuit of claim 2, wherein the trigger-and-start module comprises a key switch, a current limiting device, and a filter device; the key switch comprises 4 pins, wherein the first pin and the second pin of the key switch are connected in parallel and then grounded, the third pin of the key switch is connected with the RST pin of the driving chip, and the fourth pin of the key switch is connected with the BOOT pin of the driving chip; one end of the current limiting device is connected with the output end of the second power supply module; the other end of the current limiting device is connected with a third pin of the key switch; one end of the filter device is connected with the third pin of the key switch, and one end of the filter device is grounded.
6. The chip test circuit of claim 2, wherein the second power module comprises a voltage conversion chip, and wherein an input terminal of the voltage conversion chip is connected to the first power module; the output end of the voltage conversion chip is connected with the serial port isolation module; the output end of the voltage conversion chip is connected with the trigger starting module; and the output end of the voltage conversion chip is connected with the storage chip.
7. The chip test circuit of claim 5, wherein the current limiting device comprises a resistor or a jumper.
8. The chip test circuit of claim 5, wherein the filter device comprises an electrolytic capacitor or a non-polar capacitor.
9. The chip test circuit of claim 1, wherein the indicator light module comprises 4 LED lights.
10. A chip testing device, comprising a plurality of chip testing circuits according to any one of claims 1 to 9 and an external power supply, wherein a plurality of the chip testing circuits are connected in parallel and then connected to the external power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320780780.0U CN219842810U (en) | 2023-03-31 | 2023-03-31 | Chip test circuit and test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320780780.0U CN219842810U (en) | 2023-03-31 | 2023-03-31 | Chip test circuit and test device |
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| Publication Number | Publication Date |
|---|---|
| CN219842810U true CN219842810U (en) | 2023-10-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320780780.0U Active CN219842810U (en) | 2023-03-31 | 2023-03-31 | Chip test circuit and test device |
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| CN (1) | CN219842810U (en) |
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- 2023-03-31 CN CN202320780780.0U patent/CN219842810U/en active Active
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