CN219777832U - Electric energy quality monitoring circuit and monitoring device - Google Patents

Abstract

The utility model discloses a power quality monitoring circuit and a monitoring device, and belongs to the field of power monitoring. Aiming at the problems of low efficiency, high cost and incapability of monitoring ultra-high harmonic in the prior art, the utility model provides a power quality monitoring circuit and a monitoring device. The power grid voltage and current signal processing circuit comprises a voltage sampling circuit, a current sampling circuit, a multi-core CPU chip and a FLASH chip, wherein voltage and current signals in the power grid are respectively processed through the voltage sampling circuit and the current sampling circuit and then are sent into the multi-core CPU chip for power quality monitoring, and storage information is mutually transmitted between the multi-core CPU chip and the FLASH chip. The method can realize the monitoring of ultra-high harmonic waves of 2KHz-150KHz under the condition of low cost.

Description

Electric energy quality monitoring circuit and monitoring device

Technical Field

The utility model relates to the field of power monitoring, in particular to a power quality monitoring circuit and a monitoring device.

Background

With the wide application of power electronics technology, harmonic pollution of a power system is increasingly serious, and the power system becomes a nuisance affecting the quality of electric energy. The main hazards of the method are that the electric energy quality index is deteriorated, the reliability of a power grid is reduced, the loss of the power grid is increased, the service life of electric equipment is shortened, communication equipment is interfered and the like. When the harmonic components in the power grid exceed the limit standards, the safety, reliability, stability and economy of the operation of the power system and the electric equipment are seriously affected, and the surrounding electric environment is also seriously polluted. During the power electronization process of the power system, new electric energy quality problems such as ultra-high harmonic wave of 2KHz-150KHz and the like are generated.

Most of the existing power quality online monitoring products adopt a multi-CPU technical scheme, the multi-CPU technical scheme often needs 2-3 CPUs to cooperatively work to jointly complete the power quality monitoring function, the implementation cost is high, and the data interaction efficiency among the multi-CPUs is low; the technical implementation scheme of the single-core CPU is adopted, and the cost and the implementation difficulty are reduced, but due to the performance limitation of the single-core CPU, the function of simply monitoring the electric energy quality can be realized, and the function of monitoring the ultra-high harmonic waves can not be monitored; the existing scheme can not meet the requirements of a novel power system on low cost and wide frequency domain monitoring of the power quality on-line monitoring.

The utility model discloses a novel Fourier transform-based power harmonic monitoring system, which consists of a voltage transformer, a current transformer, a signal conditioning circuit, an anti-aliasing filter, an A/D converter, a novel Fourier transform-based controller, a memory, an input module, a display, an external communication module and an alarm. The system can well solve the problems of spectrum aliasing, low frequency resolution capability, fence effect and spectrum leakage existing in the traditional harmonic monitoring system based on Fourier transform when harmonic analysis is carried out by utilizing Fourier transform, greatly improves the accuracy of electric power harmonic monitoring, adopts a double CPU technology in a controller, and improves the real-time performance of electric power harmonic monitoring. But it does not allow efficient on-line and real-time monitoring of ultra-high harmonics.

Disclosure of Invention

1. Technical problem to be solved

Aiming at the problems of low efficiency, high cost and incapability of monitoring ultra-high harmonic in the prior art, the utility model provides a power quality monitoring circuit and a monitoring device. The method can realize the monitoring of ultra-high harmonic waves of 2KHz-150KHz under the condition of low cost.

2. Technical proposal

The aim of the utility model is achieved by the following technical scheme.

The utility model provides an electric energy quality monitoring circuit, includes voltage sampling circuit, current sampling circuit, multicore CPU chip and FLASH chip, and voltage and current signal in the electric wire netting is after handling through voltage sampling circuit and current sampling circuit respectively, send into multicore CPU chip and carry out electric energy quality monitoring, transmits the storage information each other between multicore CPU chip and the FLASH chip.

Furthermore, the multi-core CPU chip is a heterogeneous multi-core CPU and comprises an ARM core and a floating point DSP core, wherein the DSP core comprises a real-time calculation module and a real-time acquisition module, and the signals converted by the voltage sampling circuit and the current sampling circuit are acquired in real time and calculated by the real-time calculation module; the DSP core comprises a timer for capturing interruption, measures the frequency of a fundamental wave of a power grid, controls PWM to output an AD conversion signal according to the measured power grid frequency, and further adjusts the AD sampling frequency in real time to realize synchronous sampling.

Further, the ARM core runs one operating system, such as an embedded Linux operating system, and the DSP core runs another operating system, such as an RTOS operating system.

Furthermore, the DSP core uses EDMA to access the AD chip through the GMPC interface and directly access the memory, namely directly access the L2SRAM to obtain the collected data, and the collected data is provided for the real-time calculation module to calculate.

Furthermore, the ARM core and the DSP core comprise a message queue module and a shared memory module, wherein the message queue module is used for inter-core communication, and the shared memory module is used for information and data interaction.

Furthermore, the voltage sampling circuit comprises a sampling circuit, an operational amplifier circuit, a first-order low-pass RC filter circuit and an ADC conversion circuit, wherein the collected voltage signals are filtered by the first-order low-pass RC filter circuit and then sent to the ADC conversion circuit, and then sent to the multi-core CPU chip through a bus.

Further, the frequency measuring circuit is further arranged for converting the collected sine wave signals into PWM square wave signals with the same frequency, and the multi-core CPU chip captures the PWM signals for measuring the frequency of the fundamental wave of the power grid and adjusts the sampling frequency in real time according to the frequency of the power grid.

Furthermore, the current sampling circuit comprises a current transformer, an operational amplifier circuit, a first-order RC low-pass filter circuit and an ADC conversion circuit, wherein the collected current signal is filtered by the first-order RC low-pass filter circuit and then sent to the ADC conversion circuit, and then sent to the multi-core CPU chip through a bus.

A power quality monitoring device comprising a power quality monitoring circuit as described above.

Still further still include touch-sensitive screen and communication interface, multicore CPU chip sends the information after handling into touch-sensitive screen display, and the ethernet that is connected through communication interface or communication module such as 4G/5G send to external system.

3. Advantageous effects

Compared with the prior art, the utility model has the advantages that:

the scheme realizes the wide-frequency-domain power quality synchronous monitoring function based on 1 heterogeneous multi-core CPU, and solves the problems that the existing multi-CPU scheme is low in efficiency, high in cost and low in single-core CPU scheme performance, and ultra-high harmonic cannot be monitored. The information and data interaction between the ARM core and the DSP core is performed by adopting an inter-core communication message queue and shared memory technology, so that the high-efficiency and rapid communication of the data between the two CPU cores is ensured, the effects of low cost and high efficiency are realized, and the ultra-high harmonic wave can be detected at the same time.

Drawings

FIG. 1 is a schematic diagram of the overall circuit of the present utility model;

FIG. 2 is a schematic diagram of a voltage sampling circuit according to an embodiment;

FIG. 3 is a schematic diagram of a current sampling circuit according to an embodiment;

FIG. 4 is a schematic diagram of a voltage acquisition and low pass filter circuit according to an embodiment;

fig. 5 is a schematic diagram of a current collection and low pass filtering circuit according to an embodiment.

Detailed Description

The utility model will now be described in detail with reference to the drawings and the accompanying specific examples.

Example 1

The implementation scheme realizes the wide-frequency-domain power quality synchronous monitoring function based on one heterogeneous multi-core CPU, solves the problems that the multi-CPU scheme has low efficiency and high cost and the single-core CPU scheme has low performance and cannot monitor ultra-high harmonic waves, and can be widely applied to the power quality on-line monitoring of novel power systems.

As shown in fig. 1, the on-line monitoring circuit module of the scheme comprises a voltage sampling circuit, a current sampling circuit, a multi-core CPU chip and a FLASH chip. The voltage and current signals in the power grid are respectively processed by a voltage sampling circuit and a current sampling circuit and then are sent to a multi-core CPU chip, and the multi-core CPU chip and the FLASH chip mutually transmit storage information; the multi-core CPU chip monitors the collected information on line.

The multi-core CPU chip 5 in this embodiment may be a heterogeneous multi-core CPU, and mainly includes an ARM core and a floating-point DSP core, where the main frequency of the ARM core is 1ghz and the main frequency of the DSP core is 750MHz. The DSP core comprises a real-time calculation module and a real-time acquisition module, the real-time acquisition module acquires signals converted by the AD chip and calculates the signals by the real-time calculation module, the DSP core captures interruption by using hardware of a timer, accurately measures the frequency of a fundamental wave of a power grid, controls the high-precision PWM to output the converted signals of the AD according to the measured frequency of the power grid in real time, and further adjusts the sampling frequency of the AD in real time to realize high-precision synchronous sampling; the DSP core uses the EDMA to access the AD chip through the GMPC interface, the EDMA is used for directly pushing the acquired data into the L2SRAM, the L2SRAM is a shared memory, the DSP core directly accesses the L2SRAM to obtain the acquired data, and the acquired data is provided for the real-time calculation module for calculation; in the actual use process, the ARM core runs an embedded Linux operating system and carries non-real-time services such as equipment management, external communication, man-machine interfaces, data statistics, event recording, fixed value management, time synchronization and the like; the DSP core runs an RTOS operating system and carries real-time services such as high-speed synchronous sampling, calculation of all parameter indexes of the electric energy quality and the like. And the ARM core and the DSP core adopt an inter-core communication message queue and shared memory technology to carry out information and data interaction, so that the high-efficiency and rapid communication of data between the two CPU cores is ensured.

The voltage sampling circuit and the current sampling circuit can adopt the existing circuits and are used for carrying out corresponding conversion and conditioning after collecting voltage and current, so as to realize real-time sampling of the voltage and the current of the power grid.

The voltage sampling circuit in this embodiment is shown in fig. 2 and fig. 4, and includes an analog quantity conditioning and filtering circuit, where the processed analog signal is sent to an ADC conversion chip (i.e. ADC chip) and the processed signal is sent to a multi-core CPU chip for processing.

The voltage sampling circuit converts the acquired power grid voltage from a high-voltage analog signal to a low-voltage analog signal through the voltage conditioning circuit, the acquired analog signal is sent to the real-time sampling chip for analog-to-digital conversion after two times of filtering, the acquired data is finally sent to the multi-core CPU through the BUS BUS, the analog quantity conditioning and filtering circuit is a low-pass filtering circuit, the problems of poor anti-interference capacity, high design requirement level and the like of an analog quantity acquisition circuit are considered in design, a first-order low-pass RC filtering circuit is added in each analog quantity acquisition circuit, the circuit can effectively weaken the coupling of the power grid and the device and the high-frequency interference of radiation to the analog circuit, the high-frequency and clutter interference of the analog acquisition circuit is reliably reduced, and the analog quantity acquisition precision is effectively improved; as shown in figure 4 of the drawings,

the high-voltage analog signal of the power grid is converted into a small signal with the acceptable identification analog quantity of the ADC chip through a high-precision low-temperature drift resistor and a high-precision operational amplifier, a large amount of high-frequency interference signals are contained in the power grid signal, a low-cost high-reliability first-order RC low-pass filter circuit, namely RC filter formed by a resistor R16 and a capacitor C2, is added at the back end of operational amplification acquisition, the high-frequency interference of the power grid is reliably filtered, and the precision of the analog signal is effectively improved;

the voltage transformation calculation formula is: uo= (r1/(r1+r2+r3+r4+r5)). Uin;

resistance requirements: r1+r2+r3+r4+r5=r6+r7+r8+r9+r10; r11=r12. In the embodiment, the resistor of RJM16M0207B7T1003 type can be adopted.

Preferably, the synchronous sampling device also comprises a frequency measurement circuit, namely a zero crossing detection circuit, which mainly converts sine wave signals into PWM square wave signals with the same frequency through a hysteresis comparator principle, and the multi-core CPU chip captures the PWM signals through a capture interface of a timer for measuring the frequency of a fundamental wave of a power grid, and adjusts the frequency of AD sampling in real time according to the frequency of the power grid, so as to realize the synchronous sampling function.

The current sampling circuit in this embodiment is shown in fig. 3 and 5, and includes an analog quantity conditioning and filtering circuit, where the processed analog signal is sent to an ADC conversion chip (i.e. ADC chip) and the processed signal is sent to a multi-core CPU chip for processing.

The current sampling circuit converts the collected power grid current into a low-voltage analog signal through the current conditioning circuit, the collected analog signal is sent to the real-time sampling chip for analog-to-digital conversion after twice filtering, and finally the collected data is uplifted to the multi-core CPU through the BUS BUS, the front end of the current signal collecting circuit is provided with a high-precision CT current transformer, the current loop adopts the high-linearity low-temperature drift current transformer to collect the power grid current, secondary circuit isolation is effectively realized, high-frequency interference of the power grid current signal is reliably filtered, the high-low-voltage loop is effectively isolated, the reliability and the safety of circuit design are improved, and the type of the current transformer is one choice of the embodiment, and can be adjusted according to requirements. After a large current signal in a power grid is converted into a small signal through CT, the CT secondary side driving capability is poor due to the limitation of a CT process, and in order to solve the problem, the circuit is arranged at the rear end of a high-precision operational amplifier circuit, so that the acquired analog magnitude is matched with a value (Vp-p=10V) required by an ADC chip, and the problem of poor CT secondary side driving capability is reliably avoided. The low-cost and high-reliability first-order RC low-pass filter circuits (R17 and C3) are added at the back end of the operational amplifier acquisition, so that the high-frequency interference of the power grid is reliably filtered, and the accuracy of analog signals is effectively improved; the current transformation calculation formula is: uo2=io×r13; iin/io=2000.

The corresponding ADC chip adopts a 16-bit 8-channel ADC chip, the maximum data rate of each channel is 510kSPS, a GPMC high-speed interface is adopted between the ADC chip and a multi-core CPU chip, the multi-core CPU chip adopts high-precision PWM (eHRPWM) to control a CONVST pin of the ADC chip, and data read from the AD chip is directly pushed into an L2SRAM cache through EDMA by using hardware interrupt, so that the design ensures the precision and the transmission efficiency of the data under high sampling rate, and finally meets the requirement of electric energy quality on 2KHz-150KHz ultra-high harmonic measurement. Of course, the specific chip model can be adjusted according to the needs, and only the functions required by users can be selected.

Preferably, the system also comprises a touch screen and a communication interface, wherein the multi-core CPU chip sends the processed information to the touch screen for display, and the processed information can be sent to an external system through the communication interface by using an Ethernet or a 4G/5G communication module.

The scheme realizes the wide-frequency-domain power quality synchronous monitoring function based on 1 heterogeneous multi-core CPU, and solves the problems that the existing multi-CPU scheme is low in efficiency, high in cost and low in single-core CPU scheme performance, and ultra-high harmonic cannot be monitored. And the ARM core and the DSP core adopt an inter-core communication message queue and shared memory technology to carry out information and data interaction, so that the high-efficiency and rapid communication of data between the two CPU cores is ensured. Therefore, the effects of low cost and high efficiency are realized, and the ultra-high harmonic wave can be detected at the same time.

The foregoing has been described schematically the utility model and embodiments thereof, which are not limiting, but are capable of other specific forms of implementing the utility model without departing from its spirit or essential characteristics. The drawings are also intended to depict only one embodiment of the utility model, and therefore the actual construction is not intended to limit the claims, any reference number in the claims not being intended to limit the claims. Therefore, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical scheme are not creatively designed without departing from the gist of the present utility model, and all the structural manners and the embodiment are considered to be within the protection scope of the present patent. In addition, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the inclusion of a plurality of such elements. The various elements recited in the product claims may also be embodied in software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.

Claims (10)

1. The power quality monitoring circuit is characterized by comprising a voltage sampling circuit, a current sampling circuit, a multi-core CPU chip and a FLASH chip, wherein voltage and current signals in a power grid are respectively processed by the voltage sampling circuit and the current sampling circuit and then are sent to the multi-core CPU chip for power quality monitoring, and storage information is mutually transmitted between the multi-core CPU chip and the FLASH chip.

2. The power quality monitoring circuit according to claim 1, wherein the multi-core CPU chip is a heterogeneous multi-core CPU, and comprises an ARM core and a floating-point DSP core, the DSP core includes a real-time calculation module and a real-time acquisition module, and the signals converted by the voltage sampling circuit and the current sampling circuit are acquired in real time and calculated by the real-time calculation module; the DSP core comprises a timer capturing interrupt, is used for measuring the frequency of a fundamental wave of a power grid, controlling a PWM to output an AD conversion signal according to the measured power grid frequency, and adjusting the AD sampling frequency in real time to synchronously sample.

3. A power quality monitoring circuit according to claim 2 wherein the ARM core runs one operating system and the DSP core runs another operating system.

4. A power quality monitoring circuit according to claim 2 or 3, wherein the DSP core accesses the AD chip and directly accesses the memory to obtain the collected data, and provides the collected data to the real-time calculation module for calculation.

5. A power quality monitoring circuit according to claim 2 or 3, wherein the ARM core and the DSP core comprise a message queue module for inter-core communication and a shared memory module for information and data interaction.

6. The power quality monitoring circuit according to claim 1, wherein the voltage sampling circuit comprises a sampling circuit and an operational amplifier circuit, and the collected voltage signal is filtered by the filter circuit and sent to the ADC conversion circuit, and then sent to the multi-core CPU chip through the bus.

7. The power quality monitoring circuit of claim 6, further comprising a frequency measurement circuit for converting the collected sine wave signals into PWM square wave signals of the same frequency, wherein the multi-core CPU chip captures the PWM signals for measuring the frequency of the fundamental wave of the power grid and adjusts the sampling frequency in real time according to the frequency of the power grid.

8. The power quality monitoring circuit according to claim 1, wherein the current sampling circuit comprises a current transformer and an operational amplifier circuit, and the collected current signal is filtered by the filter circuit, sent to the ADC conversion circuit, and then sent to the multi-core CPU chip by the bus.

9. A power quality monitoring device comprising a power quality monitoring circuit as claimed in any one of claims 1 to 8.

10. The power quality monitoring device of claim 9, further comprising a touch screen and a communication interface, wherein the multi-core CPU chip sends the processed information to the touch screen for display, and the communication module connected through the communication interface sends the processed information to an external system.