CN219697609U - Power amplifier bias time sequence control circuit - Google Patents
Power amplifier bias time sequence control circuit Download PDFInfo
- Publication number
- CN219697609U CN219697609U CN202320366529.XU CN202320366529U CN219697609U CN 219697609 U CN219697609 U CN 219697609U CN 202320366529 U CN202320366529 U CN 202320366529U CN 219697609 U CN219697609 U CN 219697609U
- Authority
- CN
- China
- Prior art keywords
- transistor
- power amplifier
- comparator
- voltage
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004146 energy storage Methods 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 238000010295 mobile communication Methods 0.000 abstract description 12
- 229910002601 GaN Inorganic materials 0.000 description 25
- 238000000034 method Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides a power amplifier bias time sequence control circuit, and belongs to the technical field of radio frequency power amplifiers. The circuit comprises a power amplifier, a grid voltage power supply module, a drain voltage power supply module, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, a processor, a three-input logic AND gate, an NPN transistor, a PNP transistor, an energy storage capacitor and a radio frequency choke coil; and when the TDD time sequence levels output by the first comparator, the second comparator and the processor are high levels, the three-input logic AND gate outputs high levels, and the voltage leakage power supply module supplies power to the drain electrode of the power amplifier. The utility model realizes the rapid switching of the mobile communication TDD time sequence stage control GaN power amplifier in the opening and closing states and the rapid switching of the mobile communication TDD time sequence stage control power amplifier energy storage capacitor charge and discharge under the premise of meeting the power amplifier bias voltage power on-off time sequence protection.
Description
Technical Field
The utility model relates to the technical field of radio frequency power amplifiers, in particular to a power amplifier bias voltage time sequence control circuit.
Background
The GaN power amplifier is particularly suitable for being applied to high-frequency and high-power radio-frequency power amplifiers due to the characteristics of better broadband semiconductor characteristics, high saturated electron mobility, high breakdown field strength and the like. The GaN power amplifier needs two power supplies of gate voltage and drain voltage to supply power, the power-on time sequence requires the gate voltage to be earlier than the drain voltage, and the power-off time sequence requires the drain voltage to be earlier than the gate voltage.
In the prior art, the grid voltage is generally adjusted by a certain bias circuit to realize the optimal working state of the power amplifier, as described in patent document with publication number of CN209627325U, a digital-to-analog conversion chip is adopted to realize the grid voltage adjustment, and patent document with publication number of CN107528553A and patent document with publication number of CN205725694U adopt a resistor voltage division mode to realize the grid voltage adjustment. In any adjustment mode, abnormal conditions, such as the possibility that the grid voltage accidentally exceeds the rated value range of the grid voltage of the power amplifier, exist in specific operation. If the grid voltage is mistakenly beyond the rated value range of the grid voltage of the power amplifier in the adjustment process and the drain electrode is electrified, or the grid voltage is accidentally powered down due to some uncontrollable factors, the power amplifier circuit can be damaged.
In addition, in order to save power consumption, the GaN power amplifier generally works in a pulse state along with the TDD transceiving time sequence of the mobile communication, and the current demand is also pulse. In order to meet the pulse current requirement of the emission period, the transient response capability is improved, and an energy storage capacitor is generally added at the power supply position of the drain electrode of the power amplifier. The large amount of charges stored in the energy storage capacitor must be released after the power amplifier is powered off, otherwise, the power amplifier and other modules may be damaged. On the premise of meeting the requirement of the bias power-on and power-off time sequence, the energy stored by the radio frequency choke coil also needs to be released in time after the power amplifier is powered off.
The bias voltage protection circuit of the existing GaN power amplifier has the following steps:
the patent document with publication number CN113965173A discloses a power supply time sequence control system and a control method of a GaN power amplifier, wherein the power supply time sequence control system comprises a voltage module, a step-down voltage stabilizer, a logic gate, a voltage monitor, a multi-path grid voltage generator, a voltage division module and the GaN power amplifier, and solves the problem of power amplifier bias power-on and power-off time sequence protection. And when the grid voltage is smaller than the set reference value, the drain electrode of the power amplifier is electrified. The patent cannot judge whether the set grid voltage value exceeds the lower limit voltage value of the rated power amplifier grid voltage value, and can not realize the rapid switching of the charge and discharge of the energy storage module under the control of the TDD time sequence on the premise of power amplifier bias power on-off time sequence protection.
Patent document with publication number of CN113992164A discloses a GaN power amplifier negative gate voltage bias protection circuit and a working method thereof, which realize the rapid switching of the bias protection circuit of the GaN power amplifier tube in the state of controlling the power amplifier tube to be opened and closed at the time sequence level of 5G mobile communication TDD. The patent cannot judge whether the set grid voltage value meets the upper limit reference voltage and the lower limit reference voltage range of the power amplifier grid voltage, and can realize the rapid switching of the charge and discharge of the energy storage module under the control of the TDD time sequence on the premise of power amplifier bias voltage power-on and power-off time sequence protection.
The Chinese patent document with publication number of CN110048677A discloses a power amplifier power supply control method and device, which saves a slow start circuit, MOS and Vg output high-capacity energy storage capacitors on a Vd line, improves the reliability of the circuit, and saves the area and cost of a single board on the premise of meeting the power amplifier power supply and power supply time sequence. The patent cannot judge whether the set grid voltage value meets the upper limit reference voltage and the lower limit reference voltage range of the power amplifier grid voltage, and can realize the rapid switching of the charge and discharge of the energy storage module under the control of the TDD time sequence on the premise of power amplifier bias voltage power-on and power-off time sequence protection.
The Chinese patent document with publication number of CN215580896U discloses an automatic discharging circuit of a power amplifier energy storage capacitor, which can rapidly release energy in an energy storage module under the condition of power failure and avoid damaging other components in the circuit. The patent cannot judge whether the set grid voltage value meets the upper limit reference voltage and the lower limit reference voltage range of the power amplifier grid voltage, and can realize the rapid switching of the charge and discharge of the energy storage module under the control of the TDD time sequence on the premise of power amplifier bias voltage power-on and power-off time sequence protection.
Chinese patent publication No. CN110098809a discloses a gallium nitride power amplifier timing sequence protection power supply device, which performs dynamic temperature compensation on gate voltage on the premise of meeting the requirement of power amplifier power on-off timing sequence protection. The patent compares the grid voltage with a preset upper limit reference voltage value and a preset lower limit reference voltage value to confirm that the grid voltage is in a range required by the grid voltage of the power amplifier. The patent cannot realize the rapid switching of the TDD time sequence stage control power amplifier in the opening state and the closing state and the rapid switching of the energy storage module under the control of the TDD time sequence.
Disclosure of Invention
In view of the above, the present utility model provides a power amplifier bias voltage timing control circuit, which can realize the fast switching of the mobile communication TDD timing stage control GaN power amplifier in the on and off states and the fast switching of the mobile communication TDD timing stage control power amplifier storage capacitor charge and discharge under the premise of satisfying the power amplifier bias voltage power on and off timing protection.
In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:
a power amplifier bias time sequence control circuit comprises a GaN power amplifier; the device also comprises a grid voltage power supply module, a drain voltage power supply module, a three-input logic AND gate, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, an energy storage module and a processor;
the output end of the grid voltage power supply module is simultaneously connected to the non-inverting input end of the first comparator, the inverting input end of the second comparator and the input end of the inverter; the first reference voltage module is connected to the inverting input end of the first comparator, and the second reference voltage module is connected to the non-inverting input end of the second comparator; the output end of the inverter is connected to the grid electrode of the GaN power amplifier;
when the output voltage value of the grid voltage power supply module is smaller than the voltage value of the first reference voltage module or larger than the voltage value of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage value of the grid voltage power supply module is larger than the voltage value of the first reference voltage module and smaller than the voltage value of the second reference voltage module, the first comparator and the second comparator both output high level;
the output end of the first comparator, the output end of the second comparator and the TDD time sequence level output port of the processor are sequentially connected to three input ends of the three-input logic AND gate; when the TDD time sequence level output by the processor is high level and the first comparator and the second comparator both output high level, the three-input logic AND gate outputs high level, otherwise, the three-input logic AND gate outputs low level;
the output end of the three-input logic AND gate is connected with a first passage for controlling the power on and power off of the GaN power amplifier drain electrode and a second passage for controlling the charge and discharge of the energy storage module; the first path comprises a first transistor and a second transistor, and the second path comprises a third transistor and a fourth transistor;
when the three-input logic AND gate outputs high level, the first transistor and the second transistor are conducted, and at the moment, the drain voltage power supply module supplies power to the drain electrode of the GaN power amplifier through the second transistor and charges the energy storage module; when the three-input logic AND gate outputs high level, the third transistor is turned on, the fourth transistor is turned off, and at the moment, the energy storage module cannot discharge;
when the three-input logic AND gate outputs a low level, the first transistor and the second transistor are turned off, and at the moment, the drain electrode of the GaN power amplifier is powered off; when the three-input logic AND gate outputs low level, the third transistor is turned off, and the fourth transistor is turned on, and at the moment, the energy storage module discharges.
Further, the first transistor, the third transistor and the fourth transistor are NPN transistors, and the second transistor is a PNP transistor.
Further, the energy storage module is arranged at the drain electrode of the GaN power amplifier and comprises an energy storage capacitor and a radio frequency choke coil.
Further, the base electrode of the first transistor is connected with the output of the three-input logic AND gate, the emitter electrode of the first transistor is grounded through a resistor, and the collector electrode of the first transistor is connected with the base electrode of the second transistor;
the base electrode of the third transistor is connected with the output of the three-input logic AND gate, the emitter electrode of the third transistor is grounded, the collector electrode of the third transistor is pulled up to 5V through a resistor to be externally supplied with power, the collector electrode of the third transistor is also connected with the base electrode of the fourth transistor, the emitter electrode of the fourth transistor is grounded through a resistor, and the collector electrode of the fourth transistor is connected with the drain electrode of the GaN power amplifier.
The beneficial effects of the utility model are as follows:
1. the utility model can realize the rapid switching of the mobile communication TDD time sequence stage control GaN power amplifier in the opening and closing states and the rapid switching of the mobile communication TDD time sequence stage control power amplifier energy storage module charge and discharge.
2. The utility model adopts two comparators and a three-input logic AND gate circuit, which can prevent the problem that the grid voltage of the power amplifier is mistakenly beyond the rated value range of the grid voltage of the power amplifier (such as overlarge adjustment range of a sliding rheostat or abnormal work of a digital-analog converter) in the grid voltage adjustment process, and the power amplifier is damaged due to the fact that the drain electrode is electrified.
Drawings
Fig. 1 is a schematic diagram of a power amplifier bias timing control circuit according to an embodiment of the utility model.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent and understandable.
As shown in fig. 1, a power amplifier bias time sequence control circuit includes a GaN power amplifier, a gate voltage supply module, a drain voltage supply module, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, a processor, a three-input logic and gate circuit, NPN transistors Q1, Q3, Q4, a PNP transistor Q2, an energy storage capacitor C1, and a radio frequency choke L1.
The output voltage of the grid voltage power supply module is converted into negative voltage through the inverter and then is supplied to the grid electrode of the power amplifier, and the output of the grid voltage power supply module is simultaneously connected to the non-inverting input end of the first comparator and the inverting input end of the second comparator. The first reference voltage module is connected to the inverting input terminal of the first comparator, and the second reference voltage module is connected to the non-inverting input terminal of the second comparator. The first reference voltage module is set with reference to the lower limit value of the rated value of the grid voltage of the power amplifier (if the lower limit value of the grid voltage is-2.2V, the first reference voltage is set to be 2.2V), and the second reference voltage module is set with reference to the upper limit value of the rated value of the grid voltage of the power amplifier (if the upper limit value of the grid voltage is-4V, the second reference voltage is set to be 4V). When the output voltage value of the grid voltage power supply module is smaller than the voltage value of the first reference voltage module or larger than the voltage value of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage value of the grid voltage power supply module is larger than the voltage value of the first reference voltage module and smaller than the voltage value of the second reference voltage module, the first comparator and the second comparator both output high level.
The output end of the first comparator, the output end of the second comparator and the TDD time sequence level output port of the processor are sequentially connected to three input ends of the three-input logic AND gate. When the TDD time sequence level output by the processor is high level and the first comparator and the second comparator both output high level, the logic AND gate outputs high level, otherwise, the logic AND gate outputs low level.
And the three-input logic AND gate controls the power amplifier drain electrode to power on and power off, and the power amplifier energy storage module charges and discharges the switching circuit. The working logic is as follows:
1) When the three-input logic AND gate outputs a high level, the base of the transistor Q1 is high level, and the transistor Q1 is conducted. After Q1 is turned on, the base of transistor Q2 is pulled down by resistor R1 and Q2 is turned on. The leakage voltage power supply module supplies power to the drain electrode of the power amplifier through Q2, and simultaneously charges the energy storage capacitor C1 and the radio frequency choke coil L1; at this time, the transistor Q3 is turned on, the base of the transistor Q4 is pulled down, the transistor Q4 is turned off, and the energy storage capacitor C1 and the rf choke L1 cannot be discharged.
2) When the three-input logic AND gate outputs a low level, the base electrode of the transistor Q1 is pulled down, the transistor Q1 is turned off, the transistor Q2 is turned off, and the drain electrode of the power amplifier is powered off; at this time, the transistor Q3 is turned off, the base of Q4 is pulled up by the voltage of 5V through the resistor R2, Q4 is turned on, and the energy storage capacitor C1 and the rf choke L1 are rapidly discharged through the resistor R3.
In the circuit, the output voltage of the grid voltage power supply module is converted into negative voltage through the inverter to be supplied to the grid electrode of the power amplifier, when the TDD time sequence level output by the first comparator, the second comparator and the processor is high, the three-input logic AND gate outputs high level, the voltage leakage power supply module supplies power to the drain electrode of the power amplifier through the Q2, when the three-input logic AND gate circuit outputs low level, the power amplifier is turned off, and the C1 and the L1 are rapidly discharged through the transistor Q4. The circuit realizes the fast switching of the mobile communication TDD time sequence stage control GaN power amplifier in the on and off states and the fast switching of the mobile communication TDD time sequence stage control power amplifier energy storage capacitor charge and discharge under the premise of meeting the power amplifier bias voltage power on and off time sequence protection.
The specific control process of the circuit is as follows:
step 1: the grid voltage power supply module outputs positive voltage, and the positive voltage is converted into negative voltage through the inverter to supply power to the grid electrode of the power amplifier;
step 2: the first reference voltage module is set with reference to the lower limit value of the rated value of the grid voltage of the power amplifier (if the lower limit value of the grid voltage is-2.2V, the first reference voltage is set to be 2.2V), and the second reference voltage module is set with reference to the upper limit value of the rated value of the grid voltage of the power amplifier (if the upper limit value of the grid voltage is-4V, the second reference voltage module is set to be 4V). When the output voltage value of the grid voltage power supply module is larger than the first reference voltage value and smaller than the second reference voltage value, the first comparator and the second comparator both output high level;
step 3: the three-input logic AND gate outputs corresponding levels by combining the first comparator, the second comparator and the TDD time sequence level state output by the processor;
step 4: transistors Q1, Q2 control the on and off of drain voltage according to the state of the output voltage of the three-input logic AND gate;
step 5: the transistors Q3 and Q4 control the opening and closing of the discharging loop of the energy storage module according to the state of the output voltage of the three-input logic AND gate.
In the using process of the GaN power amplifier, firstly, the power on-off time sequence of the grid electrode and the drain electrode is concerned, secondly, how to ensure that the grid voltage is in the rated value range of the power amplifier and then the drain electrode is electrified, and thirdly, how to quickly release the energy in the energy storage module under the condition of outage.
When the power amplifier is powered on: the output voltage of the grid voltage power supply module is supplied to the grid electrode of the power amplifier after being reversed. And judging whether the output voltage of the grid voltage power supply module is within a voltage range defined by the first reference voltage module and the second reference voltage module. And if the grid voltage meets the range requirement of the grid voltage rated value of the power amplifier, the first comparator and the second comparator both output high level. At this time, if the TDD time sequence level is a high level, the high level indicates that the transmitting channel is opened, the three-input logic and gate outputs a high level, the transistors Q1 and Q2 are turned on, and the drain voltage power supply module supplies power to the drain electrode of the power amplifier through the transistor Q2.
When power is turned off: when the TDD timing level is low, the low indicates that the receive channel is on, requiring the transmit channel to be turned off. At this time, the three-input logic AND gate outputs a low level to turn off the transistor Q1, so that the emitter and the base of the transistor Q2 cannot form an effective voltage drop, and the transistor Q2 is turned off. Finally, the output voltage of the voltage leakage power supply module cannot be supplied to the drain electrode of the power amplifier, the power amplifier is in a closed state, and the transmitting channel is closed.
When the energy storage module is charged: when the TDD time sequence level is high and the three-input logic and gate outputs high, the transistors Q1, Q2 are turned on, and the drain voltage supply module charges the energy storage capacitor C1 and the radio frequency choke L1 through the transistor Q2. At this time, the transistor Q3 is turned on, Q4 is turned off, and the energy storage capacitor C1 and the rf choke L1 cannot be discharged through the resistor R3.
When the energy storage module discharges: when the TDD timing level is low, the three-input logic and gate outputs a low level, the base of transistor Q3 is pulled low, and Q3 is turned off. The base electrode of Q4 is pulled up through a resistor R2 by 5V voltage, Q4 is conducted, and the power amplifier energy storage capacitor C1 and the radio frequency choke coil L1 are rapidly discharged through a resistor R3.
During use, the following anomalies may be encountered:
1. the grid voltage power supply module is abnormally powered down, so that the first comparator and the second comparator both output low level, the three-input logic AND gate outputs low level, Q1 and Q2 are turned off, the drain voltage of the GaN power amplifier is turned off, and the power amplifier is protected;
2. in the grid voltage adjusting process, the grid voltage of the power amplifier unexpectedly exceeds the rated value range of the power amplifier, for example, the rated value range of the grid voltage of the power amplifier is-4V to-2.2V, when the grid voltage power supply module outputs 2.1V, namely the voltage of a supply grid electrode is-2.1V, the first comparator outputs low level, the three-input logic AND gate outputs low level, Q1 and Q2 are closed, the drain voltage of the GaN power amplifier is closed, and the power amplifier is protected.
In summary, in the power amplifier bias time sequence control circuit provided by the utility model, the grid electrode is firstly electrified and the drain electrode is firstly electrified, so that the time sequence requirement of GaN power amplifier use is met. In addition, the utility model can realize the rapid switching of the mobile communication TDD time sequence stage control GaN power amplifier in the opening and closing states, and the rapid switching of the mobile communication TDD time sequence stage control power amplifier energy storage module charge and discharge.
Having shown and described embodiments of the present utility model, it is to be understood that the above-described embodiments are illustrative and are not to be construed as limiting the utility model. The above-described embodiments may be numbered, modified, substituted and altered within the scope of the utility model by those skilled in the art without departing from the principles and spirit of the utility model. In general, the scope of the utility model is defined by the appended claims and equivalents thereof.
Claims (4)
1. A power amplifier bias time sequence control circuit comprises a GaN power amplifier; the device is characterized by further comprising a grid voltage power supply module, a drain voltage power supply module, a three-input logic AND gate, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, an energy storage module and a processor;
the output end of the grid voltage power supply module is simultaneously connected to the non-inverting input end of the first comparator, the inverting input end of the second comparator and the input end of the inverter; the first reference voltage module is connected to the inverting input end of the first comparator, and the second reference voltage module is connected to the non-inverting input end of the second comparator; the output end of the inverter is connected to the grid electrode of the GaN power amplifier;
when the output voltage value of the grid voltage power supply module is smaller than the voltage value of the first reference voltage module or larger than the voltage value of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage value of the grid voltage power supply module is larger than the voltage value of the first reference voltage module and smaller than the voltage value of the second reference voltage module, the first comparator and the second comparator both output high level;
the output end of the first comparator, the output end of the second comparator and the TDD time sequence level output port of the processor are sequentially connected to three input ends of the three-input logic AND gate; when the TDD time sequence level output by the processor is high level and the first comparator and the second comparator both output high level, the three-input logic AND gate outputs high level, otherwise, the three-input logic AND gate outputs low level;
the output end of the three-input logic AND gate is connected with a first passage for controlling the power on and power off of the GaN power amplifier drain electrode and a second passage for controlling the charge and discharge of the energy storage module; the first path comprises a first transistor and a second transistor, and the second path comprises a third transistor and a fourth transistor;
when the three-input logic AND gate outputs high level, the first transistor and the second transistor are conducted, and at the moment, the drain voltage power supply module supplies power to the drain electrode of the GaN power amplifier through the second transistor and charges the energy storage module; when the three-input logic AND gate outputs high level, the third transistor is turned on, the fourth transistor is turned off, and at the moment, the energy storage module cannot discharge;
when the three-input logic AND gate outputs a low level, the first transistor and the second transistor are turned off, and at the moment, the drain electrode of the GaN power amplifier is powered off; when the three-input logic AND gate outputs low level, the third transistor is turned off, and the fourth transistor is turned on, and at the moment, the energy storage module discharges.
2. The power amplifier bias timing control circuit of claim 1, wherein the first transistor, the third transistor, and the fourth transistor are NPN transistors and the second transistor is a PNP transistor.
3. The power amplifier bias timing control circuit of claim 1, wherein the energy storage module is disposed at a drain of the GaN power amplifier and comprises an energy storage capacitor and a radio frequency choke.
4. The power amplifier bias timing control circuit of claim 2, wherein the base of the first transistor is connected to the output of the three-input logic and gate, the emitter of the first transistor is grounded through a resistor, and the collector of the first transistor is connected to the base of the second transistor;
the base electrode of the third transistor is connected with the output of the three-input logic AND gate, the emitter electrode of the third transistor is grounded, the collector electrode of the third transistor is pulled up to 5V through a resistor to be externally supplied with power, the collector electrode of the third transistor is also connected with the base electrode of the fourth transistor, the emitter electrode of the fourth transistor is grounded through a resistor, and the collector electrode of the fourth transistor is connected with the drain electrode of the GaN power amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320366529.XU CN219697609U (en) | 2023-03-02 | 2023-03-02 | Power amplifier bias time sequence control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320366529.XU CN219697609U (en) | 2023-03-02 | 2023-03-02 | Power amplifier bias time sequence control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219697609U true CN219697609U (en) | 2023-09-15 |
Family
ID=87938236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320366529.XU Active CN219697609U (en) | 2023-03-02 | 2023-03-02 | Power amplifier bias time sequence control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219697609U (en) |
-
2023
- 2023-03-02 CN CN202320366529.XU patent/CN219697609U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11165423B2 (en) | Power switch drive circuit and device | |
| US9069365B2 (en) | DC-DC converter enabling rapid output voltage changes | |
| US8725218B2 (en) | Multimode operation DC-DC converter | |
| CN101458536B (en) | External control mode switching regulator integrated circuit, power supply system applying same and control method of integrated circuit | |
| CN112615425B (en) | Detection control circuit | |
| CN104753330A (en) | Soft start method of power management | |
| CN114865905A (en) | High-voltage started switch power supply | |
| CN216929868U (en) | Input protecting circuit for anti-impact MOS tube | |
| CN118054533B (en) | Controllable charging circuit for electric automobile | |
| CN110048677B (en) | Power amplifier power supply control method and device | |
| Kim et al. | 33.9 A hybrid switching supply modulator achieving 130MHz envelope-tracking bandwidth and 10W output power for 2G/3G/LTE/NR RF power amplifiers | |
| CN219697609U (en) | Power amplifier bias time sequence control circuit | |
| CN118041327A (en) | Integrated bootstrap switching circuit suitable for high-voltage GaN half-bridge gate driving chip | |
| US20240007002A1 (en) | Switching power supply protection circuit and power supply system | |
| CN116260403A (en) | Power amplifier bias time sequence control circuit | |
| CN110474532B (en) | Circuit for switching working modes of charge pump without power failure under load and implementation method thereof | |
| CN115694373A (en) | Power supply unit and communications facilities of gaN power amplifier | |
| CN116054610A (en) | AC-DC converter, controller, driving system and driving method | |
| CN112769103B (en) | Transient supporting protection system for super capacitor | |
| CN108111003B (en) | Thyristor driving circuit and method | |
| CN110165880B (en) | Circuit and method for stabilizing output voltage of switching circuit | |
| CN111883085A (en) | Device for improving stable work of liquid crystal equipment | |
| CN219576854U (en) | D-type gallium nitride switch driving circuit and switching power supply circuit | |
| CN220440412U (en) | 5G communication power-down protection circuit | |
| US20230170809A1 (en) | Two-Transistor Flyback Conversion Circuit, Power Module, Electric Vehicle, and Control Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |