CN219695748U - Data processing circuit and wind speed detection device - Google Patents
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Abstract
The present disclosure provides a data processing circuit and a wind speed detection apparatus, wherein the data processing circuit includes: an analog-to-digital conversion unit; an input interface for receiving data output by the analog-to-digital conversion unit; a first memory unit; a first DMA unit for transferring data of the input interface to the first memory unit; a second memory unit; a processing unit for processing the data stored in the first memory unit to generate a processing result and storing it in the second memory unit; a communication interface; a second DMA unit for transferring the processing result from the second memory unit to the communication interface; and a communication unit for transmitting the processing result of the communication interface. With one or more embodiments of the present disclosure, when the processing unit performs data processing, data reception and processing result transmission can be performed simultaneously, and the processing result can be output at a high rate.
Description
Technical Field
The present disclosure relates to the field of electronic circuits, and in particular, to a data processing circuit and a wind speed detection device.
Background
In some data processing circuits, an analog signal is sampled and converted to a digital signal, which is processed to produce a processed result and sent out. The analog signal is usually sampled and converted by an analog-to-digital converter, the digital signal obtained by the conversion of the analog-to-digital converter is read by a processor, and the processor processes the digital signal to generate a processing result and then sends the processing result. The processor is required to perform digital signal reading, digital signal processing and processing result transmission, so that the digital signal reading, the digital signal processing and the processing result transmission cannot be performed simultaneously, and further, it is difficult to output the processing result at a high speed.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided a data processing circuit comprising: an analog-to-digital conversion unit; an input interface for receiving data output by the analog-to-digital conversion unit; a first memory unit; a first DMA (Direct Memory Access ) unit for transferring data of the input interface to the first memory unit; a second memory unit; a processing unit for processing the data stored in the first memory unit to generate a processing result and storing it in the second memory unit; a communication interface; a second DMA unit for transferring the processing result from the second memory unit to the communication interface; and a communication unit for transmitting the processing result of the communication interface.
Optionally, the data processing circuit further comprises: a timer, comprising: a first channel for outputting a sampling clock signal; a second channel for outputting a first DMA trigger signal at a rising edge of each sampling clock signal; the analog-to-digital conversion unit performs sampling and conversion based on the sampling clock signal; the first DMA unit performs DMA transfer in response to the first DMA trigger signal.
Optionally, the first DMA unit is configured to generate a calculation trigger signal after transmitting a preset number of data; the processing unit is used for responding to the calculated trigger signal to process the data with the preset number.
Optionally, the data processing circuit further comprises: a counter for counting the number of times of storing the processing result, the counter outputting a second DMA trigger signal when the counter reaches a set value; the second DMA unit responds to the second DMA trigger signal to conduct DMA transmission.
Optionally, the data processing circuit further comprises: zero ohm resistance is connected between the analog ground and the digital ground of the analog-to-digital conversion unit.
Optionally, the data processing circuit further comprises: and the ripple noise processing unit is used for reducing ripple noise of the power supply and is connected between the power supply and the analog-to-digital conversion unit.
Optionally, the data processing circuit further comprises: an isolated power supply unit comprising: the first voltage output end is used for supplying power to the analog domain of the analog-to-digital conversion unit; and the second voltage output end is used for supplying power to the digital domain of the analog-to-digital conversion unit.
According to another aspect of the present disclosure, there is provided a wind speed detection apparatus including: an ultrasonic probe for acquiring an ultrasonic echo analog signal; the analog-to-digital converter is connected with the ultrasonic probe and used for converting the ultrasonic echo analog signal into an ultrasonic echo digital signal; a processor, comprising: the input interface is used for receiving the ultrasonic echo digital signals and is connected with the analog-to-digital converter; a first memory unit; the first DMA unit is used for transmitting the ultrasonic echo digital signal of the input interface to the first memory unit; a second memory unit; the processing unit is used for processing the ultrasonic echo digital signals stored in the first memory unit to generate processing results and storing the processing results into the second memory unit; a communication interface; a second DMA unit for transferring the processing result from the second memory unit to the communication interface; and a communication device for transmitting the processing result of the communication interface.
Optionally, the processor further comprises: a timer, comprising: a first channel for outputting a sampling clock signal; a second channel for outputting a first DMA trigger signal at a rising edge of each sampling clock signal; the analog-to-digital converter performs sampling and conversion based on the sampling clock signal; the first DMA unit responds to the first DMA trigger signal to conduct DMA transmission; the first DMA unit is used for generating a calculation trigger signal after transmitting a preset number of ultrasonic echo digital signals; the processing unit is used for responding to the calculated trigger signal and processing the ultrasonic echo digital signals with preset number.
Optionally, the processor further comprises: a counter for counting the number of times of storing the processing result, the counter outputting a second DMA trigger signal when the counter reaches a set value; the second DMA unit responds to the second DMA trigger signal to conduct DMA transmission.
Optionally, the wind speed detection apparatus further includes: zero ohm resistance connected between analog ground and digital ground of the analog-to-digital converter; an isolated power supply apparatus for reducing supply ripple noise, comprising: a first voltage output for supplying power to an analog domain of the analog-to-digital converter; a second voltage output for supplying power to the digital domain of the analog-to-digital converter; and the impedance matching device is connected between the output end of the analog-to-digital converter and the input interface.
According to one or more technical schemes provided by the embodiment of the utility model, the first DMA unit transmits data from the input interface to the first memory unit, so that the processing unit does not need to participate in data reception; the processing unit processes the data in the first memory unit and stores the processing result in the second memory unit, the second DMA unit transmits the processing result from the second memory unit to the communication interface, and the communication unit transmits the processing result in the communication interface, so that the processing unit does not need to participate in the transmission of the processing result. Thus, when the processing unit performs data processing, data reception and processing result transmission can be performed simultaneously, and the processing result can be output at a high rate.
Drawings
Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:
FIG. 1 shows a schematic block diagram of a data processing circuit provided in accordance with the present disclosure;
FIG. 2 shows a schematic block diagram of another data processing circuit provided in accordance with the present disclosure;
fig. 3 shows a schematic block diagram of a wind speed detection device provided according to the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.
It should be noted that, in the embodiment of the present utility model, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone.
It should be noted that in embodiments of the present utility model, "connected" may be understood as electrically connected, and two electrical components may be connected directly or indirectly between the two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.
Aspects of the present disclosure are described below with reference to the accompanying drawings.
The embodiment of the utility model provides a data processing circuit.
Fig. 1 shows a schematic block diagram of a data processing circuit provided in accordance with the present disclosure, as shown in fig. 1, a data processing circuit 100 includes: an analog-to-digital conversion unit 110; an input interface 121 for receiving data output from the analog-to-digital conversion unit 110; a first memory unit 131; a first DMA unit 141 for transferring data of the input interface 121 to the first memory unit 131; a second memory unit 132; a processing unit 150 for processing the data stored in the first memory unit 131 to generate a processing result and storing it in the second memory unit 132; a communication interface 122; a second DMA unit 142 for transferring the processing result from the second memory unit 132 to the communication interface 122; a communication unit 160 for transmitting the processing result of the communication interface 122. Any one of the data output by the analog-to-digital conversion unit 110 may comprise a plurality of digital bits, one data being a result of one analog-to-digital conversion of the analog input signal, i.e. one digital representation of the analog input signal.
In the data processing circuit 100 of the embodiment of the present utility model, the first DMA unit 141 transfers data from the input interface 121 to the first memory unit 131, so that the processing unit 150 does not need to participate in data reception; the processing unit 150 processes the data in the first memory unit 131 and stores the processing result in the second memory unit 132, and the second DMA unit 142 transfers the processing result from the second memory unit 132 to the communication interface 122, and the communication unit 160 transmits the processing result in the communication interface 122, so that the processing unit 150 does not need to participate in the transmission of the processing result. Thus, when the processing unit 150 performs data processing, data reception and processing result transmission can be performed simultaneously, and the processing result can be output at a high rate.
In an embodiment of the present utility model, the analog-to-digital conversion unit 110 is configured to convert the analog signal of the continuous variable into a discrete digital signal, for example, an electrical signal generated by the analog temperature sensor into a digital signal that can be processed by the processing unit 150. Analog-to-digital conversion comprises two phases, sampling, which is the conversion of a signal that varies continuously in time into a signal that is discrete in time, i.e. the conversion of an analog quantity that varies continuously in time into a series of equally spaced pulses whose amplitude depends on the input analog quantity. The sampled sample pulse level is normalized to a discrete level close to it, a process called transition.
In embodiments of the present utility model, the analog-to-digital conversion unit 110 may include various types of analog-to-digital conversion circuits, and the analog-to-digital conversion unit 110 may be selected from, but not limited to, successive approximation type, sigma-delta type, parallel pipeline type, etc. analog-to-digital conversion circuits. In practical application, the matched analog-to-digital conversion type can be selected according to the indexes such as speed, precision and the like, and the embodiment of the utility model is not limited to the above.
In an embodiment of the present utility model, the input interface 121 is used to receive data. The input interface 121 includes an input register for storing received data. The source address of the first DMA unit 141 is the input register, the destination address of the first DMA unit 141 is the first memory unit 131, and when the DMA transfer is triggered, the first DMA unit 141 transfers data from the source address to the destination address, i.e. from the input interface 121 to the first memory unit 131.
In an embodiment of the present utility model, the communication interface 122 is used to process the result transmission. The communication interface 122 includes a communication register for storing the processing result to be transmitted, and the communication unit 160 acquires the processing result from the communication register and transmits it. In the embodiment of the present utility model, the communication unit 160 may include various types of communication circuits, and the embodiment of the present utility model is not limited to the type of the communication unit 160.
In an embodiment of the present utility model, the processing unit 150 may process the data to generate a processing result by using a well-known method. The processing unit 150 may generate a processing result based on the data received one or more times. The embodiments of the present utility model do not relate to an improvement of an algorithm for processing data to generate a processing result, and thus are not described in detail.
As an embodiment, as shown in fig. 2, the data processing circuit 100 may further include: a timer 170 comprising: a first channel 171 for outputting a sampling clock signal clk_adc; a second channel 172 for outputting a first DMA trigger signal at a rising edge of each sampling clock signal clk_adc. The analog-to-digital conversion unit 110 performs sampling and conversion based on the sampling clock signal. The first DMA unit 141 performs DMA transfer in response to the first DMA trigger signal. In this embodiment, the output of the timer 170 drives the analog-to-digital conversion unit 110 to sample and convert by using a clock signal, so that sampling and conversion at a high sampling rate can be realized, and data accuracy can be improved.
The first DMA unit 141 may generate the calculation trigger signal after transmitting a predetermined number of data. The processing unit 150 may process a preset number of data stored in the first memory unit 131 in response to the calculation trigger signal.
As an embodiment, as shown in fig. 2, the data processing circuit 100 may further include: a counter 180 for counting the number of times of storing the processing result, the counter 180 outputting a second DMA trigger signal when the set value is reached. The second DMA unit 142 performs DMA transfer in response to the second DMA trigger signal, that is, transfers the plurality of processing results in the second memory unit 132 to the communication interface 141 to be transmitted by the communication unit 160. With this embodiment, the processing results can be transmitted after the processing results are output.
The analog-to-digital conversion unit 110 performs analog-to-digital conversion on the analog input signal, and in some cases, the amplitude of the analog input signal is small, so that noise interference is likely to cause low accuracy. An embodiment of reducing noise of an analog input signal is described below in connection with the circuit shown in fig. 2.
As an embodiment, as shown in fig. 2, the data processing circuit 100 may further include: zero ohm resistor 191 is connected between analog ground and digital ground of analog to digital conversion unit 110. The analog-to-digital conversion unit 110 includes an analog domain and a digital domain. With this embodiment, the interference between the analog domain and the digital domain can be reduced, and in particular, the sampling accuracy of the analog input signal having a small amplitude can be improved.
As an embodiment, as shown in fig. 2, the data processing circuit 100 may further include: a ripple noise processing unit 192 for reducing ripple noise of the power supply, the ripple noise processing unit 192 being connected between the power supply and the analog-to-digital conversion unit 110. Thereby, the influence of the power supply ripple noise on the analog-to-digital conversion unit 110 can be reduced.
As an embodiment, as shown in fig. 2, the data processing circuit 100 may further include: an isolated power supply unit 193, comprising: a first voltage output for supplying power to the analog domain of the analog-to-digital conversion unit 110; a second voltage output for supplying power to the digital domain of the analog-to-digital conversion unit 110. Thereby enabling the influence of the digital domain on the analog domain.
In some embodiments, one or more of the above units of data processing circuit 100 may be integrated within one chip, e.g., input interface 121, communication interface 122, first memory unit 131, second memory unit 132, first DMA unit 141, second DMA unit 142, timer 170, and counter 180 are integrated within one chip. The analog-to-digital conversion unit 110 communicates with the chip, and the input interface 121 may be a general purpose input output interface (GPIO).
The embodiment of the utility model also provides wind speed detection equipment.
FIG. 3 shows a schematic block diagram of a wind speed detection apparatus provided in accordance with the present disclosure, as shown in FIG. 3, a wind speed detection apparatus 300 may include: an ultrasound probe 310, an analog-to-digital converter 320, a processor 330, and a communication device 340. In some embodiments, the wind speed detection apparatus 300 may further include a filter 350, a power source, and the like, which are not described in detail in the embodiments of the present utility model.
The ultrasound probe 310 is used to acquire ultrasound echo analog signals. The analog-to-digital converter 320 is connected to the ultrasonic probe 310, and the analog-to-digital converter 320 is used for converting the ultrasonic echo analog signal into an ultrasonic echo digital signal. The processor 330 is connected to the analog-to-digital converter 320, and the processor 330 is configured to process the ultrasonic echo data to generate a wind speed detection result. The communication device 340 is connected to the processor 330 and is used for sending the wind speed detection result.
The wind changes in real time, the clearer the change is resolved, the more the fluidity and the rule can be analyzed, and the data reference is provided for various practical applications, so that the data resolution and the output rate are necessary to be improved. In addition, more advanced algorithms are often used for data processing in order to improve accuracy. The following describes the implementation of the embodiment of the present utility model.
As shown in fig. 3, the processor 330 includes: an input interface 331 connected to the analog-to-digital converter 320 for receiving the ultrasonic echo digital signal; a first memory unit 332 and a second memory unit 333; a first DMA unit 334 for transferring the ultrasonic echo digital signal of the input interface 331 to the first memory unit 332; a processing unit 335 for processing the ultrasonic echo digital signal stored in the first memory unit 332 to generate a processing result and storing the processing result in the second memory unit 333; a communication interface 336; a second DMA unit 337 for transferring the processing result from the second memory unit 333 to the communication interface 336. The communication device 340 may transmit the processing results in the communication interface 336. Thus, when the processing unit 335 performs data processing, data reception and processing result transmission can be performed simultaneously, and the processing result can be output at a high rate. And the computing resource of the processing unit 335 is not used for data receiving and processing result sending, and can be applied to algorithms with higher complexity for wind speed detection.
On the premise of meeting the Laquist sampling theorem, the higher the sampling rate is, the more echo data and details can be truly reflected, the accuracy can be enhanced, and if a traditional GPIO driving mode is adopted, the highest rate can only reach a plurality of MHZ rates, and the requirements are far from being met.
To increase the sampling rate, as an embodiment, a clock signal is used by the timer output. As shown in fig. 3, the processor 330 further includes: a timer 337 comprising: a first channel for outputting a sampling clock signal clk_adc; a second channel for outputting the first DMA trigger signal at a rising edge of each sampling clock signal. Analog-to-digital converter 320 samples and converts based on the sampling clock signal. The first DMA unit 334 performs DMA transfer in response to the first DMA trigger signal. With this embodiment, 10MHZ to 40MHZ sampling can be achieved. The first DMA unit 334 may generate a calculation trigger signal after transmitting a preset number of ultrasonic echo digital signals; the processing unit 335 may process a preset number of ultrasonic echo digital signals in response to calculating the trigger signal.
Illustratively, a Pulse Width Modulated (PWM) signal is generated by a timer 338 that is used as a sampling clock signal for the analog-to-digital converter 320. The sampling frequency of the analog-to-digital converter 320 may be the frequency of the pulse width modulated signal.
Illustratively, the DMA transfer is triggered by a compare/capture event of timer 338. The capture of the rising edge completes the sampling process of one data, generates a first DMA trigger signal, and the first DMA unit 334 performs a DMA transfer in response to the first DMA trigger signal, transferring the ultrasonic echo digital signal from the input interface 331 to the first memory unit 332.
As an embodiment, as shown in fig. 3, the processor 330 may further include: and a counter 339 for counting the number of times of storing the processing result, the counter 339 outputting a second DMA trigger signal when the set value is reached. The second DMA unit 337 performs DMA transfer in response to the second DMA trigger signal, that is, transfers the plurality of processing results from the second memory unit 333 to the communication interface 336. In the data transmission process, the next data acquisition and algorithm identification process is not influenced, and the working efficiency and sampling rate of the wind speed detection equipment can be improved.
In general, the amplitude of the ultrasonic echo analog signal is very small, and the small signal is accurately acquired, so that the wind speed identification precision can be improved.
In some embodiments, as shown in fig. 3, an impedance matching device 350 (e.g., a matching resistor) is connected between the output end of the analog-to-digital converter 320 and the input interface 331, so that the impedance of the transmission line is matched with the impedance of the analog-to-digital converter 320, and the signal is prevented from being reflected and oscillated, thereby improving the accuracy of data sampling.
In some embodiments, as shown in fig. 3, since the dc voltage ripple output by the switching power supply is large, if the analog-to-digital converter 320 is directly driven by the voltage, noise is superimposed on the ultrasonic echo signal, so that the digital power supply and the analog power supply are respectively provided to the analog-to-digital converter 320 by the low ripple noise isolation power supply 360, so that the digital signal noise (mainly, the data line and the driving clock data line) is avoided from being superimposed on the ultrasonic echo analog signal, and the sampling precision can be increased.
In some embodiments, as shown in fig. 3, the analog ground and digital ground of analog-to-digital converter 320 are connected in series through zero ohm resistor 370, which can reduce noise.
The wind speed detection apparatus 300 shown in fig. 3, the timer provides a sampling clock signal of the analog-to-digital converter, enabling high-rate sampling; the first DMA unit transfers the data from the input interface to the first memory unit, so that the processing unit does not need to participate in data reception; the processing unit processes the data in the first memory unit and stores the processing result in the second memory unit, the second DMA unit transmits the processing result from the second memory unit to the communication interface, and the communication unit transmits the processing result in the communication interface, so that the processing unit does not need to participate in the transmission of the processing result. Thus, when the processing unit performs data processing, data reception and processing result transmission can be performed simultaneously, and the processing result can be output at a high rate. And the impedance matching device prevents signals from being reflected and oscillated, the isolation power supply with low ripple noise prevents digital signal noise from being overlapped on an ultrasonic echo analog signal, noise can be reduced by serial connection of zero ohm resistors of analog ground and digital ground of the analog-to-digital converter, and the precision of wind speed detection can be improved.
The following describes an exemplary operation flow of the wind speed detection apparatus 300.
When the wind speed detection device 300 is powered on and started, the ultrasonic probe is excited, data acquisition is performed after a preset time delay is performed after excitation is completed, echo zero crossing point calculation is performed after acquisition is completed, and then a calculation result is transmitted. The timer outputs a sampling clock signal, the analog-to-digital converter converts an ultrasonic echo analog signal into an ultrasonic echo digital signal based on the sampling clock signal, the first DMA unit transmits the ultrasonic echo digital signal to the first memory unit from the input interface when the analog-to-digital converter outputs the ultrasonic echo digital signal, and after a preset number of ultrasonic echo digital signals are transmitted, a calculation trigger signal is generated and used for notifying the processing unit of processing the preset number of ultrasonic echo digital signals. The processing unit processes the preset number of ultrasonic echo digital signals in the first memory unit to obtain a processing result, the processing result is sent to the second memory unit, the counter counts the storage times, after the preset number of the ultrasonic echo digital signals are stored, the second DMA unit is triggered, and the result of the preset data is transmitted to the communication interface and sent by the communication device.
Although the present utility model has been described in terms of the preferred embodiments, it should be understood that the present utility model is not limited to the specific embodiments, but is capable of numerous modifications and equivalents, and alternative embodiments and modifications of the embodiments described above, without departing from the spirit and scope of the present utility model.
Claims (10)
1. A data processing circuit, comprising:
an analog-to-digital conversion unit;
an input interface for receiving data output by the analog-to-digital conversion unit;
a first memory unit;
a first DMA unit for transferring data of the input interface to the first memory unit;
a second memory unit;
a processing unit for processing the data stored in the first memory unit to generate a processing result and storing the processing result in the second memory unit;
a communication interface;
a second DMA unit for transferring the processing result from the second memory unit to the communication interface;
and the communication unit is used for sending the processing result of the communication interface.
2. The data processing circuit of claim 1, further comprising:
a timer, comprising:
a first channel for outputting a sampling clock signal;
a second channel for outputting a first DMA trigger signal at a rising edge of each sampling clock signal;
the analog-to-digital conversion unit performs sampling and conversion based on the sampling clock signal; the first DMA unit responds to the first DMA trigger signal to conduct DMA transmission.
3. The data processing circuit of claim 2, wherein the first DMA unit is configured to generate a computation trigger signal after transmitting a predetermined number of data; the processing unit is used for responding to the calculation trigger signal to process the preset number of data.
4. The data processing circuit of claim 1, further comprising:
a counter for counting the number of times of storing the processing result, the counter outputting a second DMA trigger signal when the counter reaches a set value;
and the second DMA unit responds to the second DMA trigger signal to conduct DMA transmission.
5. The data processing circuit of claim 1, further comprising:
and the ripple noise processing unit is used for reducing ripple noise of the power supply and is connected between the power supply and the analog-to-digital conversion unit.
6. The data processing circuit of claim 1, further comprising:
zero ohm resistance connected between analog ground and digital ground of the analog-to-digital conversion unit;
an isolated power supply unit comprising:
the first voltage output end is used for supplying power to the analog domain of the analog-to-digital conversion unit;
and the second voltage output end is used for supplying power to the digital domain of the analog-to-digital conversion unit.
7. A wind speed detection apparatus, comprising:
an ultrasonic probe for acquiring an ultrasonic echo analog signal;
the analog-to-digital converter is connected with the ultrasonic probe and used for converting the ultrasonic echo analog signal into an ultrasonic echo digital signal;
a processor, comprising: the input interface is used for receiving the ultrasonic echo digital signals and is connected with the analog-to-digital converter; a first memory unit; a first DMA unit for transmitting the ultrasound echo digital signal of the input interface to the first memory unit; a second memory unit; the processing unit is used for processing the ultrasonic echo digital signals stored in the first memory unit to generate processing results and storing the processing results into the second memory unit; a communication interface; a second DMA unit for transferring the processing result from the second memory unit to the communication interface;
and communication means for transmitting the processing result of the communication interface.
8. The wind speed detection apparatus of claim 7, wherein the processor further comprises:
a timer, comprising:
a first channel for outputting a sampling clock signal;
a second channel for outputting a first DMA trigger signal at a rising edge of each sampling clock signal;
wherein the analog-to-digital converter performs sampling and conversion based on the sampling clock signal; the first DMA unit responds to the first DMA trigger signal to conduct DMA transmission;
the first DMA unit is used for generating a calculation trigger signal after transmitting a preset number of ultrasonic echo digital signals; the processing unit is used for responding to the calculation trigger signal to process the ultrasonic echo digital signals with the preset number.
9. The wind speed detection apparatus of claim 7, wherein the processor further comprises:
a counter for counting the number of times of storing the processing result, the counter outputting a second DMA trigger signal when the counter reaches a set value;
and the second DMA unit responds to the second DMA trigger signal to conduct DMA transmission.
10. The wind speed detection apparatus according to claim 7, further comprising:
zero ohm resistance connected between the analog ground and the digital ground of the analog-to-digital converter;
an isolated power supply apparatus for reducing supply ripple noise, comprising: a first voltage output for supplying power to an analog domain of the analog-to-digital converter; a second voltage output for supplying power to the digital domain of the analog-to-digital converter;
and the impedance matching device is connected between the output end of the analog-to-digital converter and the input interface.
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| CN202321074225.2U CN219695748U (en) | 2023-05-06 | 2023-05-06 | Data processing circuit and wind speed detection device |
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| CN202321074225.2U CN219695748U (en) | 2023-05-06 | 2023-05-06 | Data processing circuit and wind speed detection device |
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