CN219677263U - Undoped tunneling transistor with ferroelectric film and metal embedded layer - Google Patents
Undoped tunneling transistor with ferroelectric film and metal embedded layer Download PDFInfo
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- CN219677263U CN219677263U CN202321308017.4U CN202321308017U CN219677263U CN 219677263 U CN219677263 U CN 219677263U CN 202321308017 U CN202321308017 U CN 202321308017U CN 219677263 U CN219677263 U CN 219677263U
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- 230000005641 tunneling Effects 0.000 title claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 61
- 239000002184 metal Substances 0.000 title claims abstract description 61
- 239000010408 film Substances 0.000 claims description 36
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- FIWXUAGPOBLSIJ-UHFFFAOYSA-N [Hf].[Zr].[O] Chemical compound [Hf].[Zr].[O] FIWXUAGPOBLSIJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 8
- 239000013590 bulk material Substances 0.000 abstract description 6
- 230000003321 amplification Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model relates to the technical field of semiconductors, in particular to an undoped tunneling transistor with a ferroelectric film and a metal embedded layer, which comprises the following components:the device comprises a source electrode, a drain electrode, a grid dielectric layer, a source region, a drain region, a channel region, a metal embedded layer and a ferroelectric film layer; inserting Pt metal embedded layer into the gate dielectric layer to form P in the underlying bulk material + -pocket; adopting a bimetal gate structure to adjust the electric field intensity at the tunneling junction; ferroelectric film layer is added under tunneling gate to raise electron tunneling rate, reduce tunneling barrier and enhance control capability of gate voltage. The utility model effectively solves the problems of lower on-state current, smaller switching current and higher subthreshold swing of the traditional undoped TFET due to relatively weaker gate electric field amplification, and achieves the purposes of improving the on-state current and the switching current ratio of the device and reducing the subthreshold swing of the device.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to an undoped tunneling transistor with a ferroelectric film and a metal embedded layer.
Background
As the integration of semiconductor devices increases and the device size decreases, MOSFETs are approaching physical limits. To continue moore's law, new devices that can replace MOSFETs are being sought. Undoped TFETs are of increasing interest to researchers because of the ability to avoid random doping fluctuations, greatly reduce complex thermal budget, and the ease of forming abrupt junctions in the source/channel and drain/channel regions without doping. However, a gap exists between the source and the gate of the conventional undoped TFET, which increases the tunneling barrier at the source/channel junction, thereby blocking tunneling of carriers, and eventually leading to degradation of the device dc and rf performance.
To address this problem, tirkey et al propose a new type of undoped TFET that directly utilizes a P-type heavily doped silicon substrate as the source region, unlike conventional undoped TFETs based on the charge plasma principle. However, this method is basically applicable to silicon-based devices only and is not applicable to devices in which the bulk material is a composite semiconductor material. To achieve steeper tunneling junctions in undoped TFETs, yadav et al propose another approach to insert a Hf metal embedded layer with a work function of 3.9eV into the dielectric layer between the TFET source and the channel. The purpose of this is to form an N in the bulk material under the metal embedding layer + Pocket, thereby helping to improve tunneling of carriers. With this structure, the tunnel junction is deviated from the gate due to the Hf metal embedded layer, so that the influence of the variation of the gate voltage and the gate metal work function on the tunnel junction is small, and the performance of the device cannot be significantly improved.
Disclosure of Invention
The utility model provides an undoped tunneling transistor with a ferroelectric film and a metal embedded layer, which is used for solving the problems of lower on-state current, smaller switching current and higher subthreshold swing caused by relatively weaker gate electric field amplification of the traditional undoped TFET, and achieving the purposes of improving the on-state current and the switching current ratio of a device and reducing the subthreshold swing of the device.
The utility model provides an undoped tunneling transistor with a ferroelectric film and a metal embedded layer, comprising: the device comprises a source electrode, a drain electrode, a grid dielectric layer, a source region, a drain region, a channel region, a metal embedded layer and a ferroelectric layer;
the source electrode is in a shape of a ' [ -and is arranged on one side of the transistor, the drain electrode is arranged on one side of the transistor opposite to the source electrode, the drain electrode is in a shape of a ' J ', the grid electrode is divided into an upper group and a lower group and is arranged on the other two sides of the transistor and is not contacted with the source electrode and the drain electrode, the grid electrode comprises a tunneling grid and a control grid, the tunneling grid is contacted with the control grid, a ferroelectric film layer is arranged above the tunneling grid, and the ferroelectric film layer has the same length as the tunneling grid;
the gate dielectric layer is divided into an upper group and a lower group, the gate dielectric layer covers the upper part and the side of the grid electrode and the ferroelectric film layer, the gate dielectric layer is contacted with the source electrode and the drain electrode, the gate dielectric layer comprises a first dielectric layer and a second dielectric layer, one side of the first dielectric layer is contacted with the source electrode, the other side of the first dielectric layer extends to the upper part of the ferroelectric film layer and the control grid, one side of the second dielectric layer is contacted with the drain electrode, the other side of the second dielectric layer extends to the upper part of the control grid and is contacted with the first dielectric layer, the upper surface and the lower surface of the first dielectric layer are flush, and the metal embedded layer is arranged on the first dielectric layer;
the source region, the channel region and the drain region are respectively arranged between two groups of gate dielectric layers from left to right, the upper surface and the lower surface of the source region are contacted with the first dielectric layer, the upper surface and the lower surface of the drain region are contacted with the second dielectric layer, and the upper surface and the lower surface of the channel region are contacted with the first dielectric layer and the second dielectric layer.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the tunneling gate material is metal with a work function of 3.9eV, and the control gate material is metal with a work function of 4.85 eV.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the source electrode material is metal platinum with a work function of 5.93eV, and the drain electrode material is hafnium with a work function of 3.9 eV.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the material of the metal embedded layer is platinum.
The undoped tunneling transistor with the ferroelectric film and the metal embedded layer provided by the utility model has the source region, the drain region and the channel region which are made of InGaAs (In) 0.53 Ga 0.47 As)。
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the ferroelectric film layer is made of hafnium zirconium oxygen.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the first dielectric layer is made of hafnium oxide.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the second dielectric layer is made of silicon dioxide.
The utility model adopts a double source drain electrode structure, thereby leading the hole distribution of the source region to be more uniform; inserting a metal embedded layer in the dielectric layer between the source/channel to form a P in the underlying bulk material + -pocket; adopting a bimetal gate structure to adjust the electric field intensity at the tunneling junction; ferroelectric film layer is added under tunneling gate to raise electron tunneling rate, reduce tunneling barrier and enhance control capability of gate voltage. The utility model effectively solves the problems of lower on-state current and lower switching current caused by relatively weak gate electric field amplification of the traditional undoped TFETThe problems of small subthreshold swing are solved, and the purposes of improving on-state current and switching current ratio of the device and reducing the subthreshold swing of the device are achieved.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
In order to more clearly illustrate the utility model or the technical solutions of the prior art, the following description will briefly explain the embodiments or the drawings needed in the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the utility model and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional structure of an undoped tunneling transistor device having a ferroelectric thin film and a metal embedded layer according to an embodiment of the present utility model;
fig. 2 is a schematic cross-sectional structure of a conventional undoped tunneling transistor device;
reference numerals:
1. a source electrode; 2. a drain electrode; 3. a gate; 31. a tunneling gate; 32. a control gate; 4. a gate dielectric layer; 41. a first dielectric layer; 42. a second dielectric layer; 5. a metal embedded layer; 6. a source region; 7. a drain region; 8. a channel region; 9. a ferroelectric thin film layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, the technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the embodiments of the present utility model, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely for convenience in describing the embodiments of the present utility model and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present utility model. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In describing embodiments of the present utility model, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present utility model will be understood in detail by those of ordinary skill in the art.
In embodiments of the utility model, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present utility model. In this specification, schematic representations of the above terms are not directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The technical solution of the present utility model is described below with reference to the embodiment shown in fig. 1:
an undoped tunneling transistor having a ferroelectric thin film and a metal embedded layer 5, comprising: a source electrode 1, a drain electrode 2, a grid electrode 3, a grid dielectric layer 4, a source region 6, a drain region 7, a channel region 8, a metal embedded layer 5 and a ferroelectric film layer 9;
the source electrode 1 is in a shape of a '[ -and is arranged on one side of the transistor, the drain electrode 2 is arranged on one side of the transistor opposite to the source electrode, the drain electrode 2 is in a shape of a' ], the grid electrode 3 is divided into an upper group and a lower group, the two groups are arranged on the other two sides of the transistor and are not contacted with the source electrode 1 and the drain electrode 2, the grid electrode 3 comprises a tunneling grid 31 and a control grid 32, the tunneling grid 31 is contacted with the control grid 32, a ferroelectric film layer 9 is arranged above the tunneling grid 31, and the ferroelectric film layer 9 and the tunneling grid 31 have the same length;
the gate dielectric layer 4 is divided into an upper group and a lower group, the gate dielectric layer 4 covers the upper part and the side parts of the gate electrode 3 and the ferroelectric film layer 9, the gate dielectric layer 4 is contacted with the source electrode 1 and the drain electrode 2, the gate dielectric layer 4 comprises a first dielectric layer 41 and a second dielectric layer 42, one side of the first dielectric layer 41 is contacted with the source electrode 1, the other side of the first dielectric layer 41 extends to the upper part of the ferroelectric film layer 9 and the control gate 32, one side of the second dielectric layer 42 is contacted with the drain electrode 2, the other side extends to the upper part of the control gate 32 and is contacted with the first dielectric layer 41, the upper surface and the lower surface of the first dielectric layer 41 are flush with the upper surface and the lower surface of the second dielectric layer 42, and the metal embedded layer 5 is arranged on the first dielectric layer 41;
the source region 6, the channel region 8 and the drain region 7 are respectively arranged between the two groups of gate dielectric layers 4 from left to right, the upper surface and the lower surface of the source region 6 are contacted with the first dielectric layer 41, the upper surface and the lower surface of the drain region 7 are contacted with the second dielectric layer 42, and the upper surface and the lower surface of the channel region 8 are contacted with the first dielectric layer 41 and the second dielectric layer 42.
The utility model adopts a double source drain electrode structure, thereby leading the hole distribution of the source region 6 to be more uniform; inserting a metal embedded layer 5 in the dielectric layer between the source/channel to form a P in the underlying bulk material + -pocket; adopting a bimetal gate structure to adjust the electric field intensity at the tunneling junction; a ferroelectric film layer 9 is added under the tunneling gate 31 to improve the electron tunneling rate in the device, reduce the tunneling barrier and enhance the control capability of the gate voltage. The utility model effectively solves the problems of lower on-state current, smaller switching current and higher subthreshold swing of the traditional undoped TFET due to relatively weaker gate electric field amplification, and achieves the purposes of improving the on-state current and the switching current ratio of the device and reducing the subthreshold swing of the device.
According to the undoped tunneling transistor with the ferroelectric film and the metal embedded layer, the tunneling gate 31 material is metal with a work function of 3.9eV, and the control gate 32 material is metal with a work function of 4.85 eV; the source electrode 1 material is metal platinum Pt with a work function of 5.93eV, and the drain electrode 2 material is hafnium Hf with a work function of 3.9 eV; the material of the metal embedded layer 5 is platinum Pt; the source region 6, the drain region 7 and the channel region 8 are made of InGaAs (In 0.53 Ga 0.47 As); the ferroelectric thin film layer 9 is made of hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ) The method comprises the steps of carrying out a first treatment on the surface of the The first dielectric layer 41 is made of hafnium oxide HfO 2 The method comprises the steps of carrying out a first treatment on the surface of the The second dielectric layer 42 is made of silicon dioxide SiO 2 。
The existence of the Pt metal embedded layer 5 enables the tunneling junction to move towards the channel direction, so that the influence of the voltage of the grid electrode 3 on the tunneling junction can be enhanced, and electron tunneling is facilitated. In addition, since the inserted Pt metal embedded layer 5 can reduce parasitic capacitance between the gate electrode 3 and the source electrode 1, radio frequency characteristics of the device can be improved. The presence of the Pt metal embedded layer 5 makes the device more sensitive to changes in the work function of the tunnel gate 31, and thus can further improve the dc and rf characteristics of the TFET. Furthermore, the use of control gate 32 in a bi-metal gate is intended to suppress off-state current; and the heterogeneous gate dielectric structure is adopted to enhance the transverse electric field at the tunneling junction, so that the on-state current is improved.
The preparation process comprises the following steps:
the undoped tunneling transistor with ferroelectric film and metal embedded layer 5 is prepared through growing undoped In on InP substrate by MBE technique 0.53 Ga 0.47 As epitaxial layers serve As bulk materials for the device, followed by deposition of HfO using ALD techniques 2 A dielectric layer;
s1: growing undoped In on an InP substrate using MBE technique 0.53 Ga 0.47 As epitaxial layers serve As bulk materials for the device, followed by deposition of HfO using ALD techniques 2 A dielectric layer;
s2: using ICP etching technology to perform HfO 2 Etching the dielectric layer to etch the positions of the Pt metal film and the ferroelectric layer, and sequentially depositing the Pt metal film and the ferroelectric film at the etched positions by an ALD (atomic layer deposition) technology; wherein the ferroelectric material is a hafnium zirconium oxide film (wherein Hf 0.5 Zr 0.5 O 2 HfO in 2 And ZrO(s) 2 According to 1:1 by the stoichiometric ratio of the raw materials;
s3: deposition of HfO on metal and ferroelectric films 2 Subsequently by reacting to HfO 2 Is to the etching of SiO 2 Is deposited to form HfO 2 /SiO 2 A heterogeneous dielectric layer;
s4: etching the positions of the top source electrode 1, the top tunneling gate 31 and the top control gate 32 and the top drain electrode 2 by utilizing an ICP etching technology, and respectively depositing Pt, mo (nitrogen with different dosages in Mo of 4 and 5) and Hf metal by utilizing an ALD technology to realize a top metal electrode of the device;
s5: bonding the structure in the step (4) with the Si substrate by using a BCB polymer through an adhesive bonding technology, and etching the InP substrate after bonding;
s6: step S1 is repeated (considering only HfO 2 S4), the same symmetrical structure as the top of the bulk material in step S4 can be obtained. Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the present utility model has been described in detail with reference to the foregoing embodiments, it is to be understood thatThe person of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims (8)
1. An undoped tunneling transistor having a ferroelectric thin film and a metal embedded layer, comprising: the device comprises a source electrode, a drain electrode, a grid dielectric layer, a source region, a drain region, a channel region, a metal embedded layer and a ferroelectric film layer;
the source electrode is in a shape of a ' [ -and is arranged on one side of the transistor, the drain electrode is arranged on one side of the transistor opposite to the source electrode, the drain electrode is in a shape of a ' ] ', the grid electrode is divided into an upper group and a lower group and is arranged on the other two sides of the transistor and is not contacted with the source electrode and the drain electrode, the grid electrode comprises a tunneling grid and a control grid, the tunneling grid is contacted with the control grid, a ferroelectric film layer is arranged above the tunneling grid, and the ferroelectric film layer has the same length as the tunneling grid;
the gate dielectric layer is divided into an upper group and a lower group, the gate dielectric layer covers the upper part and the side of the grid electrode and the ferroelectric film layer, the gate dielectric layer is contacted with the source electrode and the drain electrode, the gate dielectric layer comprises a first dielectric layer and a second dielectric layer, one side of the first dielectric layer is contacted with the source electrode, the other side of the first dielectric layer extends to the upper part of the ferroelectric film layer and the control grid, one side of the second dielectric layer is contacted with the drain electrode, the other side of the second dielectric layer extends to the upper part of the control grid and is contacted with the first dielectric layer, the upper surface and the lower surface of the first dielectric layer are flush, and the metal embedded layer is arranged on the first dielectric layer;
the source region, the channel region and the drain region are respectively arranged between two groups of gate dielectric layers from left to right, the upper surface and the lower surface of the source region are contacted with the first dielectric layer, the upper surface and the lower surface of the drain region are contacted with the second dielectric layer, and the upper surface and the lower surface of the channel region are contacted with the first dielectric layer and the second dielectric layer.
2. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the tunneling gate material is a metal with a work function of 3.9eV, and the control gate material is a metal with a work function of 4.85 eV.
3. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the source electrode material is metal platinum with a work function of 5.93eV, and the drain electrode material is hafnium with a work function of 3.9 eV.
4. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the metal embedded layer is made of platinum metal.
5. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the source region, the drain region and the channel region are made of InGaAs (In 0.53 Ga 0.47 As)。
6. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the ferroelectric film layer material is hafnium zirconium oxygen.
7. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the first dielectric layer material is hafnium oxide.
8. The undoped tunneling transistor with ferroelectric thin film and metal embedded layer according to claim 1, wherein: the second dielectric layer is made of silicon dioxide.
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