CN219658715U - Gallium nitride high electron mobility transistor for improving MTBF - Google Patents
Gallium nitride high electron mobility transistor for improving MTBF Download PDFInfo
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- CN219658715U CN219658715U CN202321232833.1U CN202321232833U CN219658715U CN 219658715 U CN219658715 U CN 219658715U CN 202321232833 U CN202321232833 U CN 202321232833U CN 219658715 U CN219658715 U CN 219658715U
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 52
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 195
- 239000002184 metal Substances 0.000 claims abstract description 195
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 65
- 230000006911 nucleation Effects 0.000 claims description 5
- 238000010899 nucleation Methods 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000003780 insertion Methods 0.000 claims description 4
- 230000037431 insertion Effects 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000008859 change Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The utility model provides a gallium nitride high electron mobility transistor for improving MTBF, which comprises a gallium nitride substrate, a source electrode region, a gate electrode region and a drain electrode region, wherein a source electrode interconnection metal layer is provided with a top layer source electrode metal, a drain electrode interconnection metal layer is provided with a top layer drain electrode metal, and the metal width sizes of the top layer source electrode metal and the top layer drain electrode metal in the direction from the head to the root are gradually increased. The width from the head to the root of the top drain metal and the source metal is gradually widened, compared with the width of the root of the equal-width metal wire, the width of the gradually-changed metal can reach the same MTBF as the width of the equal-width metal, and the width of the gradually-changed metal can be designed to be wider than the width of the equal-width metal, so that the larger MTBF is achieved; meanwhile, the parasitic capacitance of the device can be reduced through the design of gradually changing metal width.
Description
Technical Field
The utility model relates to the technical field of semiconductor devices, in particular to a semiconductor device of a GaN high electron mobility transistor (high electron mobility transistor; HEMT) for improving the mean time between failure (Mean Time Between Failure; MTBF) of the device, namely improving the reliability of the device.
Background
As a representative of third generation semiconductor materials subsequent to the first generation semiconductor silicon (Si) and the second generation semiconductor gallium arsenide (GaAs), gallium nitride (GaN) has many excellent material characteristics such as a wide forbidden band, high temperature resistance, high electron concentration, high electron mobility, high thermal conductivity, and the like. Therefore, gaN-based High Electron Mobility Transistors (HEMTs) possess excellent performance in the fields of microwave communication and power electronic conversion, and are particularly suitable for manufacturing high-power electronic devices.
The power device is an important component of a power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power device have a decisive influence on various technical indexes and performances of the whole power electronic system. There are many factors affecting the reliability of the device, and in addition to external environmental factors such as temperature, humidity, pressure, there are factors related to the design of the device itself such as metal electromigration. The effect of metal electromigration on the device MTBF follows the equation Arrhenii Wu Sigong: 1/mtbf=a·j 2 ·e -Ea/kT Wherein A is a factor before finger, J is current density, E a For reaction activation energy, k is boltzmann constant, and T is thermodynamic temperature, it can be seen from the equation that decreasing the current density of a metal wire increases the MTBF of the device, and it is therefore common practice to increase the width or thickness of the metal wire and thus its cross-sectional area. However, the above two measures also introduce additional problems such as an increase in manufacturing cost and an increase in parasitic capacitance, while the metal electrodeThe width is also limited by the design rules of the fab and cannot be further widened.
Fig. 2 shows a top metal view of a rectangular equal-width source and drain in the prior art, where reference numeral 31 is a drain metal Bus,32 is a drain metal, 33 is a source metal, 34 is a source metal Bus, in the prior art, the widths from the head to the root of the drain metal and the source metal are equal, and because the metal wires are converged from the head to the root, the current density of the root is the largest under the condition that the widths of the head and the root are the same, and electromigration is the easiest, and the section of metal width from the head to the root is redundant although wide, and cannot promote the electromigration phenomenon of the weak part.
Disclosure of Invention
The utility model provides a gallium nitride high electron mobility transistor with a gradual change metal width design. The Mean Time Between Failure (MTBF) of the device can be increased.
In order to solve the technical problems, the utility model adopts the following technical scheme:
a gallium nitride high electron mobility transistor for increasing MTBF, comprising:
a gallium nitride substrate;
a source region formed in the gallium nitride substrate and including a source ohmic metal in contact with a portion of the gallium nitride substrate, the source ohmic metal having at least one source interconnection metal layer formed thereon;
a gate region formed in the gallium nitride substrate for separating the source and drain regions; and
a drain region formed in the gallium nitride substrate and including a drain ohmic metal in contact with a portion of the gallium nitride substrate, the drain ohmic metal having at least one drain interconnect metal layer formed thereon; wherein the number of layers of the source interconnection metal layer is the same as the number of layers of the drain interconnection metal layer;
the source interconnection metal layer has a top-level source metal, the drain interconnection metal layer has a top-level drain metal, and metal width dimensions in a head-to-root direction of the top-level source metal and the top-level drain metal become gradually larger.
Preferably, the top-level source metal and the top-level drain metal are in a trapezoid structure, the narrowest end of the trapezoid structure is a head, and the widest end of the trapezoid structure is a root.
Preferably, the top source metal and the top drain metal are multi-step structures, the narrowest end of the multi-step structures is the head, and the widest end of the multi-step structures is the root.
Further, the source interconnection metal layer is a single layer including a first source metal (41) formed on the source ohmic metal, and the drain interconnection metal layer is a single layer including a first drain metal (51) formed on the drain ohmic metal, the width dimensions of the first source metal, the first drain metal being gradually increased in a head-to-root direction of the first source metal, the first drain metal.
Preferably, the first source metal is further stacked with a second source metal, the first drain metal is further stacked with a second drain metal, and the width dimensions of the second source metal and the second drain metal become larger gradually in the direction from the head to the root of the second source metal and the second drain metal.
According to the technical scheme, the widths of the top-layer source metal and the top-layer drain metal from the head to the root are gradually widened, and compared with the equal-width metal wires, the width of the gradually-changed metal can reach the same MTBF as the equal-width metal width under the condition that the widths of the roots are equal, and the width of the gradually-changed metal can be designed to be wider than the equal-width metal width, so that the larger MTBF is achieved; meanwhile, the design of gradual change metal width can reduce parasitic capacitance of the device and has wider metal spacing between the source electrode and the drain electrode.
Drawings
Fig. 1 is a longitudinal cross-sectional view of one embodiment of a gallium nitride high electron mobility transistor of the present utility model;
FIG. 2 is a schematic plan view of a top metal structure of a rectangular equal-width source and drain in the prior art;
FIG. 3 is a schematic plan view of a top metal structure according to an embodiment of the present utility model;
FIG. 4 is a schematic plan view of a top metal structure according to another embodiment of the present utility model;
fig. 5 is a schematic diagram showing the comparison of the equal width top metal of the source and drain electrodes and the graded top metal of the source and drain electrodes.
Detailed Description
A preferred embodiment of the present utility model will be described in detail with reference to the accompanying drawings.
The present utility model provides a gallium nitride high electron mobility transistor comprising a gallium nitride substrate 10, and a source region 43, a drain region 53 and a gate region 80 formed in or on the gallium nitride substrate, wherein the gate region 80 is disposed between the source region 43 and the drain region 53, the drain region 53 is separated from the source region 43, and a dielectric layer 20 is filled between the source region, the drain region and the gate region.
The gallium nitride substrate 10 includes a substrate and a multi-layered functional structure formed on the substrate, which is disposed as needed, and may include, but is not limited to, a substrate, a nucleation layer, a buffer layer, a first GaN layer, a second GaN layer, and an AlGaN barrier layer, which are sequentially stacked. It may further comprise a nucleation layer, a buffer layer, a first insertion layer, a first GaN layer, a second insertion layer, a second GaN layer and an AlGaN barrier layer stacked in this order, wherein the nucleation layer is connected to a substrate, wherein the substrate may be sapphire, silicon or gallium nitride.
In the present utility model, the source region 43 includes a source ohmic metal 42 contacting a portion of the gallium nitride substrate 10, and at least one source interconnection metal layer is formed on the source ohmic metal 42. The drain region 53 includes a drain ohmic metal 52 in contact with a portion of the gallium nitride substrate 10, having at least one drain interconnect metal layer formed thereon. The source interconnection metal layer and the drain interconnection metal layer may be one layer of metal, two layers of metal or three layers of metal, and the number of layers of the source interconnection metal layer and the drain interconnection metal layer is the same. Fig. 1 and 3 illustrate specific embodiments in which the interconnect metal layer employs two layers of metal.
As shown in fig. 1, the source region 43 includes a source ohmic metal 42 contacting a portion of the gallium nitride substrate 10, a first source metal 41 is formed on the source ohmic metal 42, a second source metal 40 is further formed on the first source metal 41 in a stacked manner, and the first source metal 41 and the second source metal 40 form a source interconnection metal layer having a two-layer structure, wherein the second source metal 40 is a top source metal. The drain region 53 includes a drain ohmic metal 52 in contact with a portion of the gallium nitride substrate 10, on which a first drain metal 51 is formed, and on which a second drain metal 50 is further formed on top of the first drain metal 51, the first drain metal 51 and the second drain metal 50 forming a drain interconnection metal layer of a two-layer structure, wherein the second drain metal 50 is a top drain metal.
In the present utility model, the second source metal 40 and the second drain metal 50 are designed with gradually changed metal widths, and referring to fig. 3, specifically, the metal width dimension in the direction from the head to the root of the top metal plane gradually increases, and the gradually changed metal width can reach the same MTBF as the equal width metal width when the root width is equal with respect to the equal width metal wire. Because the design of gradual change metal width can guarantee that metal current density is equal (metal width linear broadening can be enough) of metal finger structure's head to root, then head to root's MTBF is equal promptly, so can reach the same MTBF as the equal width metal design.
The design of the gradual change width of the top metal of the drain electrode and the source electrode can also reduce the parasitic capacitance of the device and has wider metal spacing of the source electrode and the drain electrode. The specific parasitic capacitance refers to the capacitance C of a parallel plate capacitor model formed by drain metal, source metal and a dielectric layer 20 between the drain metal and the source metal DS ＝ε r ε 0 S/d, where ε r Represents the relative dielectric constant, epsilon, of the insulating medium 0 Representing vacuum dielectric constant, S representing equivalent facing area of two polar plates, d representing equivalent distance between two polar plates, the parallel plate capacitor model is equivalent to parallel structure of parallel plate capacitor with gradually widened polar plate distance, when adopting gradual metal width design, the parallel plate capacitor with distance except for root position is wider than equal width metal design, thus gradually changing according to capacitance formulaThe parasitic capacitance of the metal-width transistor is lower than for a relatively wide metal design.
In one embodiment, as shown in fig. 3, the second source metal 40 and the second drain metal 50 are both trapezoidal structures, the narrowest end of the trapezoid is a head portion a, and the widest end of the trapezoid is a root portion B. The metal width dimension f (x) of the trapezoid structure satisfies the following formula:
f(x)＝kx
where x is the distance from the metal head and k is a constant determined by the transistor design, i.e., the metal width widens linearly with the change in x.
In another embodiment, as shown in fig. 4, the second source metal 40 and the second drain metal 50 are both multi-step structures, the narrowest end of the multi-step structures is the head a, and the widest end of the multi-step structures is the root B. The multi-step structure can realize the effect of gradually changing the metal width, and the number of steps is not limited.
The gate region 80 includes a gate stack structure in contact with a portion of the gallium nitride substrate, the gate stack structure being any one of a depletion mode GaN-HEMT, a recessed gate enhancement mode GaN-HEMT, an ion implantation enhancement mode GaN-HEMT, and a p-GaN enhancement mode GaN-HEMT.
Moreover, since the distance between the metal lines in the wafer factory has a minimum value, the graded metal width design is relatively equal to the wide metal width, and the root metal width can be designed to be wider. As shown in fig. 5, when the minimum distance between metals is 5um, the width X of the equal width metal can only be 9um, when the width y1+y2=18um of the gradual change metal of the present utility model is the root width, Y2 is the head width, Y1 > Y2, and then 9um < Y1 < 18um, so the root metal width of the gradual change metal is larger than the equal width metal width dimension of the same condition, thereby achieving a larger average fault free working time MTBF.
The above-described embodiments are merely illustrative of the preferred embodiments of the present utility model and are not intended to limit the scope of the present utility model, and various modifications and improvements made by those skilled in the art to the technical solution of the present utility model should fall within the scope of protection defined by the claims of the present utility model without departing from the spirit of the present utility model.
Claims (10)
1. A gallium nitride high electron mobility transistor for increasing MTBF, comprising:
a gallium nitride substrate (10);
a source region (43) formed in the gallium nitride substrate (10) and including a source ohmic metal (42) in contact with a portion of the gallium nitride substrate, the source ohmic metal having at least one source interconnect metal layer formed thereon;
a gate region (80) formed in the gallium nitride substrate for separating the source and drain regions; and
a drain region (53) formed in the gallium nitride substrate and comprising a drain ohmic metal (52) in contact with a portion of the gallium nitride substrate, the drain ohmic metal having at least one drain interconnect metal layer formed thereon; wherein the number of layers of the source interconnection metal layer is the same as the number of layers of the drain interconnection metal layer;
the source interconnection metal layer has a top-level source metal, the drain interconnection metal layer has a top-level drain metal, and metal width dimensions in a head-to-root direction of the top-level source metal and the top-level drain metal become gradually larger.
2. The gan hemt of claim 1, wherein the top-level source metal and top-level drain metal are trapezoids with the narrowest end of the trapezoids being the head and the widest end of the trapezoids being the root.
3. Gallium nitride high electron mobility transistor according to claim 2, wherein the metal width dimensions f (x) of the top-level source metal and top-level drain metal satisfy the following formula:
f(x)＝kx
where x is the distance from the metal header and k is a constant determined by the transistor design.
4. The gallium nitride high electron mobility transistor of claim 1, wherein the top-level source metal and the top-level drain metal are multi-step structures having a head at a narrowest end and a root at a widest end.
5. Gallium nitride high electron mobility transistor according to any one of claims 1-4, wherein the source interconnect metal layer is a single layer comprising a first source metal (41) formed on the source ohmic metal, and wherein the drain interconnect metal layer is a single layer comprising a first drain metal (51) formed on the drain ohmic metal, the width dimensions of the first source metal, the first drain metal being progressively larger in a head-to-root direction of the first source metal, the first drain metal.
6. Gallium nitride high electron mobility transistor according to claim 5, wherein a second source metal (40) is further stacked on the first source metal (41), and a second drain metal (50) is further stacked on the first drain metal (51), and the width dimensions of the second source metal and the second drain metal become larger gradually in the direction from the head to the root of the second source metal and the second drain metal.
7. Gallium nitride high electron mobility transistor according to claim 1, wherein the gate region (80) comprises a gate stack structure in contact with a portion of the gallium nitride substrate (10).
8. The gallium nitride high electron mobility transistor of claim 7, wherein the gate stack structure is any one of a depletion mode GaN-HEMT, a recessed gate enhancement mode GaN-HEMT, an ion implantation enhancement mode GaN-HEMT, and a p-GaN enhancement mode GaN-HEMT.
9. Gallium nitride high electron mobility transistor according to any of claims 1-4, wherein the gallium nitride substrate (10) comprises a substrate, a nucleation layer, a buffer layer, a first GaN layer, a second GaN layer and an AlGaN barrier layer stacked in this order.
10. Gallium nitride high electron mobility transistor according to any of claims 1-4, wherein the gallium nitride substrate (10) comprises a substrate, a nucleation layer, a buffer layer, a first insertion layer, a first GaN layer, a second insertion layer, a second GaN layer and an AlGaN barrier layer, stacked in this order.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321232833.1U CN219658715U (en) | 2023-05-17 | 2023-05-17 | Gallium nitride high electron mobility transistor for improving MTBF |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117438458A (en) * | 2023-12-20 | 2024-01-23 | 合肥艾创微电子科技有限公司 | Gallium nitride device structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117438458A (en) * | 2023-12-20 | 2024-01-23 | 合肥艾创微电子科技有限公司 | Gallium nitride device structure |
| CN117438458B (en) * | 2023-12-20 | 2024-04-09 | 合肥艾创微电子科技有限公司 | Gallium nitride device structure |
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Address after: Floor 1-5, Building B7, Hefei Innovation and Technology Park, Intersection of Jianghuai Avenue and Sugang Road, Feixi County Economic Development Zone, Hefei City, Anhui Province, 231200 Patentee after: HEFEI AICHUANG MICROELECTRONICS TECHNOLOGY CO.,LTD. Address before: 3rd Floor, East A2, Liheng Industrial Plaza, Hefei Gongtou, Economic Development Zone, Feixi County, Hefei City, Anhui Province, 231200 Patentee before: HEFEI AICHUANG MICROELECTRONICS TECHNOLOGY CO.,LTD. |