CN219658693U - Power semiconductor module - Google Patents
Power semiconductor module Download PDFInfo
- Publication number
- CN219658693U CN219658693U CN202223495817.XU CN202223495817U CN219658693U CN 219658693 U CN219658693 U CN 219658693U CN 202223495817 U CN202223495817 U CN 202223495817U CN 219658693 U CN219658693 U CN 219658693U
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- Prior art keywords
- shell
- semiconductor module
- power semiconductor
- insulating substrate
- layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 239000000919 ceramic Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 6
- 239000000565 sealant Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a power semiconductor module, which relates to the technical field of power electronics and comprises the following components: the bottom of the shell is opened, and at least one cavity is arranged in the shell; the upper cover of the insulating substrate is provided with a shell, the surface of the insulating substrate is provided with at least one power chip, and each power chip is arranged in the cavity; the insulating substrate includes: the lower surface of the first metal layer is connected with the upper surface of the ceramic layer; the upper surface of the second metal layer is connected with the lower surface of the ceramic layer; the lower surface of the side wall of the shell does not exceed the lower surface of the second metal layer, and the horizontal interval between the lower surface of the side wall of the shell and the second metal layer is a first interval; the inner side wall of the shell is provided with a notch corresponding to the insulating substrate, a second interval is arranged between the upper surface of the notch and the upper surface of the ceramic layer, and an elastic layer is arranged in the second interval; the electric connection structures are connected with the power chip through connection wires, are perpendicular to the insulating substrate, and are exposed and extend from the corresponding openings of the shell. The beneficial effect is that the elastic layer is filled between the shell and the insulating substrate for buffering pressure.
Description
Technical Field
The utility model relates to the technical field of power electronics, in particular to a power semiconductor module.
Background
The power semiconductor module generates heat during operation, the temperature has a great influence on its safe and reliable operation, and good thermal contact between the power semiconductor module and a heat sink for heat transfer is of great importance for the operation of the module at safe operating temperatures.
The power semiconductor chips are mounted on an electrically insulating substrate (exemplified by a ceramic substrate) within the power semiconductor module. The ceramic substrate comprises a ceramic base to which pure copper is soldered with high bond strength by high temperature melting and diffusion treatment, and the module typically further comprises a housing that protects the power semiconductor components from damage. The primary means of attachment of the module to the heat sink is by pressure contact through a threaded connection that applies pressure on the housing, which can damage the ceramic substrate of the electrically insulating substrate.
It is therefore desirable to limit the pressure of the housing against the electrically insulating substrate and to reduce the impact of the threaded connection on the electrically insulating substrate during installation.
Disclosure of Invention
In view of the problems existing in the prior art, the present utility model provides a power semiconductor module, comprising:
the bottom of the shell is provided with an opening, and at least one cavity is arranged in the shell;
the insulating substrate is covered by the shell, at least one power chip is arranged on the surface of the insulating substrate, and each power chip is arranged in the cavity; the insulating substrate includes:
the lower surface of the first metal layer is connected with the upper surface of the ceramic layer;
the upper surface of the second metal layer is connected with the lower surface of the ceramic layer;
the lower surface of the side wall of the shell does not exceed the lower surface of the second metal layer, and the horizontal interval between the lower surface of the side wall of the shell and the lower surface of the side wall of the shell is a first interval;
a gap corresponding to the insulating substrate is formed in the inner side wall of the shell, a second interval is formed between the upper surface of the gap and the upper surface of the ceramic layer, and an elastic layer is arranged in the second interval;
and at least one electric connection structure, wherein each electric connection structure is connected with the power chip through a connection wire, is perpendicular to the insulating substrate, and is exposed and extends from an opening correspondingly formed in the shell.
Preferably, the two sides of the shell are also connected with mounting structures, and the lower surfaces of the mounting structures and the lower surfaces of the side walls of the shell are on the same horizontal line.
Preferably, the power semiconductor module is further connected to a radiator, and the radiator is provided with a screw hole, and each mounting structure is provided with a through hole corresponding to the screw hole, and the through hole is connected with the screw hole by passing through a bolt, so that the through hole is fixedly connected with the radiator.
Preferably, the insulating substrate includes: copper bond substrates, or aluminum bond substrates, or active metal braze substrates.
Preferably, the cavities are separated by spacers, and each spacer is in contact with the upper surface of the first metal layer.
Preferably, the elastic layer is prepared by adopting an elastic sealant.
Preferably, the power chip comprises a diode, or an insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, or a junction field effect transistor, or a high electron mobility transistor.
Preferably, the value range of the first interval is 0.05mm-0.5mm.
Preferably, the value range of the second interval is 0mm-0.3mm.
Preferably, the first metal layer is a continuous layer, or a structured layer.
The technical scheme has the following advantages or beneficial effects: by forming the notch corresponding to the insulating substrate on the shell and filling the elastic material between the notch and the insulating substrate, the pressure generated by the threaded connection structure when the radiator is connected with the power semiconductor module is reduced, and the insulating substrate is prevented from being damaged by excessive pressure on the shell.
Drawings
FIG. 1 is a schematic view showing the overall structure of a power semiconductor module before mounting according to a preferred embodiment of the present utility model;
fig. 2 is a schematic diagram showing the overall structure of a power semiconductor module after being mounted in accordance with the preferred embodiment of the present utility model;
FIG. 3 is a schematic diagram of a structured layer according to a preferred embodiment of the present utility model.
Detailed Description
The utility model will now be described in detail with reference to the drawings and specific examples. The present utility model is not limited to the embodiment, and other embodiments may fall within the scope of the present utility model as long as they conform to the gist of the present utility model.
In a preferred embodiment of the present utility model, based on the above-mentioned problems occurring in the prior art, there is now provided a power semiconductor module, as shown in fig. 1 and 3, comprising:
a housing 1, wherein the bottom of the housing 1 is open and at least one cavity 2 is arranged in the housing;
the power chip comprises an insulating substrate 3, wherein a shell 1 is arranged on the upper cover of the insulating substrate 3, at least one power chip 4 is arranged on the surface of the insulating substrate 3, and each power chip 4 is arranged in a cavity 2;
the insulating substrate 3 includes:
a first metal layer 31, a lower surface of the first metal layer 31 being connected to an upper surface of the ceramic layer 32;
a second metal layer 33, an upper surface of the second metal layer 33 being connected to a lower surface of the ceramic layer 32;
the lower surface of the sidewall of the case 1 does not exceed the lower surface of the second metal layer 33 with a horizontal interval of the first interval d1 therebetween;
the inner side wall of the shell 1 is provided with a notch 11 corresponding to the insulating substrate, the upper surface of the notch 11 is parallel to the upper surface of the first metal layer 31, a second interval d2 is arranged between the upper surface of the notch 11 and the upper surface of the ceramic layer 32, and an elastic layer 5 is arranged in the second interval d 2;
at least one electrical connection structure 6, each electrical connection structure 6 is connected to the power chip 4 through a connection wire 61, and each electrical connection structure 6 is perpendicular to the insulating substrate 3 and exposed and extends from a corresponding opening of the housing 1.
Specifically, in this embodiment, the power semiconductor module provided by the present utility model needs to be mounted on the heat sink 100, as shown in fig. 1, at this time, the length of the first metal layer 31 is smaller than that of the ceramic layer 32, so that the elastic layer 5 may be filled in the first space d1, at this time, the lower surface of the second metal layer 33 slightly exceeds the lower surface of the side wall of the housing 1, so that the insulating substrate 3 may be ensured to be in close contact with the heat sink 100 through the second metal layer 33, and a good heat dissipation effect may be achieved; as shown in fig. 2, the power semiconductor module of the present utility model has been mounted on the heat sink 100 at this time, and the elastic layer 5 is compressed due to the pressure F1 of the housing 1, and since the elastic layer 5 has good elasticity, it is possible to ensure the close contact of the lower surface of the second metal layer 33 with the heat sink 100, and to reduce the pressure of the housing 1 during and after the mounting, and to prevent the insulating substrate 3 from being damaged by excessive pressure.
In the preferred embodiment of the present utility model, the mounting structure 12 is further connected to both sides of the housing 1, and the lower surface of the mounting structure 12 and the lower surface of the side wall of the housing 1 are on the same horizontal line.
In the preferred embodiment of the present utility model, the power semiconductor module is further connected to the heat sink 100, and the heat sink 100 is provided with a screw hole 101, so that each mounting structure 12 is provided with a through hole 13 corresponding to the screw hole 101, and the through hole 13 is connected to the screw hole 101 by a bolt 7, and is fixedly connected to the heat sink 100.
Specifically, in this embodiment, through holes 13 of the mounting structure 12 connected through two sides of the housing 1 by bolts 7 are correspondingly connected with screw holes 101 on the heat sink 100, so as to realize tight connection between the power semiconductor module and the heat sink 100.
In a preferred embodiment of the present utility model, the insulating substrate 3 includes: copper bond substrates, or aluminum bond substrates, or active metal braze substrates.
In the preferred embodiment of the present utility model, the cavities 2 are separated by spacers 8, and each spacer 8 is in contact with the upper surface of the first metal layer 31.
Specifically, in this embodiment, the cavities 2 are separated by the spacer columns 8, and the spacer columns 8 are in contact with the upper surface of the first metal layer 31, so that the two sides of the insulating substrate 3 can be prevented from being pressed to cause the middle bulge, the connection with the radiator 100 is not tight, the heat dissipation effect is not good, and the insulating substrate 3 can be prevented from being deformed under pressure.
In a preferred embodiment of the utility model, the elastic layer 5 is made of an elastic sealant.
Specifically, in this embodiment, the elastic layer 5 may be prepared by selecting an elastic sealant with different elastic properties, so as to achieve a better buffering effect, and in this embodiment, a rubber type sealant is preferably used, which has a shore a hardness after curing.
In a preferred embodiment of the utility model, the power chip 4 comprises a diode, or an insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, or a junction field effect transistor, or a high electron mobility transistor.
In a preferred embodiment of the present utility model, the first distance d1 has a value ranging from 0.05mm to 0.5mm.
In a preferred embodiment of the present utility model, the second distance d2 has a value ranging from 0mm to 0.3mm.
In a preferred embodiment of the present utility model, the first metal layer 31 is a continuous layer, or a structured layer.
Specifically, in this embodiment, as shown in fig. 3, the first metal layer 31 may also be a discontinuous structured layer.
The foregoing is merely illustrative of the preferred embodiments of the present utility model and is not intended to limit the embodiments and scope of the present utility model, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present utility model.
Claims (10)
1. A power semiconductor module, comprising:
the bottom of the shell is provided with an opening, and at least one cavity is arranged in the shell;
the insulating substrate is covered by the shell, at least one power chip is arranged on the surface of the insulating substrate, and each power chip is arranged in the cavity; the insulating substrate includes:
the lower surface of the first metal layer is connected with the upper surface of the ceramic layer;
the upper surface of the second metal layer is connected with the lower surface of the ceramic layer;
the lower surface of the side wall of the shell does not exceed the lower surface of the second metal layer, and the horizontal interval between the lower surface of the side wall of the shell and the lower surface of the side wall of the shell is a first interval;
a gap corresponding to the insulating substrate is formed in the inner side wall of the shell, a second interval is formed between the upper surface of the gap and the upper surface of the ceramic layer, and an elastic layer is arranged in the second interval;
and at least one electric connection structure, wherein each electric connection structure is connected with the power chip through a connection wire, is perpendicular to the insulating substrate, and is exposed and extends from an opening correspondingly formed in the shell.
2. The power semiconductor module according to claim 1, wherein mounting structures are further connected to both sides of the housing, and a lower surface of the mounting structures and a lower surface of a side wall of the housing are on the same horizontal line.
3. The power semiconductor module according to claim 2, wherein the power semiconductor module is further connected to a heat sink, and the heat sink is provided with a screw hole, and each of the mounting structures is provided with a through hole corresponding to the screw hole, and is connected to the screw hole by passing a bolt through the through hole, so as to be fixedly connected to the heat sink.
4. The power semiconductor module of claim 1, wherein the insulating substrate comprises: copper bond substrates, or aluminum bond substrates, or active metal braze substrates.
5. The power semiconductor module of claim 1, wherein the cavities are separated by spacers, each of the spacers being in contact with an upper surface of the first metal layer.
6. The power semiconductor module of claim 1, wherein the elastic layer is prepared using an elastic sealant.
7. The power semiconductor module of claim 1, wherein the power chip comprises a diode, or an insulated gate bipolar transistor, or a metal oxide semiconductor field effect transistor, or a junction field effect transistor, or a high electron mobility transistor.
8. The power semiconductor module of claim 1, wherein the first pitch has a value in a range of 0.05mm to 0.5mm.
9. The power semiconductor module of claim 1, wherein the second pitch has a value in the range of 0mm to 0.3mm.
10. The power semiconductor module of claim 1, wherein the first metal layer is a continuous layer, or a discontinuous structured layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223495817.XU CN219658693U (en) | 2022-12-27 | 2022-12-27 | Power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223495817.XU CN219658693U (en) | 2022-12-27 | 2022-12-27 | Power semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219658693U true CN219658693U (en) | 2023-09-08 |
Family
ID=87860130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223495817.XU Active CN219658693U (en) | 2022-12-27 | 2022-12-27 | Power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219658693U (en) |
-
2022
- 2022-12-27 CN CN202223495817.XU patent/CN219658693U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: No.988, Kexing Road, Nanhu District, Jiaxing City, Zhejiang Province Patentee after: Star Semiconductor Co.,Ltd. Address before: No.988, Kexing Road, Nanhu District, Jiaxing City, Zhejiang Province Patentee before: STARPOWER SEMICONDUCTOR Ltd. |