CN219642840U - Display substrate and display device comprising same - Google Patents

Abstract

The embodiment of the utility model discloses a display substrate and a display device comprising the same. In a specific embodiment, the display substrate includes a substrate; the buffer layer is arranged on the substrate, and a groove is formed in one side, away from the substrate, of the buffer layer; an active layer disposed on the buffer layer, a portion of the active layer on the recess conforming to a surface of the buffer layer; a gate electrode disposed on the active layer within the recess; and a gate insulating layer disposed within the recess between the active layer and the gate electrode. The utility model can realize a passivation layer with gentle morphology and a flat source-drain electrode layer by providing the groove in the structure below the grid electrode of the display panel comprising the top grid type thin film transistor and arranging the grid electrode in the groove. The method has the advantages that the shading effect of the thin film transistor is improved, meanwhile, poor corrosion of the through hole is effectively solved, the AOI detection rate and the illumination stability of the driving transistor are improved, and the product yield and quality of the display panel are improved.

Description

Display substrate and display device comprising same

Technical Field

The present utility model relates to the field of display technologies, and in particular, to a display panel and a display device including the display substrate.

Background

With the continuous development of display technologies, organic Light-Emitting Diode (OLED) display technologies have been increasingly used in display devices such as mobile phones, tablet computers, digital cameras, etc. due to their advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, high response speed, etc.

The display back plate of the large-size and high-resolution display device generally adopts a top gate type thin film transistor, and the top gate type thin film transistor comprises an active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode layer and an interlayer dielectric layer, wherein the source electrode and the drain electrode layer are connected with the active layer through a via hole on the interlayer dielectric layer. In some thin film transistor structure designs, a source-drain electrode layer is overlaid over the gate to reduce the effect of light on transistor performance. The step structure of the source-drain electrode layer climbing gate electrode provides higher requirements for the transistor preparation process.

Disclosure of Invention

In order to solve the above problems, an aspect of the present utility model provides a display substrate including

A substrate base;

the buffer layer is arranged on the substrate, and a groove is formed in one side, away from the substrate, of the buffer layer;

an active layer disposed on the buffer layer, a portion of the active layer on the recess conforming to a surface of the buffer layer;

the grid electrode is arranged in the groove and is positioned at one side of the active layer away from the substrate; and

and the gate insulating layer is arranged in the groove and positioned between the active layer and the gate.

Optionally, a groove is formed on one side, close to the buffer layer, of the substrate, and the part, on the groove, of the buffer layer is conformal with the surface of the substrate.

Optionally, the surface of the gate, the surface of the active layer outside the recess region, and the surface of the gate insulating layer between the gate and the active layer in a direction parallel to the substrate are substantially flush.

Optionally, the display substrate further includes a first conductive structure layer disposed between the surface of the substrate and the buffer layer, where the first conductive structure layer is a first metal layer, or the first conductive structure layer includes a first metal layer disposed on the surface of the substrate and a first conductive metal oxide layer disposed on the first metal layer.

Optionally, the display substrate further includes a first conductive structure layer disposed between the substrate surface and the buffer layer, the first conductive structure layer including a first metal layer disposed on the substrate surface and a first conductive metal oxide layer disposed on the first metal layer, and an orthographic projection of the first conductive metal oxide layer on the substrate surface covers an orthographic projection of the groove on the substrate surface.

Optionally, the display substrate further includes an interlayer insulating layer covering the gate electrode surface, the gate insulating layer surface, and the active layer surface, the interlayer insulating layer having a flat surface on a side remote from the substrate.

Optionally, the display substrate further includes a source-drain electrode layer having a flat structure disposed on a surface of the interlayer insulating layer, and the source-drain electrode layer is electrically connected to the active layer through a via hole penetrating the interlayer insulating layer.

Optionally, the orthographic projection of the source-drain electrode layer on the substrate at least partially overlaps with the orthographic projection of the gate electrode on the substrate.

Optionally, a height difference between the gate surface and the active layer surface is smaller than a thickness of the source drain electrode layer.

Optionally, the display substrate further comprises

A passivation layer disposed on the exposed surface of the interlayer insulating layer and the source and drain electrode layer;

a second insulating layer disposed on a surface of the passivation layer on a side remote from the substrate base plate; and

and a first electrode disposed on a surface of the second insulating layer, the first electrode being electrically connected to the source-drain electrode layer through an opening region penetrating the second insulating layer and the passivation layer.

Optionally, the orthographic projection of the groove on the surface of the substrate does not overlap with the orthographic projection of the opening region on the surface of the substrate.

Optionally, the orthographic projection of the opening area on the substrate covers the orthographic projection of the interlayer insulating layer via hole on the surface of the substrate.

Another aspect of the present utility model provides a display device including the display panel as described above.

The beneficial effects of the utility model are as follows:

according to the display panel, the groove is formed in the structure below the grid electrode, the grid electrode of the top grid type thin film transistor is arranged in the groove to form the landfill structure, the surface of the grid electrode is approximately flush relative to the surface of the active layer, the step of the source drain electrode layer for climbing the grid electrode is eliminated, and the passivation layer with gentle morphology and the flat source drain electrode layer are provided. The design of the flat morphology can effectively avoid folds formed by steps in the process of forming the passivation layer on the surface of the source-drain electrode layer while increasing the shading effect of the thin film transistor, protects the source-drain electrode layer from being corroded by corrosive liquid along folds in the subsequent process, can effectively solve the problem of poor corrosion of the via hole, prevents the occurrence of AOI explosion points and poor hole contact in automatic optical detection (AOI), improves the AOI detection rate and the illumination stability of the driving transistor, improves the product yield and quality of the display panel, and improves the yield of large-size products, especially the yield of 95 inch 8K products. Furthermore, the display panel of the utility model omits the step of the interlayer insulating layer and the source-drain electrode layer for climbing the grid electrode, saves the step of forming the step by the interlayer insulating layer, saves the process time and reduces the manufacturing cost while simplifying the process flow.

Drawings

The following describes the embodiments of the present utility model in further detail with reference to the drawings.

Fig. 1 is a schematic cross-sectional structure of a conventional display panel.

Fig. 2 is a schematic diagram showing a defect of a conventional display panel structure.

Fig. 3 shows a schematic cross-sectional structure of a display panel according to a first embodiment of the present utility model.

Fig. 4 shows a schematic plan layout of the display panel shown in fig. 3.

Fig. 5 shows a flowchart of a method of manufacturing a display panel according to the present utility model.

Fig. 6A to 6F are schematic views showing a manufacturing process structure of the display panel shown in fig. 3.

Fig. 7 shows a schematic cross-sectional structure of a display panel according to a second embodiment of the present utility model.

Fig. 8A-8B are schematic views showing a manufacturing process of a display panel according to a second embodiment of the present utility model.

Fig. 9 is a schematic cross-sectional structure of a display panel according to a third embodiment of the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. The drawings are merely illustrative and, for ease of explanation, the drawings may not be drawn to scale. Furthermore, throughout the drawings used to describe the various embodiments, components having the same or similar functions may be represented by the same reference numerals or numerals. Descriptions of the same or similar components may be omitted.

It should be understood that the embodiments described in this disclosure are some, but not all, embodiments of the disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "up and down", "left and right", and the like are used only to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed accordingly. The terms "formed on … …", "formed on … …" and "disposed on … …" and the like may refer to one layer being formed directly on or disposed on another layer, or may refer to one layer being formed indirectly on or disposed on another layer, i.e., there may be other layers between the two layers. In this disclosure, the term "co-layer arrangement" means that both are formed from the same material layer, so they are in the same layer in a stacked relationship, but do not represent equal distances from the substrate, nor that they are identical to other layer structures between the substrate. In this disclosure, "surface" refers to the surface of the structure being described on the side remote from the substrate base. Fig. 1 is a schematic cross-sectional structure of a conventional display panel, and as shown, the display panel 100 includes a base substrate 101, a metal layer 102, a buffer layer 103 and an active layer 111 sequentially stacked on the base substrate 101, a gate insulating layer 112 and a gate electrode 113 disposed on the active layer 111, an interlayer Insulating Layer (ILD) 104 covering the gate electrode and the exposed active layer, a source drain electrode layer (SD) 105 disposed on the interlayer insulating layer, a passivation layer (PVX) 106 covering the exposed source drain electrode layer and the interlayer insulating layer, a Resin layer (Resin) 107 disposed on the passivation layer, and a first electrode layer 108. In this display panel circuit structure, the active layer 111, the gate insulating layer 112, and the gate electrode 113 constitute a thin film transistor, and the source-drain electrode layer 105 is electrically connected to the active layer 111 through a via hole 121 penetrating the interlayer insulating layer 104. The resin layer 107 serves as a planarizing layer and defines an opening region for forming a via hole together with the passivation layer 106 and the interlayer insulating layer 104, and the first electrode 108 is electrically connected to the source-drain electrode layer 105 in the opening region. In a display device, a light shielding layer is generally provided to prevent light from affecting an active layer in order to improve stability of a driving thin film transistor. The metal layer 102 on the substrate in the display panel can be used as a light shielding layer to prevent the active layer 111 from being irradiated by light from the substrate. The source drain electrode layer 105 is disposed to at least partially overlap the gate electrode 113 for avoiding an influence of light irradiation on a channel portion of the active layer under the gate electrode. Because the source electrode layer and the drain electrode layer need to be arranged above the grid electrode, the corresponding interlayer insulating layer needs to be designed in a climbing manner. As shown in fig. 1, the source-drain electrode layer includes a first portion STP1 provided on the surface of the interlayer insulating layer to at least partially overlap the gate electrode, a second portion STP2 as the bottom of the opening region, and a third portion STP3 electrically connected to the active layer through a hole penetrating the interlayer insulating layer. In the manufacturing process of the display panel, when the passivation layer covering the source and drain electrode layer is formed after the source and drain electrode layer is formed, the passivation layer is likely to form wrinkles on the surface of the second portion STP2 of the source and drain electrode layer due to the step. In the subsequent process of forming the opening region by opening the planarization layer and the passivation layer, the source and drain electrode layers are corroded by the infiltration of the developer through the wrinkles, as shown in the left part of fig. 2, which has a serious influence on the optical and electrical properties of the display device, for example, formation of thin dark spot clusters or AOI burst spots, as shown in the right part of fig. 2.

The utility model provides an optimized design of a thin film transistor, particularly a driving transistor, below a display area via hole. The display panel includes a substrate base; the buffer layer is arranged on the substrate, and a groove is formed in one side, away from the substrate, of the buffer layer; an active layer disposed on the buffer layer, a portion of the active layer on the recess conforming to the buffer layer; the grid electrode is arranged in the groove and is positioned at one side of the active layer away from the substrate; and a gate insulating layer disposed within the recess and between the active layer and the gate electrode. By "conformal" herein may be meant that the two shapes are identical or substantially similar. By providing a recess in the structure under the gate of the thin film transistor, the gate of the thin film transistor is disposed in the recess, a series of topography structures of the planar gate surface and active layer surface, planar interlayer insulating layer surface and planar source-drain electrode layer surface are constructed. Since the surface of the gate electrode is substantially flush with respect to the surface of the active layer outside the recess region, the step of the source-drain electrode layer for climbing the gate electrode is eliminated, and the height of the interlayer insulating layer between the source-drain electrode layer and the gate electrode can be effectively reduced, thereby eliminating the step of the interlayer insulating layer surface for providing the bottom of the opening region or for reducing the height of the source-drain electrode layer, and providing a possibility for designing the thickness of the flat interlayer insulating layer to form the flat source-drain electrode layer as required. According to the design of the flat morphology, under the condition that the breakage defect of the passivation layer at the step positions of the climbing grid electrode of the source drain electrode layer and the step position of the climbing source drain electrode layer of the passivation layer is reduced, the effect that the light shielding layer and the source drain electrode layer shield the illumination of the driving transistor is increased, the phenomenon that the passivation layer forms folds due to the existence of the step in the process of forming the passivation layer on the surface of the source drain electrode layer can be effectively avoided, the source drain electrode layer is protected from being corroded in the opening process of the passivation layer, the optical and electrical defects caused by the corrosion of the source drain electrode layer are reduced, the product yield and quality of the display panel are improved, and the large-size product yield is improved.

Fig. 3 is a schematic cross-sectional structure of a display panel according to a first embodiment of the present utility model, and fig. 4 is a plan layout view of the display panel according to the embodiment. As shown in fig. 3, the display panel 200 includes a base substrate 201, and a metal layer 202, a buffer layer 203, and an active layer 211, which are sequentially stacked on the base substrate 201. A gate insulating layer 212 disposed on the active layer 211 and a gate electrode 213 disposed on the gate insulating layer, an interlayer insulating layer 204 covering the gate electrode and the exposed active layer and the gate insulating layer, a source drain electrode layer 205 partially disposed on the interlayer insulating layer, a passivation layer 206 covering the exposed source drain electrode layer and the interlayer insulating layer, a resin layer 207 disposed on the passivation layer, and a first electrode layer 208. The active layer 211, the gate electrode 213, and the gate insulating layer 212 therebetween constitute a thin film transistor TFT. The source-drain electrode layer 205 is electrically connected to the active layer 211 through a via 230 penetrating the interlayer insulating layer, and the first electrode 208 is electrically connected to the source-drain electrode layer 205 through an opening region 240 penetrating the resin layer 207 and the passivation layer 206.

In this embodiment, the substrate 201 is, for example, a glass substrate with a recess 220 formed therein, the depth and size of the recess being configured to receive the gate electrode and the associated layers between the gate electrode and the glass substrate. The metal layer 202 is provided on a surface of the substrate base 201 on a side having a groove, and a portion on the groove conforms to the groove to maintain a groove shape for accommodating the gate electrode. The buffer layer 203 is disposed on a surface of the metal layer 202 having a groove and a portion on the groove conforms to the groove to maintain a groove shape for accommodating the gate electrode. The active layer 211 is disposed on the surface of the buffer layer 203 having the grooves and portions on the grooves conform to the grooves, maintaining the shape of the grooves for accommodating the gates. The active layer may include an oxide semiconductor or the like, for example, the oxide semiconductor includes a metal oxide semiconductor, for example, the metal oxide semiconductor includes Indium Gallium Zinc Oxide (IGZO), and IGZO is described herein as an example, but it should be understood that the technical scheme of the present utility model is not limited thereto. The gate insulating layer 212 is disposed in and conformally with the recess of the active layer 211, and the gate electrode 213 is disposed in the recess of the gate insulating layer 212. As shown, the gate 213 is received in a recess 220 provided by the underlying layers, wherein the surface of the gate, the surface of the active layer outside the recess area, and the exposed surface of the gate insulation layer between the gate and the active layer in a direction parallel to the substrate are substantially flush, as a preferred embodiment. The interlayer insulating layer 204 covers the gate surface, the exposed surface of the gate insulating layer, and the exposed surface of the active layer, and has a flat surface on the side remote from the substrate. The source and drain electrode layer 205 is disposed on the flat surface of the interlayer insulating layer and has a flat structure, and is electrically connected to the active layer through a via 230 penetrating the interlayer insulating layer. As a preferred embodiment, the orthographic projection of the source-drain electrode layer on the substrate and the orthographic projection of the grid electrode on the substrate are at least partially overlapped, so as to shield the light-emitting unit from illuminating the thin film transistor to cause instability of the thin film transistor. Therefore, the structure of the utility model is preferably suitable for the driving transistor of the display panel, provides stable driving performance for the display panel, and improves the quality and yield of products.

In an OLED display panel, particularly in a large-sized display panel, a metal layer formed on a substrate base plate may be used as a light shielding layer for preventing light from reaching a channel region of an active layer through a glass substrate, improving stability of a thin film transistor; and may also be used as electrode layers, for example to form storage capacitors with the source and drain electrode layers of the thin film transistor and other conductive layers, such as ITO layers, located over the thin film transistor, respectively. The different capacitors have different requirements on the thickness of the inter-electrode dielectric layer, and the manufacturing process of the thin film transistor display panel also has corresponding requirements on the thickness of the insulating layer and the size of the via hole between which the via hole is formed, so that the thickness of each insulating layer and the thickness of the dielectric layer are reduced, the size of the via hole is reduced, and the miniaturization, the light weight and the high resolution of the display panel are realized. The grid electrode is accommodated in the groove, so that the height difference between the grid electrode and the active layer is reduced, the height of an interlayer insulating layer between the source electrode layer and the drain electrode layer can be effectively reduced, and the source electrode layer and the drain electrode layer can be overlapped with the grid electrode without climbing; it is possible to design the thickness of the interlayer insulating layer as needed to provide the interlayer insulating layer with a flat surface. The lowering of the height of the interlayer insulating layer may eliminate the step required for the interlayer insulating layer to realize the interlayer insulating layer via hole for the first electrode electrical connection, eliminate the step required for the source-drain electrode layer to be used as the second electrode of the storage capacitor, such as step STP2 in fig. 1, make it possible to design and realize the interlayer insulating layer having a flat surface according to performance requirements and process requirements and thereby form the source-drain electrode layer having a flat structure on the flat interlayer insulating layer surface.

The passivation layer 206 is disposed on the flat surface of the source/drain electrode layer, so that wrinkles of the passivation layer on the surface of the source/drain electrode layer due to multiple steps of the source/drain electrode layer are avoided. An opening region 240 through the resin layer 207 and the passivation layer 206 provides a via hole for electrically connecting the first electrode to the source-drain electrode layer 205, and an orthographic projection of the opening region 240 on the substrate covers the interlayer insulating layer to provide an orthographic projection of the via hole 230 for electrically connecting the source-drain electrode layer to the active layer on the surface of the substrate. As a preferred embodiment, the orthographic projection of the opening area 240 on the substrate does not overlap with the orthographic projection of the groove for accommodating the gate electrode on the surface of the substrate.

FIG. 5 shows a flow chart of a method of manufacturing a display panel according to the utility model, the method comprising providing a substrate base plate; a buffer layer is formed on the substrate, and a groove is formed on one side of the buffer layer away from the substrate; forming an active layer on the surface of the buffer layer, wherein the part of the active layer on the groove is conformal with the groove; forming a gate insulating layer on the surface of the active layer, wherein the part of the gate insulating layer on the groove is conformal with the groove; forming a gate in the recess; and patterning the gate insulating layer to expose the surface of the active layer outside the groove.

The method further includes forming an interlayer insulating layer having a flat surface on a surface of the gate electrode, a surface of the active layer located outside the recess region, and a surface of the gate insulating layer located between the gate electrode and the active layer in a direction parallel to the substrate, forming a via hole penetrating the interlayer insulating layer; and forming a source-drain electrode layer on the surface of the obtained structure, wherein the orthographic projection of the source-drain electrode layer on the substrate and the orthographic projection of the grid electrode on the substrate are at least partially overlapped, and the source-drain electrode layer is electrically connected with the active layer through the via hole penetrating through the interlayer insulating layer.

The method for manufacturing the display panel of the first embodiment shown in fig. 3 is specifically described below with reference to fig. 6A to 6F.

A substrate, such as a glass substrate 201, is provided, and a recess 220 is formed in one side of the substrate, as shown in fig. 6A.

A first metal layer 202 is deposited on the grooved surface of the substrate base plate. The first metal layer 202 is patterned and portions of the metal layer over the grooves of the substrate conform to the grooves. The patterned metal layer can be used as a light shielding layer of the thin film transistor and as a first electrode of the storage capacitor. The storage capacitor is used as a storage capacitor of the second electrode with, for example, a source-drain electrode layer, a storage capacitor of the second electrode with, for example, an ITO layer on a planarization layer, or the like. A buffer layer 203 is formed on the surface of the first metal layer 202, and the portion of the buffer layer on the groove is conformal with the groove in the metal layer. Forming an IGZO active layer 211 on the surface of the buffer layer 203, wherein a portion of the active layer on the groove is conformal with the groove in the buffer layer; a gate insulating layer 212 is formed on the IGZO active layer surface, and a portion of the gate insulating layer on the groove conforms to the IGZO active layer groove, as shown in fig. 6B.

A gate metal layer is deposited on the surface of the gate insulating layer, and the metal material is copper Cu or aluminum Al, for example. The gate metal layer is patterned to obtain a gate 213, e.g. a block structure, received in the recess. The gate insulating layer is then stripped to obtain a gate insulating layer 212 disposed between the active layer 211 and the gate electrode 213, exposing the surface of the active layer outside the recess. As a preferred embodiment of the present utility model, the resulting height difference between the gate surface and the exposed active layer surface is less than the thickness of the source drain electrode layer. As another preferred embodiment of the present utility model, the resulting gate surface, active layer surface and gate insulator surface therebetween are substantially flush surfaces, as shown in fig. 6C.

Providing a recess in the substrate below the gate electrode and maintaining the recess shape in the layers on the substrate, in particular in the active layer and the gate insulation layer, makes it possible to provide the gate electrode of the top gate thin film transistor in the recess, reducing the height difference between the gate surface and the active layer surface. And a certain height difference is allowed between the surface of the grid electrode and the surface of the active layer, so long as the height difference does not affect the surface of the interlayer insulating layer formed on the surface to have a gentle slope, the process redundancy is provided for the grid electrode patterning process and the stripping process of the grid electrode insulating layer, and the process difficulty is reduced.

The exposed IGZO active layer is then subjected to conductor formation.

Depositing an insulating layer 204, such as SiO, on the resulting structure surface ₂ An insulating layer as an interlayer insulating layer. The interlayer insulating layer is subjected to an opening process to obtain a via 230 penetrating the interlayer insulating layer. And depositing a metal layer on the surface of the obtained structure, wherein the metal material can be copper Cu or aluminum Al. The metal layer is patterned to obtain the source-drain electrode layer 205. The orthographic projection of the source-drain electrode layer 205 on the substrate and the orthographic projection of the gate on the substrate are at least partially overlapped, so as to shade the channel region of the thin film transistor. In the present utility model, since the gate surface is substantially flush with the exposed gate insulating layer surface and the exposed active layer surface, the thickness of the interlayer insulating layer can be set according to the requirement of the insulating property of each conductive layer or the requirement of the insulating layer dielectric property for forming the storage capacitor, and the thickness of the interlayer insulating layer of the source drain electrode layer climbing gate structure in the prior art shown in fig. 1 is reduced.

Depositing a passivation layer 206, for example, silicon oxide SiO with a thickness of 3000-5000A, on the resulting structure surface _x And a passivation layer covering the exposed interlayer insulating layer surface and the exposed source drain electrode layer surface. The source electrode layer and the drain electrode layer are of flat structures, and the passivation layer formed on the source electrode layer and the drain electrode layer completely cover the surfaces of the source electrode layer and the drain electrode layer, so that the phenomena of wrinkling and the like caused by the existence of steps are avoided. A resin layer 207 is deposited as a planarizing layer on the surface of the resulting passivation layer. The resin layer and the passivation layer are patterned to form an opening region 240 penetrating the resin layer and the passivation layer, and the source and drain electrode layer is exposed at the bottom of the opening region, as shown in fig. 6E. Because the passivation layer completely covers the surface of the source drain electrode layer, in the etching process for forming the opening area, corrosive liquid such as developing solution cannot permeate into the surface of the source drain electrode layer due to the existence of folds of the passivation layer to further influence the optical performance and the electrical performance of the display panel, and dark spot clusters and explosion spots of the display panel are avoided.

An electrode layer, such as an oxide metal electrode ITO layer, is then deposited on the resulting structure surface and patterned to form a first electrode that is electrically connected to the source-drain electrode layer through the open area, as shown in FIG. 6F.

Compared with the preparation method of the display panel circuit in the prior art shown in fig. 1, the display panel of the utility model realizes that the source-drain electrode layer shields the thin film transistor from illumination to improve the transistor performance, and meanwhile, the step STP2 of the interlayer insulating layer and the source-drain electrode layer for climbing the grid is eliminated, thereby saving the perforating process for forming the step STP2, shortening the process time and reducing the manufacturing cost of the display panel.

Fig. 7 is a schematic cross-sectional structure of a display panel 300 according to a second embodiment of the present utility model. Unlike the first embodiment shown in fig. 3, as shown in fig. 7, a groove for accommodating the gate electrode below the gate electrode is not provided in the substrate base plate but provided from the buffer layer. Specifically, the display panel 300 includes a substrate base 301, a metal layer 302 disposed on the substrate base; a buffer layer 303 disposed on the metal layer, the buffer layer 303 having a recess 320 formed on a surface thereof remote from the side of the substrate; an active layer 311 disposed on a surface of the buffer layer having a groove, a portion of the active layer on the groove conforming to the groove in the buffer layer, maintaining a groove shape for accommodating the gate electrode; a gate insulating layer 312 disposed within and conformal with the recess of the active layer 311; and a gate electrode 313 disposed in the recess of the gate insulating layer 312. The active layer 311, the gate electrode 313, and the gate insulating layer 312 therebetween constitute a thin film transistor TFT. As shown, the surface of the gate, the exposed surface of the active layer outside the recess, and the exposed surface of the gate insulating layer between the gate and active layers are substantially flush.

Other circuit structures of the display panel 300 are similar to those of the first embodiment shown in fig. 3. The display panel further includes an interlayer insulating layer 304 covering the gate electrode and the exposed active layer and gate insulating layer, a source-drain electrode layer 305 partially disposed on the interlayer insulating layer, a passivation layer 306 covering the exposed source-drain electrode layer and the interlayer insulating layer, a resin layer 307 disposed on the passivation layer, and a first electrode layer 308. The active layer 311, the gate electrode 313, and the gate insulating layer 312 therebetween constitute a thin film transistor TFT. The source/drain electrode layer 305 is electrically connected to the active layer 311 through a via 330 penetrating the interlayer insulating layer, and the first electrode 308 is electrically connected to the source/drain electrode layer 305 through an opening region 340 penetrating the resin layer 307 and the passivation layer 306.

According to the circuit structure of the preferred embodiment, by arranging the grooves in the buffer layer, the process links of grooving in the glass substrate can be saved, the process time can be shortened, and the manufacturing cost can be reduced. Further, by arranging the grooves in the buffer layer, the circuit structure of the utility model can be applied to a flexible display panel with a substrate base plate made of flexible materials, and a flexible light and thin display device is realized.

The manufacturing method of the display panel 300 of the second embodiment of the present utility model includes the steps of providing a substrate base 301; a first metal layer 302 is deposited on the surface of the substrate, and the metal layer is patterned to form a light shielding layer of the thin film transistor and a first electrode of each storage capacitor. A buffer layer 303 is formed on the surface of the first metal layer, and a recess 320 is formed on a side of the buffer layer away from the substrate, as shown in fig. 8A, and the depth and size of the recess are configured to accommodate the active layer, the gate insulating layer, and the gate electrode. An IGZO active layer 311 and a gate insulating layer 312 are conformally formed on the buffer layer surface, the gate insulating layer surface having a recess 320 for accommodating a gate electrode, as shown in fig. 8B. Forming a gate in the recess; and etching the gate insulating layer to expose the surface of the active layer outside the groove. The steps for preparing the display panel of the second embodiment are similar to those of fig. 6C-6F and related descriptions, and are not repeated here for brevity.

Fig. 9 is a schematic cross-sectional structure of a display panel 400 according to a third embodiment of the present utility model. Unlike the first embodiment shown in fig. 3, the circuit structure of the third embodiment is provided with a conductive metal oxide layer, such as an ITO layer, between a metal layer and a buffer layer, which together constitute a first conductive structure layer provided on the surface of a substrate. Specifically, the display panel 400 includes a substrate base 401, a first metal layer 402 disposed on the substrate base, a conductive metal oxide ITO layer 442 disposed on the first metal layer, and a buffer layer 403 disposed on the conductive metal oxide layer. The substrate 401 may be a glass substrate with grooves 420 formed therein, the depth and size of the grooves being configured to receive the gate electrode and the associated layers between the gate electrode and the glass substrate. The first metal layer 402 is provided on a surface of the substrate 401 on a side having a groove, and a portion on the groove conforms to the groove to maintain a groove shape for accommodating the gate electrode. The ITO layer 442 is disposed on a surface of the metal layer 402 on a side having a groove, and a portion on the groove conforms to the groove to maintain a groove shape for accommodating the gate electrode. As one embodiment, the ITO layer covers the orthographic projection of the first metal layer on the surface of the substrate; as another embodiment, the orthographic projection of the ITO layer on the substrate surface covers at least the orthographic projection of the groove on the substrate surface. The buffer layer 403 is disposed on a surface of the ITO layer 442 having a groove side, and a portion on the groove conforms to the groove to maintain a groove shape for accommodating the gate electrode. The conductive metal oxide layer in this embodiment is used to provide protection for the first metal layer disposed below the conductive metal oxide layer, so that the metal layer is prevented from being corroded in the buffer layer opening process, the shading effect of the metal layer on the thin film transistor formed on the metal layer is affected, and the electrical performance of the metal layer serving as the first electrode of the storage capacitor is damaged. The display panel 400 further includes an active layer 411 disposed on a surface of the buffer layer having a groove, a portion of the active layer on the groove conforming to the groove, maintaining a groove shape for accommodating the gate electrode; a gate insulating layer 412 disposed within and conformally with the recess of the active layer 411; and a gate electrode 413 disposed in the groove of the gate insulating layer 412. The active layer 411, the gate electrode 413, and the gate insulating layer 412 therebetween constitute a thin film transistor TFT. As shown, the surface of the gate, the exposed surface of the active layer outside the recess, and the exposed surface of the gate insulating layer between the gate and active layers are substantially flush. Other circuit structures of the display panel 400 are similar to those of the first and second embodiments, and are not described here again for brevity.

It will be appreciated by those skilled in the art that the first conductive structure layer structure provided between the substrate base and the buffer layer in the present embodiment may be used in combination with the second embodiment.

The method of manufacturing the display panel 400 according to the third embodiment of the present utility model includes the steps of providing a substrate, such as a glass substrate 401, forming a groove 420 on one side of the substrate, forming a first conductive structure layer on a surface of the substrate having the groove, and forming a portion of the first conductive structure layer on the groove of the substrate to conform to the groove of the substrate. The first conductive structure includes a first metal layer 402 on the substrate base and an ITO layer 442 on the first metal layer. As one embodiment, the step of forming the first conductive structure layer includes forming a first metal layer conformally with the substrate on a surface of the substrate having the grooves, and forming an ITO layer conformally with the first metal layer on the first metal layer. Patterning the ITO layer and the first metal layer to obtain orthographic projection of the first conductive metal oxide layer in the first conductive structure layer on the surface of the substrate, wherein orthographic projection of the metal layer on the surface of the substrate is covered. As another embodiment, the step of forming the first conductive structure layer includes forming a first metal layer on the surface of the substrate having the grooves, patterning the first metal layer to form a metal layer having grooves conformal with the grooves on the substrate, functioning as a light shielding layer of the thin film transistor, and a first electrode of the storage capacitor. An ITO layer is formed on the patterned first metal layer. Patterning the ITO layer, wherein the orthographic projection of the patterned ITO layer on the surface of the substrate covers the orthographic projection of the first metal layer on the surface of the substrate, or the orthographic projection of the patterned ITO layer on the surface of the substrate at least covers the orthographic projection of the groove on the surface of the substrate. And the ITO layer is used for covering the first metal layer, so that the problem that the patterned metal layer is broken or thinned due to excessive etching in the subsequent step of patterning the buffer layer is avoided, and the problem of bad dark spots is solved.

A buffer layer is formed on the resulting structure surface, forming a buffer layer 403, the portion of which on the recess is conformal with the recess in the first conductive structure layer. The IGZO active layer 311 and the gate insulating layer 312 are conformally formed on the buffer layer surface, and the gate insulating layer surface has a groove 420 for accommodating the gate electrode. Forming a gate in the recess; and etching the gate insulating layer to expose the surface of the active layer outside the groove. The steps for preparing the display panel of the third embodiment are similar to those of fig. 6C-6F and related descriptions, and are not repeated here for brevity.

A fourth embodiment of the present utility model provides a display device including the display panel described above. As one embodiment, the present utility model provides a flexible display device including the flexible display panel as described above.

It should be understood that the foregoing examples of the present utility model are provided merely for clearly illustrating the present utility model and are not intended to limit the embodiments of the present utility model, and that various other changes and modifications may be made therein by one skilled in the art without departing from the spirit and scope of the present utility model as defined by the appended claims.

Claims (13)

1. A display substrate is characterized by comprising

A substrate base;

the buffer layer is arranged on the substrate, and a groove is formed in one side, away from the substrate, of the buffer layer;

an active layer disposed on the buffer layer, a portion of the active layer on the recess conforming to a surface of the buffer layer;

the grid electrode is arranged in the groove and is positioned at one side of the active layer away from the substrate; and

and the gate insulating layer is arranged in the groove and positioned between the active layer and the gate.

2. The display substrate according to claim 1, wherein a groove is formed in a side of the substrate adjacent to the buffer layer, and a portion of the buffer layer on the groove of the substrate conforms to a surface of the substrate.

3. A display substrate according to claim 1 or 2, characterized in that the gate surface, the surface of the active layer outside the recess area, and the surface of the gate insulation layer between the gate and the active layer in a direction parallel to the substrate are substantially flush.

4. The display substrate according to claim 1 or 2, further comprising a first conductive structure layer disposed between the substrate surface and the buffer layer, the first conductive structure layer being a first metal layer or the first conductive structure layer comprising a first metal layer disposed on the substrate surface and a first conductive metal oxide layer disposed on the first metal layer.

5. The display substrate of claim 2, further comprising a first conductive structure layer disposed between the substrate surface and the buffer layer, the first conductive structure layer comprising a first metal layer disposed on the substrate surface and a first conductive metal oxide layer disposed on the first metal layer, an orthographic projection of the first conductive metal oxide layer on the substrate surface covering an orthographic projection of the recess on the substrate surface.

6. The display substrate according to claim 1 or 2, further comprising an interlayer insulating layer covering the gate surface, the gate insulating layer surface, and the active layer surface, the interlayer insulating layer having a flat surface on a side remote from the substrate.

7. The display substrate according to claim 6, further comprising a source-drain electrode layer having a flat structure provided on a surface of the interlayer insulating layer, the source-drain electrode layer being electrically connected to the active layer through a via penetrating the interlayer insulating layer.

8. The display substrate of claim 7, wherein an orthographic projection of the source-drain electrode layer on the substrate at least partially overlaps an orthographic projection of the gate electrode on the substrate.

9. The display substrate of claim 7, wherein a height difference between the gate surface and the active layer surface is less than a thickness of a source drain electrode layer.

10. The display substrate of claim 7, further comprising

A passivation layer disposed on the exposed surface of the interlayer insulating layer and the source and drain electrode layer;

a second insulating layer disposed on a surface of the passivation layer on a side remote from the substrate base plate; and

and a first electrode disposed on a surface of the second insulating layer, the first electrode being electrically connected to the source-drain electrode layer through an opening region penetrating the second insulating layer and the passivation layer.

11. The display substrate of claim 10, wherein an orthographic projection of the recess on a substrate surface does not overlap with an orthographic projection of the opening region on the substrate surface.

12. The display substrate of claim 10, wherein an orthographic projection of the opening region on the substrate covers an orthographic projection of the interlayer insulating layer via on a surface of the substrate.

13. A display device comprising a display substrate according to any one of claims 1-12.