CN219627736U - Serial port test circuit based on FPGA - Google Patents
Serial port test circuit based on FPGA Download PDFInfo
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- CN219627736U CN219627736U CN202320478037.XU CN202320478037U CN219627736U CN 219627736 U CN219627736 U CN 219627736U CN 202320478037 U CN202320478037 U CN 202320478037U CN 219627736 U CN219627736 U CN 219627736U
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- 238000012360 testing method Methods 0.000 title claims abstract description 28
- 238000006243 chemical reaction Methods 0.000 claims abstract description 50
- 238000004891 communication Methods 0.000 claims abstract description 32
- 230000008054 signal transmission Effects 0.000 claims description 3
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- 239000003990 capacitor Substances 0.000 description 2
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A serial port test circuit based on FPGA comprises an FPGA module and a conversion circuit; the conversion circuit comprises two paths of signal conversion units, is connected with different FIFO interfaces of the FPGA module and is respectively used for being connected with different serial port communication interfaces of the tested board card; the FPGA module is used for communicating with the upper computer through an instruction interface thereof to acquire a control instruction, generating a TTL pulse signal, sending the TTL pulse signal from one of the FIFO interfaces, and converting the TTL pulse signal received by one signal conversion unit into a differential signal of an RS485 serial port communication physical layer standard and transmitting the differential signal to a corresponding serial port communication interface of a board to be tested; the signal conversion unit is used for converting the differential signals output by the serial port communication interface of the tested board card into TTL pulse signals and providing the TTL pulse signals to the FIFO interface of the FPGA module. The method is applied to performance and function test of the board card, and two paths of RS485 serial ports with 5Mbps are realized.
Description
Technical Field
The utility model belongs to the technical field of board card testing, and relates to a serial port testing circuit based on an FPGA.
Background
In the production process of the board card of the nuclear power control system, the performance and the function test of the board card are indispensable production and inspection links. The test method generally comprises the steps of giving an external signal to a test tool, establishing communication with the external signal through a board card interface to perform data interaction, and analyzing to obtain a reply message to confirm the response of the board card to the given signal.
Because the special requirement control system of the nuclear industry has high-speed response capability to instructions and signals, the communication bus of the board card of the nuclear power control system is generally subjected to custom development on the basis of a general standard interface and a protocol, so that the special requirements of high speed, privacy and the like are met. Currently, the universal standard interface and protocol test tools on the market are often not suitable for testing the custom protocols, and need to be improved.
Disclosure of Invention
In order to solve the defects in the prior art, the utility model provides a serial port test circuit based on an FPGA, which is applied to performance and function test of a board card, realizes two paths of RS485 serial port communication with 5Mbps, and is particularly suitable for being applied to a nuclear power control system.
In order to achieve the above object, the present utility model adopts the following technique:
a serial port test circuit based on FPGA comprises an FPGA module and a conversion circuit;
the conversion circuit comprises two paths of signal conversion units which are respectively connected with different FIFO interfaces of the FPGA module and are respectively used for being connected with different serial port communication interfaces of the tested board card;
the FPGA module is used for communicating with the upper computer through an instruction interface thereof so as to acquire a control instruction;
the FPGA module is used for generating TTL pulse signals and sending out the TTL pulse signals from one of the FIFO interfaces, and one path of signal conversion unit corresponding to the received TTL pulse signals is used for converting the TTL pulse signals into differential signals of an RS485 serial port communication physical layer standard and transmitting the differential signals to the corresponding serial port communication interface of the tested board card;
the signal conversion unit is also used for converting the differential signals output by the serial port communication interface of the tested board card into TTL pulse signals and providing the TTL pulse signals to the FIFO interface of the FPGA module.
The FPGA module is used for generating TTL pulse signals according to the control instructions.
The FPGA module is used for converting TTL pulse signals received from the FIFO interface into data which can be identified by the upper computer and transmitting the data to the upper computer through the instruction interface.
The signal conversion units of the conversion circuit all adopt an RS-485 interface transceiver, such as MAX3491ESD+.
For each path of signal conversion unit, a RO pin of MAX3491ESD+ is connected with +3.3V through a resistor and is used as a TTL pulse signal input end, a DI pin is used as a TTL pulse signal output end, and the RO pin and the DI pin are connected with a FIFO interface of an FPGA module; pin A of MAX3491ESD+ is connected with +3.3V through a resistor, pin B is connected with GND through a resistor, pin A and pin B are connected with serial port communication interface of tested board card, which is used for realizing differential signal transmission. MAX3491esd+ pin/RE and DE pin connect DIO interface of FPGA module. Two VCC pins of MAX3491ESD+ are connected, and are connected with +3.3V and one end of two capacitors, and the other end of the two capacitors is connected, and is connected with GND; two GND pins of MAX3491ESD+ are connected and connected with GND; MAX3491ESD+ Z pin is connected with A pin, Y pin is connected with B pin; MAX3491esd+ two NC pins are suspended.
The utility model has the beneficial effects that: the method is applied to performance and function test of the board card, realizes two paths of RS485 serial port communication with 5Mbps through simple circuit structure and RS485 interface chip selection, and is particularly suitable for being applied to a nuclear power control system.
Drawings
FIG. 1 is a schematic block diagram of a test circuit according to an embodiment of the utility model.
Fig. 2 is a circuit example of a conversion circuit of an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the following detailed description of the embodiments of the present utility model will be given with reference to the accompanying drawings, but the described embodiments of the present utility model are some, but not all embodiments of the present utility model.
The embodiment of the utility model provides a serial port test circuit based on an FPGA, which comprises an FPGA module and a conversion circuit as shown in figure 1.
The conversion circuit comprises two paths of signal conversion units which are respectively connected with different FIFO interfaces of the FPGA module and are respectively connected with different serial port communication interfaces of the tested board card. The signal conversion units of the conversion circuit all adopt RS-485 interface transceivers.
Specifically, as shown in fig. 1, the conversion circuit comprises a signal conversion unit a and a signal conversion unit B, the FIFO interface of the FPGA module comprises a FIFO interface a and a FIFO interface B, the tested board card is provided with a serial port communication interface a and a serial port communication interface B, the FIFO interface a is connected with the signal conversion unit a, and the signal conversion unit a is connected with the serial port communication interface a; the FIFO interface B is connected with the signal conversion unit B, and the signal conversion unit B is connected with the serial port communication interface B.
The FPGA module is used for communicating with the upper computer through an instruction interface thereof to acquire a control instruction or transmitting data/information to the upper computer; specifically, the instruction interface may take the form of a USB.
In this example, the FIFO interface a includes an output end of the FIFO interface a and an input end of the FIFO interface a, the FPGA module receives a control instruction from the upper computer through the instruction interface, generates a TTL pulse signal and sends out the TTL pulse signal from the output end of the FIFO interface a, and the signal conversion unit a receives the TTL pulse signal and converts the TTL pulse signal into a differential signal of the RS485 serial port physical layer, and sends out the differential signal, and transmits the differential signal to the board card to be tested through the serial port communication interface a. The signal conversion unit A can receive the differential signal sent by the tested board card through the serial port communication interface A, convert the differential signal into a TTL pulse signal, then provide the TTL pulse signal for the input end of the FIFO interface A, and the FPGA module converts the received TTL pulse signal into data identifiable by an upper computer and transmits the data to the upper computer through the instruction interface.
Similarly, the FIFO interface B includes an output end of the FIFO interface B and an input end of the FIFO interface B, and the working manner is similar to that of the FIFO interface a, which is not described again.
As an example of a more specific implementation circuit of the conversion circuit, as shown in fig. 2, MAX3491esd+ is used for the signal conversion units.
With an example of a signal conversion unit, in fig. 2, U14 is MAX3491esd+, whose RO pin is connected to +3.3v through a resistor R190 and is used as a TTL pulse signal input end, DI pin is used as a TTL pulse signal output end, and the RO pin and DI pin are connected to a FIFO interface a of the FPGA module; specifically, the RO pin is connected to the input end of the FIFO interface A, and the DI pin is connected to the output end of the FIFO interface A.
MAX3491ESD+ pin A is connected +3.3V through resistance R191, and pin B is connected GND through resistance R192, and serial communication interface A of test card is connected to pin A and pin B for realize differential signal transmission.
MAX3491esd+ pin/RE and DE pin connect DIO interface of FPGA module. The RE pin and the DE pin are used for controlling MAX3491ESD+ to be in a transmitting mode or a receiving mode, and specifically the MAX3491ESD+ realizes the output TTL pulse signal of the RO pin or the receiving TTL pulse signal of the DI pin according to the high-low level control signal.
Two VCC pins of MAX3491ESD+ are connected, and connect +3.3V, electric capacity C38, electric capacity C39 one end, electric capacity C38, electric capacity C39 other end are connected, and connect GND. Two GND pins of MAX3491esd+ are connected and GND is connected. MAX3491ESD+ Z pin is connected with A pin, Y pin is connected with B pin; MAX3491esd+ two NC pins are suspended.
In fig. 2, another signal conversion unit is also implemented by MAX3491esd+ and is not described again.
Through adopting MAX3491ESD+ to build the conversion circuit, realize two-way 5 Mbps's RS485 serial port communication.
Through test verification, the test circuit of the embodiment is simple and convenient to operate, suitable for performance and function tests of all types of boards of a nuclear power control system, high in communication rate, strong in universality and convenient to maintain.
The above description is only of the preferred embodiments of the present utility model and is not intended to limit the utility model, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present utility model without departing from the spirit and scope of the utility model.
Claims (8)
1. The serial port test circuit based on the FPGA is characterized by comprising an FPGA module and a conversion circuit;
the conversion circuit comprises two paths of signal conversion units which are respectively connected with different FIFO interfaces of the FPGA module and are respectively used for being connected with different serial port communication interfaces of the tested board card;
the FPGA module is used for communicating with the upper computer through an instruction interface thereof so as to acquire a control instruction;
the FPGA module is used for generating TTL pulse signals and sending out the TTL pulse signals from one of the FIFO interfaces, and one path of signal conversion unit corresponding to the received TTL pulse signals is used for converting the TTL pulse signals into differential signals of an RS485 serial port communication physical layer standard and transmitting the differential signals to the corresponding serial port communication interface of the tested board card;
the signal conversion unit is also used for converting the differential signals output by the serial port communication interface of the tested board card into TTL pulse signals and providing the TTL pulse signals to the FIFO interface of the FPGA module.
2. The FPGA-based serial port test circuit of claim 1, wherein the FPGA module is configured to control the instruction to generate the TTL pulse signal.
3. The FPGA-based serial port test circuit of claim 1, wherein the FPGA module is configured to convert TTL pulse signals received from the FIFO interface into data recognizable by the host computer, and transmit the data to the host computer through the instruction interface.
4. The FPGA-based serial port test circuit according to claim 1, wherein the conversion circuit comprises a signal conversion unit A and a signal conversion unit B, the FIFO interface of the FPGA module comprises a FIFO interface A and a FIFO interface B, the serial port communication interface A and the serial port communication interface B are arranged on the tested board card,
the FIFO interface A is connected with the signal conversion unit A, and the signal conversion unit A is connected with the serial port communication interface A;
the FIFO interface B is connected with the signal conversion unit B, and the signal conversion unit B is connected with the serial port communication interface B.
5. The FPGA-based serial port test circuit of claim 1, wherein the signal conversion units of the conversion circuit each employ an RS-485 interface transceiver.
6. The FPGA based serial port test circuit of claim 5, wherein the signal conversion units of the conversion circuit all employ MAX3491esd+.
7. The FPGA based serial port test circuit of claim 6, wherein for each signal conversion unit, the MAX3491esd+ RO pin is connected to +3.3v through a resistor and is used as a TTL pulse signal input terminal, the DI pin is used as a TTL pulse signal output terminal, and the RO pin and the DI pin are connected to the FIFO interface of the FPGA module;
pin A of MAX3491ESD+ is connected with +3.3V through a resistor, pin B is connected with GND through a resistor, pin A and pin B are connected with serial port communication interface of tested board card, which is used for realizing differential signal transmission.
8. The FPGA based serial port test circuit of claim 7, wherein MAX3491esd+ pin/RE and DE pin connect DIO interfaces of the FPGA module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320478037.XU CN219627736U (en) | 2023-03-14 | 2023-03-14 | Serial port test circuit based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320478037.XU CN219627736U (en) | 2023-03-14 | 2023-03-14 | Serial port test circuit based on FPGA |
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| Publication Number | Publication Date |
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| CN219627736U true CN219627736U (en) | 2023-09-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202320478037.XU Active CN219627736U (en) | 2023-03-14 | 2023-03-14 | Serial port test circuit based on FPGA |
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| CN (1) | CN219627736U (en) |
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2023
- 2023-03-14 CN CN202320478037.XU patent/CN219627736U/en active Active
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