CN219611746U

CN219611746U - Peak hold circuit

Info

Publication number: CN219611746U
Application number: CN202320083283.5U
Authority: CN
Inventors: 张卫星; 王政; 张钊
Original assignee: Beijing Judian Weilai Technology Co ltd
Current assignee: Beijing Judian Weilai Technology Co ltd
Priority date: 2023-01-13
Filing date: 2023-01-13
Publication date: 2023-08-29
Anticipated expiration: 2033-01-13

Abstract

The present utility model provides a peak hold circuit including: the system comprises a signal acquisition input module, a signal screening module, a peak searching and holding module, a main control module and an analog electronic switch module; the signal screening module, the main control module, the analog electronic switch module and the peak value holding module are connected in sequence; the signal screening module screens the input pulse signals; the peak searching and peak holding module performs peak value acquisition on the acquired pulse signals and holds the acquired pulse signals according to preset time after the peak signals are acquired; the main control module starts the analog electronic switch module. The signal that signal acquisition module gathered is through signal screening module, screens out effective signal and generates the pulse signal of effective signal width to main control module, and the signal that gathers is input to seek peak value and peak value keeps the module and look for the peak value to the signal simultaneously, seeks the peak value in effective signal width, opens analog electronic switch module after finding the peak value by main control module, keeps the peak value.

Description

Peak hold circuit

Technical Field

The embodiment of the utility model relates to the technical field of data acquisition, in particular to a peak hold circuit.

Background

Logging technology is a very commonly used technical means in the petroleum exploration field, and combines an electronic technology and a computer technology together in various modes such as electricity, acoustics, radiology and the like to acquire various physical parameters of a stratum, and further acquires oil and gas information through data analysis.

In neutron logging, an americium-beryllium neutron source and a neutron generator are generally adopted as excitation sources to react with a stratum to obtain returned gamma rays, a high-energy ray detector is further used for detecting the returned gamma ray information, and corresponding stratum information can be obtained through further data analysis. Generally, gamma ray detectors use scintillation crystal detectors. In order to convert gamma rays into electrical signals which are convenient to analyze and process, a scintillation crystal is generally adopted to convert gamma rays into visible light, a photomultiplier is adopted to convert the visible light into the electrical signals, and then the electrical signals are sampled and analyzed. Common scintillation crystals include scintillation crystals such as cesium iodide and sodium iodide, and common photomultiplier tubes include photomultiplier tubes and silicon photomultiplier tubes.

The scintillation crystals of the prior art are capable of detection at low gamma ray dose rates, but are difficult to perform at high gamma ray dose rates. In neutron petroleum logging applications, it is necessary to analyze the ray energy spectrum and the count spectrum in a short time after neutron emission, and it is necessary to digitize and analyze the radiation pulse signal at a high speed. The traditional common digitizing methods are two, the first is a method of directly digitizing an electric pulse signal by a high-speed ADC, the method of shaping and stretching the electric pulse signal is needed, and then the method of directly digitizing the electric pulse signal by the high-speed ADC is needed, and the method of shaping and stretching the electric pulse signal is needed, and then the method of digitally sampling by the high-speed ADC is needed. Digitizing a pulse in engineering practice requires at least 20 sampling points to be acquired to obtain relatively accurate energy information, while the sampling performance of the ADC chip at high temperature (175C) is typically not very high and is very costly. Therefore, the digitization of the high-speed scintillation crystal pulse signal cannot be completed, so that the high-speed scintillation crystal pulse signal is difficult to apply to the petroleum logging technology; the second is a peak hold method, which uses a peak hold circuit to lock the amplitude of an electric pulse signal and then uses an ADC to collect the amplitude to obtain pulse energy information, and although the peak hold method can process the pulse of a high-speed scintillation crystal, the dead time of the peak hold method is long and usually reaches several hundred microseconds due to the peak hold lock establishment and peak hold circuit recovery process, which greatly limits the pulse passing rate (the number of processed pulses in unit time) of a digitizing part, in petroleum logging, the number of pulse events often increases in bursts, in common neutron petroleum logging, the number of pulses reaches 100k CPS, one pulse is generated every 10us on average, and if all the generated pulses are regarded as effective pulses, the dead time of the peak hold method is too short and the digitizing process loses a lot of effective pulse signals, thereby causing measurement result deviation.

Disclosure of Invention

In order to more accurately count the number of generated pulses and reduce the problem of inaccurate measurement results caused by data loss due to dead time of peak hold, the embodiment of the utility model provides a peak hold circuit, which is provided with a signal screening module for carrying out preliminary screening on all input pulse signals and filtering non-effective pulse signals so as to improve the efficiency of effective signal acquisition and reduce the problem of data loss caused by too short dead time of a peak hold method. In addition, the peak searching and peak holding module is provided with a plurality of groups of voltage stabilizing diodes which are mutually connected in series, and the voltage stabilizing diodes connected in series reduce the size of junction capacitance and reduce the influence of capacitance voltage division on charging capacitance; meanwhile, as the peak burr of the tip of the capacitor C9 occurs in a very short time in the discharging process, the burr is amplified by the pin 3 of the signal amplifying chip U3, so that the accuracy of the collected peak signal collection can be affected. The specific technical scheme is as follows:

the peak hold circuit provided by the embodiment of the utility model comprises: the system comprises a signal acquisition input module, a signal screening module, a peak searching and holding module, a main control module and an analog electronic switch module; the signal acquisition input module is respectively connected with the signal screening module and the peak searching and holding module; the signal screening module, the main control module, the analog electronic switch module and the peak value holding module are connected in sequence; the signal screening module is used for screening the input pulse signals; the peak searching and peak holding module is used for carrying out peak value acquisition on the acquired pulse signals and holding the acquired pulse signals according to preset time after the peak signals are acquired; the main control module is used for starting the analog electronic switch module.

Further, the signal screening module includes: a threshold circuit and a pulse detection circuit connected to each other; the threshold circuit is used for generating a threshold voltage signal with a preset voltage value, and the pulse detection circuit is used for outputting a high level when detecting that the input pulse signal is larger than the threshold voltage signal.

Further, the threshold circuit includes: the resistor R23, the capacitor C19 and the resistor R24 are connected in parallel, one end of the resistor R23 is connected with the power supply VCC3V3, and the other end of the resistor R23 is connected with the capacitor C19; the pulse detection circuit includes: comparator U5, resistor R17, resistor R21, resistor R22, and capacitor C16; the pin 2 and the pin 6 of the comparator U5 are connected with the analog ground AGND, the pin 4 of the comparator U5 is connected with the power supply VCC3V3, one end of the capacitor C16 is connected with the power supply VCC3V3, and the other end of the capacitor C is connected with the analog ground AGND; one end of the resistor R22 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the analog ground AGND; one end of the resistor R21 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the main control module; the threshold circuit is connected with the comparator U5 through a pin 1 of the comparator U5.

Further, the peak finding and peak holding module includes: the signal amplifying chip U3, the resistor R2, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R12, the resistor R15 and the resistor R73; capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11 and capacitor C12, zener diode; a pin 13 of the signal amplification chip U3 is connected with a +5V power supply, and a capacitor C6, a capacitor C7 and a capacitor C8 are connected in parallel between the +5V power supply and the analog ground AGND; one end of the resistor R9 is connected with the pin 1 of the signal amplification chip U3, and the other end of the resistor R9 is connected with a power supply-5V; the pin 5 of the signal amplification chip U3 is connected with the power supply-5V, and a capacitor C10, a capacitor C11 and a capacitor C12 are connected between the power supply-5V and the analog ground; the pin 4 of the signal amplification chip U3 is connected with the zener diode in series in the forward direction, one end of the resistor R10 is connected with the pin 3 of the signal amplification chip U3, and the other end of the resistor R8 is connected with the resistor R8; one end of the resistor R8 is connected with the resistor R9, and the other end of the resistor R8 is connected with the reverse end of the zener diode; one end of the resistor R2 is connected with the pin 11 of the signal amplification chip U3, and the other end of the resistor R2 is connected with the pin 2 of the signal amplification chip U3; one end of the resistor R7 is connected with the capacitor C9, and the other end is connected with the resistor R8.

Further, the analog electronic switch module includes: analog switch chip U2, resistor R4, capacitor C1; one end of the resistor R4 is connected with the pin 1 of the analog switch chip U2, and the other end of the resistor R is connected with the PEAK_RST pin of the main control module; one end of the capacitor C1 is connected with the analog ground AGND, the other end of the capacitor C is connected with the pin 8 of the analog switch chip U2, and the pin 6, the pin 7, the pin 2, the pin 3 and the pin 5 of the analog switch chip U2 are connected with the analog ground AGND; the pin 10 of the analog switch chip U2 is connected between the resistor R7 and the capacitor C9.

Further, the zener diodes are in a plurality of groups, and include: a zener diode D1, a zener diode D2, and a zener diode D3 connected in series; one end of the resistor R8 is connected between the zener diode D1 and the zener diode D2, and the other end is connected with the resistor R10.

Further, the signal acquisition input module includes: the signal sensor, the input filter circuit and the sampling resistor R12 are connected in sequence; the input filter circuit comprises a resistor R14 and a capacitor C13; the resistor R14 and the capacitor C13 are connected in parallel.

Further, one end of the resistor R7 is connected with the reverse end of the D1, and the other end of the resistor R7 is connected to the capacitor C9; the resistance value of the resistor R7 is 10 ohms.

The peak hold circuit provided by the embodiment of the utility model comprises: the system comprises a signal acquisition input module, a signal screening module, a peak searching and holding module, a main control module and an analog electronic switch module; the signal acquisition input module is respectively connected with the signal screening module and the peak searching and holding module; the signal screening module, the main control module, the analog electronic switch module and the peak value holding module are connected in sequence; the signal screening module is used for screening the input pulse signals; the peak searching and peak holding module is used for carrying out peak value acquisition on the acquired pulse signals and holding the acquired pulse signals according to preset time after the peak signals are acquired; the main control module is used for starting the analog electronic switch module. The signal that signal acquisition input module gathered is through signal screening module, screens out effective signal and generates the pulse signal of effective signal width to main control module, and the signal that gathers is input to seek peak value and peak value keeps the module and carries out peak value to the signal and seek, seeks the peak value in effective signal width, opens analog electronic switch module after seeking the peak value by main control module, keeps the peak value. The embodiment of the utility model provides a peak value holding circuit, which is provided with a signal screening module for primarily screening all input pulse signals, filtering non-effective pulse signals, improving the efficiency of effective signal acquisition and reducing the problem of data loss generated by dead time of a peak value holding method.

Furthermore, the peak searching and peak holding module is provided with a plurality of groups of voltage stabilizing diodes which are connected in series, the size of junction capacitance is reduced by the plurality of groups of voltage stabilizing diodes which are connected in series, and the influence of capacitance voltage division on charging capacitance is reduced.

Furthermore, as the peak burr of the tip of the capacitor C9 occurs in a very short time in the discharging process, the burr is amplified by the pin 3 of the signal amplifying chip U3 and can affect the collected peak signal, one end of the resistor R7 is connected with the reverse end of the D1, and the other end of the resistor R7 is connected with the capacitor C9; the resistance value of the resistor R7 is 10 ohms so as to level burrs and improve the accuracy of peak detection.

Drawings

FIG. 1 is a schematic block diagram of a peak hold circuit provided in an embodiment of the present utility model;

fig. 2 is a schematic circuit diagram of a signal screening module of a peak hold circuit according to an embodiment of the present utility model;

FIG. 3 is a schematic circuit diagram of a peak and peak hold module of a peak hold circuit according to an embodiment of the present utility model;

fig. 4 is a schematic diagram of an analog electronic switch module of a peak hold circuit according to an embodiment of the present utility model.

Detailed Description

The following description of the technical solutions in the embodiments of the present utility model will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present utility model, but not all embodiments. All other embodiments, based on the embodiments of the utility model, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the utility model.

Fig. 1 is a schematic block diagram of a peak hold circuit according to an embodiment of the present utility model, including: the system comprises a signal acquisition input module, a signal screening module, a peak searching and holding module, a main control module and an analog electronic switch module; the signal acquisition input module is respectively connected with the signal screening module and the peak searching and holding module; the signal screening module, the main control module, the analog electronic switch module and the peak value holding module are connected in sequence; the signal screening module is used for screening the input pulse signals; the peak searching and peak holding module is used for carrying out peak value acquisition on the acquired pulse signals and holding the acquired pulse signals according to preset time after the peak signals are acquired; the main control module is used for starting the analog electronic switch module. The signals collected by the signal collection input module are filtered out through the signal screening module, pulse signals with effective signal width are generated and sent to the main control module, meanwhile, the collected signals are input to the peak searching and peak holding module to search peaks of the signals, the peaks are found out in the effective signal width, and the main control module starts the analog electronic switch module after the peaks are found out, so that the peaks are held. The embodiment of the utility model provides a peak value holding circuit, which is provided with a signal screening module for primarily screening all input pulse signals, filtering non-effective pulse signals, improving the efficiency of effective signal acquisition and reducing the problem of data loss generated by dead time of a peak value holding method.

Referring to fig. 2, fig. 2 is a schematic circuit diagram of a signal screening module of a peak hold circuit according to an embodiment of the present utility model, and specifically, the signal screening module includes a threshold circuit and a pulse detection circuit that are connected to each other; the threshold detection circuit is used for generating a threshold voltage signal with a preset voltage value, and the pulse detection circuit is used for outputting a high level when detecting that the input pulse signal is larger than the threshold voltage signal. The threshold circuit includes: the resistor R23, the capacitor C19 and the resistor R24 are connected in parallel, one end of the resistor R23 is connected with the power supply VCC3V3, and the other end of the resistor R23 is connected with the capacitor C19; the pulse detection circuit includes: comparator U5, resistor R17, resistor R21, resistor R22, and capacitor C16; the pin 2 and the pin 6 of the comparator U5 are connected with the analog ground AGND, the pin 4 of the comparator U5 is connected with the power supply VCC3V3, one end of the capacitor C16 is connected with the power supply VCC3V3, and the other end of the capacitor C is connected with the analog ground AGND; one end of the resistor R22 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the analog ground AGND; one end of the resistor R21 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the main control module; the threshold circuit is connected with the comparator U5 through a pin 1 of the comparator U5.

When an input signal is detected, the input signal is input to the forward input end of the comparator U5 through the low-pass filter, the reverse input end is input with a threshold value with a preset size, and when the size of the input signal is higher than the threshold value, the output end of the comparator outputs high-level pulses and inputs the high-level pulses to the main control module. At the same time, the peak value of the input signal is detected and maintained during the active time of the high level pulse, see fig. 3 below.

Fig. 3 is a schematic circuit diagram of a peak searching and peak holding module of a peak holding circuit according to an embodiment of the present utility model, where the peak searching and peak holding module includes: the signal amplifying chip U3, the resistor R2, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R12, the resistor R15 and the resistor R73; capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11 and capacitor C12, zener diode; a pin 13 of the signal amplification chip U3 is connected with a +5V power supply, and a capacitor C6, a capacitor C7 and a capacitor C8 are connected in parallel between the +5V power supply and the analog ground AGND; one end of the resistor R9 is connected with the pin 1 of the signal amplification chip U3, and the other end of the resistor R9 is connected with a power supply-5V; the pin 5 of the signal amplification chip U3 is connected with the power supply-5V, and a capacitor C10, a capacitor C11 and a capacitor C12 are connected between the power supply-5V and the analog ground; the pin 4 of the signal amplification chip U3 is connected with the zener diode in series in the forward direction, one end of the resistor R10 is connected with the pin 3 of the signal amplification chip U3, and the other end of the resistor R8 is connected with the resistor R8; one end of the resistor R8 is connected with the resistor R9, and the other end of the resistor R8 is connected with the reverse end of the zener diode; one end of the resistor R2 is connected with the pin 11 of the signal amplification chip U3, and the other end of the resistor R2 is connected with the pin 2 of the signal amplification chip U3; one end of the resistor R7 is connected with the capacitor C9, and the other end is connected with the resistor R8.

The input signal enters the amplifying chip from the pin 10 end of the signal amplifying chip U3 for amplifying, and at the moment, the Chold pin of the chip outputs the amplified signal and charges the capacitor C9 through a loop formed by the voltage stabilizing diode, the resistor R7, the capacitor C9 and the pin 5 of the U3; the voltage across C9 gradually increases. Meanwhile, on a loop formed by the pin 3, the resistor R10, the resistor R7 and the capacitor C9 of the chip, the voltage on the pin 3 of the chip gradually rises, when the voltage rises to 0.7V, the pin 2 of the chip is conducted, an output signal is compared with an input signal, and when the output signal is higher than the input signal, the charging of the capacitor C9 is finished; otherwise, C9 is continuously charged until the largest output signal is found in the effective time, and at the moment, the main control module controls the analog electronic switch module to be conducted, and the capacitor C9 is discharged; c9 discharge duration, i.e., peak hold duration.

The voltage stabilizing diodes are in a plurality of groups, and the voltage stabilizing diodes comprise: a zener diode D1, a zener diode D2, and a zener diode D3 connected in series; one end of the resistor R8 is connected between the zener diode D1 and the zener diode D2, and the other end is connected with the resistor R10. The peak searching and peak holding module is provided with a plurality of groups of voltage stabilizing diodes which are connected in series, the size of junction capacitance is reduced by the voltage stabilizing diodes, and the influence of capacitance voltage division on charging capacitance is reduced.

The analog electronic switch module is shown in fig. 4 below, and fig. 4 is a schematic circuit diagram of an analog electronic switch module of a peak hold circuit according to an embodiment of the present utility model, including: analog switch chip U2, resistor R4, capacitor C1; one end of the resistor R4 is connected with the pin 1 of the analog switch chip U2, and the other end of the resistor R is connected with the PEAK_RST pin of the main control module; one end of the capacitor C1 is connected with the analog ground AGND, the other end of the capacitor C is connected with the pin 8 of the analog switch chip U2, and the pin 6, the pin 7, the pin 2, the pin 3 and the pin 5 of the analog switch chip U2 are connected with the analog ground AGND; the pin 10 of the analog switch chip U2 is connected between the resistor R7 and the capacitor C9.

The signal acquisition input module comprises: the signal sensor, the input filter circuit and the sampling resistor R12 are connected in sequence; the input filter circuit comprises a resistor R14 and a capacitor C13; the resistor R14 and the capacitor C13 are connected in parallel. The signal sensor is a gamma probe.

While the utility model has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the utility model and are intended to be within the scope of the utility model as claimed.

Claims

1. A peak hold circuit, comprising: the system comprises a signal acquisition input module, a signal screening module, a peak searching and holding module, a main control module and an analog electronic switch module; the signal acquisition input module is respectively connected with the signal screening module and the peak searching and holding module; the signal screening module, the main control module, the analog electronic switch module and the peak value holding module are connected in sequence; the signal screening module is used for screening the input pulse signals; the peak searching and peak holding module is used for carrying out peak value acquisition on the acquired pulse signals and holding the acquired pulse signals according to preset time after the peak signals are acquired; the main control module is used for starting the analog electronic switch module.

2. The peak hold circuit of claim 1, wherein the signal screening module comprises: a threshold circuit and a pulse detection circuit connected to each other; the threshold circuit is used for outputting a threshold voltage signal with a preset size, and the pulse detection circuit is used for outputting a high level when detecting that an input pulse signal is larger than the threshold voltage signal.

3. The peak hold circuit according to claim 2, wherein the threshold circuit comprises: a resistor R23, a capacitor C19 and a resistor R24 which are connected in parallel, wherein one end of the resistor R23 is connected with a power supply VCC3V3, and the other end is connected with the capacitor C19; the pulse detection circuit includes: comparator U5, resistor R17, resistor R21, resistor R22, and capacitor C16; the pin 2 and the pin 6 of the comparator U5 are connected with the analog ground AGND, the pin 4 of the comparator U5 is connected with the power supply VCC3V3, one end of the capacitor C16 is connected with the power supply VCC3V3, and the other end of the capacitor C is connected with the analog ground AGND; one end of the resistor R22 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the analog ground AGND; one end of the resistor R21 is connected with the pin 5 of the comparator U5, and the other end of the resistor R is connected with the main control module; the threshold circuit is connected with the comparator U5 through a pin 1 of the comparator U5.

4. The peak hold circuit of claim 1, wherein the peak finding and peak holding module comprises: the signal amplifying chip U3, the resistor R2, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R12, the resistor R15 and the resistor R73; capacitor C6, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11 and capacitor C12, zener diode; a pin 13 of the signal amplification chip U3 is connected with a +5V power supply, and a capacitor C6, a capacitor C7 and a capacitor C8 are connected in parallel between the +5V power supply and the analog ground AGND; one end of the resistor R9 is connected with the pin 1 of the signal amplification chip U3, and the other end of the resistor R9 is connected with a power supply-5V; the pin 5 of the signal amplification chip U3 is connected with the power supply-5V, and a capacitor C10, a capacitor C11 and a capacitor C12 are connected between the power supply-5V and the analog ground; the pin 4 of the signal amplification chip U3 is connected with the zener diode in series in the forward direction, one end of the resistor R10 is connected with the pin 3 of the signal amplification chip U3, and the other end of the resistor R8 is connected with the resistor R8; one end of the resistor R8 is connected with the resistor R9, and the other end of the resistor R8 is connected with the reverse end of the zener diode; one end of the resistor R2 is connected with the pin 11 of the signal amplification chip U3, and the other end of the resistor R2 is connected with the pin 2 of the signal amplification chip U3; one end of the resistor R7 is connected with the capacitor C9, and the other end is connected with the resistor R8.

5. The peak hold circuit of claim 4, wherein the analog electronic switch module comprises: analog switch chip U2, resistor R4, capacitor C1; one end of the resistor R4 is connected with the pin 1 of the analog switch chip U2, and the other end of the resistor R is connected with the PEAK_RST pin of the main control module; one end of the capacitor C1 is connected with the analog ground AGND, the other end of the capacitor C is connected with the pin 8 of the analog switch chip U2, and the pin 6, the pin 7, the pin 2, the pin 3 and the pin 5 of the analog switch chip U2 are connected with the analog ground AGND; the pin 10 of the analog switch chip U2 is connected between the resistor R7 and the capacitor C9.

6. The peak hold circuit of claim 4, wherein the zener diodes are in groups comprising: a zener diode D1, a zener diode D2, and a zener diode D3 connected in series; one end of the resistor R8 is connected between the zener diode D1 and the zener diode D2, and the other end is connected with the resistor R10.

7. The peak hold circuit of claim 1, wherein the signal acquisition input module comprises: the signal sensor, the input filter circuit and the sampling resistor R12 are connected in sequence; the input filter circuit comprises a resistor R14 and a capacitor C13; the resistor R14 and the capacitor C13 are connected in parallel.

8. The peak hold circuit according to claim 4, wherein said resistor R7 has one end connected to the opposite end of D1 and the other end connected to said capacitor C9; the resistance value of the resistor R7 is 10 ohms.