CN219577083U - Encoder signal channel selection board card - Google Patents
Encoder signal channel selection board card Download PDFInfo
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- CN219577083U CN219577083U CN202223522687.4U CN202223522687U CN219577083U CN 219577083 U CN219577083 U CN 219577083U CN 202223522687 U CN202223522687 U CN 202223522687U CN 219577083 U CN219577083 U CN 219577083U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model discloses an encoder signal channel selection board card, which at least comprises: the device comprises an encoder signal input interface, a differential-to-single-ended signal chip, a single-ended signal channel selection chip, a single-ended to differential signal chip and an encoder signal output interface. The signal output pin of the signal input interface of the encoder is connected with a differential-to-single-ended signal chip, the output pin of the differential-to-single-ended signal is connected with a single-ended signal channel selection chip, the output pin of the single-ended signal channel selection chip is connected with a single-ended-to-differential signal chip, and the single-ended-to-differential signal is connected with the signal input end of the signal output interface of the encoder. The encoder signal channel selection chip provided by the utility model can selectively output the input multichannel signals into one channel according to actual requirements, is suitable for one-to-many data interaction working conditions, reduces equipment development cost and improves production efficiency.
Description
Technical Field
The utility model relates to the technical field of input and output boards, in particular to a signal channel selection board of an encoder.
Background
In the laser cutting process, the motor position information of the carrier needs to be obtained, and one laser can only receive the motor position information of one carrier at a time. However, in the actual processing process, the motor with a plurality of carriers needs to be cut, and a plurality of lasers are needed to be realized at the moment, so that the single one-to-one use condition is obviously a great increase in production cost for enterprise production. Therefore, a board is needed to send the position information of the plurality of carrier motors to 1 laser, and control the laser to cut the corresponding carrier according to the actual requirement of the user, so that the one-to-many data interaction working condition can be satisfied.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide an encoder signal path selection board card, which solves the above-mentioned problems.
The utility model provides an encoder signal channel selection board card, which at least comprises:
an encoder signal input interface, said encoder signal input interface comprising at least two, each said encoder signal input interface to receive at least one set of first differential signals;
the number of the differential-to-single-ended signal chips is the same as that of the encoder signal input interfaces, each differential-to-single-ended signal chip is electrically connected with differential signal output pins of 1 encoder signal input interface, and each differential-to-single-ended signal chip is used for converting at least one group of first differential signals received by the encoder signal input interface connected with the differential-to-single-ended signal chip into corresponding single-ended signals;
the single-ended signal channel selection chip is electrically connected with the output end of the differential-to-single-ended signal chip and is used for selecting at least one group of single-ended signals converted from first differential signals received by the 1 encoder signal input interfaces;
the single-ended transfer differential signal chip is electrically connected with the output end of the single-ended signal channel selection chip and is used for restoring the selected single-ended signal into a corresponding second differential signal;
the encoder signal output interface is connected with the output end of the single-ended differential signal chip, and the second differential signal is output through the encoder signal output interface.
In an alternative embodiment of the present utility model, the board card further includes an external input interface, the external input interface includes 2 input terminals, each of the input terminals includes 1 first sub-input terminal and 1 second sub-input terminal, an input end of each signal selection input loop is respectively connected with one of the first sub-input terminal and the second sub-input terminal, and an output of the signal selection input loop is changed according to a level of connection of the first sub-input terminal and the second sub-input terminal.
In an optional embodiment of the present utility model, the board card further includes a signal selection control loop, an input end of the signal selection control loop is connected to an external input signal, an output end of the signal selection input loop is electrically connected to a gate control pin of the single-ended signal channel selection chip, and the signal selection input loop is used for controlling channel selection of the single-ended signal channel selection chip.
In an alternative embodiment of the present utility model, the number of signal selection control loops includes 2, each of the signal selection control loops includes a first resistor, a first diode, a photocoupler, a light emitting diode, a first capacitor, and a second resistor, specifically:
the first end of the first resistor is connected with the first sub-input terminal, and the second end of the first resistor is connected with the cathode of the first diode and the first end of the photoelectric coupler;
the anode of the first diode, the cathode of the light emitting diode and the second sub-input terminal are connected; the positive electrode of the light emitting diode is connected with the second end of the photoelectric coupler;
the first end of the second resistor is connected with a power supply VCC;
the fourth end of the photoelectric coupler is connected with the second end of the second resistor and the first end of the first capacitor;
the third end of the photoelectric coupler and the second end of the first capacitor are grounded;
and the fourth end of the photoelectric coupler is used as an output end of the signal selection control loop.
In an alternative embodiment of the present utility model, when the first sub-input terminal is connected to high level and the second sub-input terminal is connected to 0V, the output of the signal selection input loop is a logic value 1, and when the first sub-input terminal is connected to high level and the second sub-input terminal has no power input, the output of the signal selection input loop is a logic value 0.
In an alternative embodiment of the present utility model, the encoder signal strobe board further includes a power circuit, through which an externally input power supplies power to circuitry inside the board.
In an alternative embodiment of the present utility model, the power supply circuit specifically includes:
the power supply connector, the fuse, the second diode, the second capacitor, the third capacitor, the fourth capacitor and the inductor;
the first end of the fuse is connected to the first connection port of the power connector, and the second end of the fuse is connected with the negative electrode of the diode, the positive electrode of the second capacitor, the first end of the third capacitor and the first end of the inductor;
the second end of the inductor and the first end of the fourth capacitor are connected with an internal power supply VCC;
the second connecting port of the power connector is connected with the positive electrode of the second diode, the negative stage of the second capacitor, the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fourth capacitor are grounded.
In an alternative embodiment of the utility model, the board card further comprises an indicator light loop, wherein the indicator light loop is used for displaying the power-on condition of the circuit.
In an alternative embodiment of the present utility model, the single-ended signal path selection chip is model number 74HC153.
In an alternative embodiment of the present utility model, the differential signal voltage value is half the voltage value of the single-ended signal into which the differential signal is converted.
The utility model has the beneficial effects that:
the utility model provides an encoder signal channel selection board card, which comprises encoder signal input interfaces, wherein the encoder signal input interfaces at least comprise two encoder signal input interfaces, and each encoder signal input interface is used for receiving at least one group of first differential signals; then, the output end of the differential-to-single-ended signal chip is connected to a single-ended signal gating chip, and the single-ended signal channel selection chip is used for selecting single-ended signals converted from first differential signals received by the 1 encoder signal input interfaces; connecting the output end of the single-ended signal channel through chip to the signal input end of a single-ended differential signal chip, wherein the single-ended differential signal chip is used for restoring the selected single-ended signal into a corresponding second differential signal; and finally outputting the selected second differential signal through the signal output interface of the encoder. The encoder signal channel selection chip provided by the utility model can selectively output the input multichannel signals into one channel according to actual requirements, is suitable for one-to-many data interaction working conditions, reduces equipment development cost and improves production efficiency.
Drawings
Fig. 1 is a block diagram of an encoder signal path selection board card according to an exemplary embodiment of the present utility model.
Fig. 2 is a circuit diagram of an encoder signal input interface according to an exemplary embodiment of the present utility model.
Fig. 3 is a schematic circuit diagram of a differential to single-segment chip according to an exemplary embodiment of the utility model.
Fig. 4-1 is a schematic circuit diagram of a single-ended signal gating chip U2 according to an exemplary embodiment of the present utility model.
Fig. 4-2 is a schematic circuit diagram of a single-ended signal gating chip U5 according to an exemplary embodiment of the present utility model.
Fig. 5 is a schematic circuit diagram of a signal selection control loop according to an exemplary embodiment of the present utility model.
Fig. 6 is a schematic circuit diagram of a single-to-differential signal chip according to an exemplary embodiment of the utility model.
Fig. 7 is a circuit diagram of an encoder signal output interface according to an exemplary embodiment of the present utility model.
Fig. 8 is a schematic diagram of a power supply circuit inside an encoder signal path selection board card according to an exemplary embodiment of the present utility model.
Detailed Description
Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the illustrations, not according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In view of the above-mentioned problems with the prior art, the present utility model provides an encoder signal path selection board, which at least includes:
an encoder signal input interface, said encoder signal input interface comprising at least two, each said encoder signal input interface to receive at least one set of first differential signals;
the number of the differential-to-single-ended signal chips is the same as that of the encoder signal input interfaces, each differential-to-single-ended signal chip is electrically connected with differential signal output pins of 1 encoder signal input interface, and each differential-to-single-ended signal chip is used for converting at least one group of first differential signals received by the encoder signal input interface connected with the differential-to-single-ended signal chip into corresponding single-ended signals;
the single-ended signal channel selection chip is electrically connected with the output end of the differential-to-single-ended signal chip and is used for selecting at least one group of single-ended signals converted from first differential signals received by the 1 encoder signal input interfaces;
the single-ended transfer differential signal chip is electrically connected with the output end of the single-ended signal channel selection chip and is used for restoring the selected single-ended signal into a corresponding second differential signal;
the encoder signal output interface is connected with the output end of the single-ended differential signal chip, and the second differential signal is output through the encoder signal output interface.
It should be noted that the information contained in the second differential signal and the first signal are the same.
The board card capable of selecting and outputting the input 4-channel signal to the 1-channel signal will now be described as an example:
referring to fig. 1 and 2, in an embodiment of the present utility model, the encoder signal input interfaces include 4, respectively ENC1, ENC2, ENC3 and ENC4, each including 15 pins thereon, and 5 each encoder signal input interface may receive one to four pairs of differential signals, and each encoder signal input interface corresponds to one channel.
Fig. 2 shows a schematic diagram of the encoder signal input interface ENC1 (the structure and circuit connection relationships of ENC2, ENC3, and ENC4 are the same as ENC 1). Referring to fig. 2, in an exemplary embodiment of the present utility model, pin 1, pin 9, pin 4, pin 12, pin 5, pin 13, pin 6 and pin 14 are output pins of the encoder signal input interface, and CH1A and/CH 1A, CH1B and/CH 1B, CH1C and/CH 1C, CH1D and/CH 1D are four pairs of differential signals input to the encoder signal input interface ENC 1. Wherein, the differential signals of CH1A and/CH 1A input to the encoder signal input interface ENC1 are output through the pins 14 and 6 of the encoder signal input interface respectively; the differential signals of the CH1B and/CH 1B input to the encoder signal input interface ENC1 are output through the pins 13 and 5 of the encoder signal input interface respectively; the pair of differential signals of CH1C and/CH 1C input to the encoder signal input interface ENC1 are output through pins 12 and 4 of the encoder signal input interface respectively; the pair of differential signals CH1D and/CH 1D input to the encoder signal input interface ENC1 are output through pins 9 and 1 of the encoder signal input interface, respectively.
Referring to fig. 2, in the present embodiment, pins 3 or 7 of the encoder signal input interface ENC1 are grounded to provide power for an external circuit, and resistors R1 and R17 are used for balancing differential signals, and voltages at two ends of R5 are differential signal voltage differences.
Referring to fig. 1 and 3, in an embodiment of the utility model, the differential to single-ended signal chip includes 4 differential to single-ended signal chips, which are denoted as U1, U4, U6, and U7 respectively. Each differential-to-single-ended chip comprises 8 input pins, namely a No. 2 pin INA+, a No. 1 pin INA-, a No. 14 pin INB+, a No. 15 pin INB-, a No. 6 pin INC+, a No. 7 pin INC-, a No. 10 pin IND+ and a No. 9 pin IND-; the 4 output pins are the No. 3 pin OUTA, the No. 13 pin OUTB, the No. 5 pin OUTC and the No. 11 pin OUTD respectively.
In this embodiment, the differential to single ended signal chip may be a 26C32/SO chip, it being understood that other types of chips may be used in other embodiments.
Referring to fig. 2 and 3, in a specific embodiment, pins ina+ and INA-No. 2 and INA-of the differential-to-single-ended signal chip U1 are respectively connected to pins No. 1 and pin 9 of the encoder signal input interface ENC1, for receiving differential signals CH1D and/CH 1D; the 14 # pin INB+ and the 15 # pin INB-of the differential-to-single-ended signal chip U1 are respectively connected with the 4 # pin and the 12 # pin of the encoder signal input interface ENC1 and are used for receiving differential signals CH1C and/CH 1C; the No. 6 pin INC+ and the No. 7 pin INC-of the differential-to-single-ended signal chip U1 are respectively connected with the No. 4 pin and the No. 12 pin of the encoder signal input interface ENC1 and are used for receiving differential signals CH1C and/CH 1C; the number 10 pin ind+ and the number 9 pin IND-of the differential-to-single-ended signal chip U1 are respectively connected with the number 6 pin and the number 14 pin of the encoder signal input interface ENC1, and are used for receiving differential signals CH1D and/CH 1D. Four pairs of differential signals CH1A, CH1B, CH1C, CH1D and/CH 1D are output into 4 corresponding single-ended signals CH1-A, CH1-B, CH-C and CH1-D through a differential-to-single-ended signal chip, the single-ended signal CH1-A is output through a No. 11 pin of the differential-to-single-ended signal chip U1, the single-ended signal CH1-B is output through a No. 5 pin of the differential-to-single-ended signal chip U1, the single-ended signal CH1-C is output through a No. 13 pin of the differential-to-single-ended signal chip U1, and the single-ended signal CH1-D is output through a No. 3 pin of the differential-to-single-ended signal chip U1.
It should be noted that, the voltage value of each pair of differential signals=half of the voltage value of the single-ended signal generated by the differential-to-single-ended signal chip.
Referring to fig. 1, 4-1 and 4-2, in one embodiment of the present utility model, the single-ended signal path selection chip includes 2 single-ended signal path selection chips, denoted as U2 and U5, respectively. Each single-ended signal path selection chip comprises: 8 input pins, namely a pin number 6 1C0, a pin number 5 1C1, a pin number 4 1C2, a pin number 3 1C3, a pin number 10 2C0, a pin number 11 2C1, a pin number 12 2C2 and a pin number 13 2C3; the 2 output pins are respectively a No. 7 pin 1Y and a No. 9 pin 2Y; the 2 gating control pins are a 14 # pin A and a 2 # pin B respectively.
In this embodiment, the single-ended signal path selection chip may be of a type 74HC153, it being understood that in other embodiments, the single-ended signal path selection chip may be of other types.
Referring to fig. 3, 4-1 and 4-2, in a specific embodiment, the single-ended signal CH1-a output by the differential to single-ended signal chip U1 is connected to pin 3 of the single-ended signal gating chip U2, the single-ended signal CH1-B output by the differential to single-ended signal chip U1 is connected to pin 13 of the single-ended signal gating chip U2, the single-ended signal CH1-C output by the differential to single-ended signal chip U1 is connected to pin 3 of the single-ended signal gating chip U5, and the single-ended signal CH1-D output by the differential to single-ended signal chip U1 is connected to pin 13 of the single-ended signal gating chip U5.
IN order to realize the control of the single-ended signal channel selection chip, referring to fig. 5, IN an embodiment of the utility model, the board further includes an external input interface sel_in and a signal selection control loop, wherein an input end of the signal selection input loop is connected to an external input signal, an output end of the signal selection input loop is electrically connected to a gate control pin of the single-ended signal channel selection chip, and the signal selection input loop is used for controlling the single-ended signal channel selection chip to select channels.
Referring to fig. 5, IN one embodiment, the signal selection control loop includes 2 signal selection control loops, and the external input interface sel_in includes 2 input terminals. Each input terminal comprises 1 first sub-input terminal and 1 second sub-input terminal, two signal input ends of each signal selection control loop are respectively connected with one first sub-input terminal and one second sub-input terminal, and the output of the signal selection control loop is changed according to the level of connection of the first sub-input terminal and the second sub-input terminal. For convenience of description hereinafter, a first sub-input terminal connected to an input end of one of the signal selection control loops is denoted as +sel0, a second sub-input terminal is denoted as-SEL 0, and an output end is denoted as/SEL 0; the first sub-input terminal connected to the input terminal of the other signal selection control circuit is denoted as +sel1, the second sub-input terminal is denoted as-SEL 1, and the output terminal is denoted as/SEL 1.
Referring to FIGS. 4-1, 4-2 and 5, the outputs/SEL 0,/SEL 1 of the signal select control loop are connected to the strobe control pins 14 and 2 of the single-ended signal strobe chips U2 and U5, respectively. In this embodiment, when the first sub-input terminal is connected to the high level and the second sub-input terminal is connected to the 0V, the output of the signal selection input circuit is a logic value 1, and when the first sub-input terminal is connected to the high level and the second sub-input terminal has no power input, the output of the signal selection input circuit is a logic value 0. For example, when the first sub-input terminal +SEL0 (or +SEL1) is connected to 24V and the second sub-input terminal-SEL0 (or-SEL1) is connected to 0V,/SEL0 (or/SEL1) is a digital logic value "1"; when the first sub-input terminal is denoted +SEL0 (or +SEL1) to 24V and the second sub-input terminal-SEL0 (-SEL1) has no power input,/SEL0 (or/SEL1) is a digital logic value "0". That is, by controlling whether-SEL 0 (-SEL 1) is connected with 0V, the logic value of the output of/SEL 0 (or/SEL 1) can be controlled, and further/SEL 0 and/SEL 1 can form four combinations of "00", "01", "10" and "11".
All differential signals in a certain encoder can be selected according to the four combined states of the input signals/SEL 0 and/SEL 120 received by the two gating control pins of the single-ended signal gating chips U2 and U5. For example, it can be provided that: sel0=0,
When/sel1=0, the single-ended signal gating chip U2 selects and outputs CH1A and CH1B, and the single-ended signal gating chip U5 selects and outputs CH1C and CH1D; when,/sel0=0,/sel1=1, the single-ended signal gating chip U2 selects the outputs CH2A and CH2B, and the single-ended signal gating chip U5 selects the outputs CH2C and CH2D; when/sel0=1 and/sel1=0, the single-ended signal gating chip U2 selects and outputs CH3A and CH3B, and the single-ended signal gating chip U5 selects and outputs CH3C and CH3D; when,/sel0=1,/SEL 110, the single-ended signal gating chip U2 selects the outputs CH4A and CH4B, and the single-ended signal gating chip U5 selects the outputs CH4C and CH4D. By the arrangement, single-ended signals corresponding to differential signals in a certain encoder signal input interface channel can be selected.
Referring to fig. 5, in one embodiment, each of the signal selection control loops includes a first resistor R39 (R49), a first diode D1 (D2), a photo coupler (coupled by a diode and a triode PC1 (PC 2)), a light emitting diode LED1 (LED 2), a first capacitor C1 (C2), and a second resistor R38 (R48), specifically:
a first end of the first resistor R39 (R49) is connected to the first sub-input terminal +sel0 (+sel1), and a second end of the first resistor R39 (R49) is connected to the negative electrode of the first diode D1 (D2) and the first end 1 of the photocoupler;
the positive electrode of the first diode D1 (D2), the negative electrode of the light emitting diode LED1 (LED 2) and the second sub-input terminal-SEL 0 (-SEL 1) are connected;
the positive electrode of the light emitting diode is connected with the second end 2 of the photoelectric coupler;
a first end of the second resistor R38 (R48) is connected with a power supply VCC;
the third end 3 of the photoelectric coupler and the second end of the first capacitor C1 (C2) are grounded;
the fourth terminal 4 of the photo coupler is connected to the second terminal of the second resistor R38 (R48) and the first terminal of the first capacitor C1 (C2), and is used as the output terminal of the signal selection input circuit.
Referring to fig. 6, in one embodiment, the single-ended to differential signal chip U3 includes 4 input pins and 8 input pins. The 4 input pins are a pin 1A, a pin 2A, a pin 3A and a pin 15A; the 8 input pins are respectively a No. 2 pin 1Y, a No. 3 pin 1Z, a No. 6 pin 2Y, a No. 5 pin 2Z, a No. 10 pin 3Y, a No. 11 pin 3Z, a No. 14 pin 4Y and a No. 13 pin 4Z.
Referring to fig. 4 and 6, in a specific embodiment, a signal output pin 7 and a signal output pin 9 of a U2 of the single-ended signal strobe chip are connected to a No. 1 input pin and a No. 7 input pin of the single-ended to differential signal chip U3, respectively; the signal output pin 7 and the signal output pin 9 of the U5 of the single-ended signal gating chip are respectively connected to the No. 9 input pin and the No. 15 input pin of the single-ended to differential signal chip U3. And restoring the single-ended signal corresponding to the differential signal in a certain input encoder signal input interface channel into the differential signal which is initially received by a certain input encoder signal input interface channel through the single-ended-to-differential chip.
In this embodiment, the single-ended to differential signal chip may be 26C31/SO, and it is understood that in other embodiments, the single-ended to differential signal chip may be of other types.
Referring to fig. 7, in an embodiment of the present utility model, the encoder signal output interface enc_sel includes 15 pins, where pin 1, pin 9, pin 4, pin 12, pin 5, pin 13, pin 6, pin 14 of the encoder signal input interface are signal input pins, and each encoder signal output interface may allow four pairs of differential signals to pass through.
Referring to fig. 6 and 7, a signal input pin of an encoder signal output interface enc_sel is connected to an output end of a single-ended differential signal chip, and the encoder signal output interface enc_sel outputs a differential signal received by a selected encoder signal input interface through the signal input pin.
It should be noted that the above embodiments are described based on selecting one output from four encoder signal input interfaces, and it is understood that the differential signals in each encoder signal input interface are not limited to four groups. In other embodiments, the present utility model is not limited to the above description, for example, the number of encoder signal input interfaces is two, and in this case, the selection of one output from 2 encoder signal input interfaces may be implemented, and for example, the number of encoder signal input interfaces is 3, and in this case, the selection of one output from 3 encoder signal input interfaces may be implemented. It should be noted that the single-ended signal gating chip is not necessarily two, for example, when there are only 2 encoder signal input interfaces, and each encoder signal input interface value receives a set of differential signals, only 1 single-ended signal gating implementation is required to satisfy the condition.
In summary, the number of the differential to single-ended signal chip, the single-ended signal strobe chip, the encoder signal input interface, and the single-to-differential chip is not limited to the description of the present disclosure, and the principle is the same as that described in the foregoing embodiments, and the corresponding arrangement needs to be made according to the actual requirements.
In this embodiment, the encoder signal strobe board further includes a power circuit, and an externally input power supply supplies power to a circuit inside the board through the power circuit.
Referring to fig. 8, in an embodiment of the present utility model, the power circuit specifically includes:
a power supply terminal PWR1, a fuse F1, a second diode D3, a second capacitor C3, a third capacitor C4, a fourth capacitor C5, and an inductor FB1;
a first end of the fuse F1 is connected to the first connection port 1 of the power supply connector PWR1, and a second end 2 of the fuse F1 is connected to the negative electrode of the diode D3, the positive electrode of the second capacitor C3, the first end of the third capacitor C4, and the first end of the inductor FB1;
the second end of the inductor FB1 and the first end of the fourth capacitor C5 are connected with an internal power supply VCC;
the second connection port 2 of the power connector is connected with the positive electrode of the second diode D3, the negative stage of the second capacitor C3, the second end of the third capacitor C4, and the second end of the fourth capacitor C5 are grounded.
In this embodiment, the board card further includes an indicator light loop, where the indicator light loop is used to display the power-on condition of the circuit.
The systems and methods have been described herein in general terms as being helpful in understanding the details of the present utility model. Furthermore, various specific details have been set forth in order to provide a thorough understanding of embodiments of the utility model. One skilled in the relevant art will recognize, however, that an embodiment of the utility model can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the utility model.
Thus, although the utility model has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the utility model will be employed without a corresponding use of other features without departing from the scope and spirit of the utility model as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present utility model. It is intended that the utility model not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this utility model, but that the utility model will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the utility model should be determined only by the following claims.
Claims (10)
1. An encoder signal path selection board, comprising at least:
an encoder signal input interface, said encoder signal input interface comprising at least two, each said encoder signal input interface to receive at least one set of first differential signals;
the number of the differential-to-single-ended signal chips is the same as that of the encoder signal input interfaces, each differential-to-single-ended signal chip is electrically connected with differential signal output pins of 1 encoder signal input interface, and each differential-to-single-ended signal chip is used for converting at least one group of first differential signals received by the encoder signal input interface connected with the differential-to-single-ended signal chip into corresponding single-ended signals;
the single-ended signal channel selection chip is electrically connected with the output end of the differential-to-single-ended signal chip and is used for selecting at least one group of single-ended signals converted from first differential signals received by the 1 encoder signal input interfaces;
the single-ended transfer differential signal chip is electrically connected with the output end of the single-ended signal channel selection chip and is used for restoring the selected single-ended signal into a corresponding second differential signal;
the encoder signal output interface is connected with the output end of the single-ended differential signal chip, and the second differential signal is output through the encoder signal output interface.
2. The encoder signal path selection board of claim 1, further comprising an external input interface comprising 2 input terminals, each of the input terminals comprising 1 first sub-input terminal and 1 second sub-input terminal, an input of each signal selection input loop being connected to one of the first sub-input terminal and the second sub-input terminal, respectively, an output of the signal selection input loop varying according to a level at which the first sub-input terminal and the second sub-input terminal are connected.
3. The encoder signal path selection board of claim 2, further comprising a signal selection control loop, an input of the signal selection input loop being connected to an external input signal, an output of the signal selection input loop being electrically connected to a strobe control pin of the single-ended signal path selection chip, the signal selection input loop being configured to control the single-ended signal path selection chip path selection.
4. The encoder signal path selection board of claim 3, wherein the signal selection control loop comprises 2, each of the signal selection control loops comprises a first resistor, a first diode, a photocoupler, a light emitting diode, a first capacitor, and a second resistor, specifically:
the first end of the first resistor is connected with the first sub-input terminal, and the second end of the first resistor is connected with the cathode of the first diode and the first end of the photoelectric coupler;
the anode of the first diode, the cathode of the light emitting diode and the second sub-input terminal are connected;
the positive electrode of the light emitting diode is connected with the second end of the photoelectric coupler;
the first end of the second resistor is connected with a power supply VCC;
the fourth end of the photoelectric coupler is connected with the second end of the second resistor and the first end of the first capacitor;
the third end of the photoelectric coupler and the second end of the first capacitor are grounded;
and the fourth end of the photoelectric coupler is used as an output end of the signal selection control loop.
5. The encoder signal path select board card of claim 2, wherein the output of the signal select input loop is a logic value of 1 when the first sub-input terminal is high and the second sub-input terminal is 0V, and wherein the output of the signal select input loop is a logic value of 0 when the first sub-input terminal is high and the second sub-input terminal is not powered.
6. The encoder signal path selection board of claim 1, wherein the encoder signal gating board further comprises a power circuit through which an externally input power supply powers circuitry within the board.
7. The encoder signal path select board card of claim 6, wherein the power supply loop comprises:
the power supply connector, the fuse, the second diode, the second capacitor, the third capacitor, the fourth capacitor and the inductor;
the first end of the fuse is connected to the first connection port of the power connector, and the second end of the fuse is connected with the negative electrode of the diode, the positive electrode of the second capacitor, the first end of the third capacitor and the first end of the inductor;
the second end of the inductor and the first end of the fourth capacitor are connected with an internal power supply VCC;
the second connecting port of the power connector is connected with the positive electrode of the second diode, the negative stage of the second capacitor, the second end of the third capacitor, the second end of the fourth capacitor and the second end of the fourth capacitor are grounded.
8. The encoder signal path selection board of claim 1, further comprising an indicator light loop for displaying a power on condition of the circuit.
9. The encoder signal path select board card of claim 1, wherein the single ended signal path select chip is model 74HC153.
10. The encoder signal path select board card of claim 1, wherein the differential signal voltage value is half of the voltage value of a single-ended signal into which the differential signal is converted.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223522687.4U CN219577083U (en) | 2022-12-27 | 2022-12-27 | Encoder signal channel selection board card |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223522687.4U CN219577083U (en) | 2022-12-27 | 2022-12-27 | Encoder signal channel selection board card |
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| Publication Number | Publication Date |
|---|---|
| CN219577083U true CN219577083U (en) | 2023-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223522687.4U Active CN219577083U (en) | 2022-12-27 | 2022-12-27 | Encoder signal channel selection board card |
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| CN (1) | CN219577083U (en) |
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