CN219575614U - Packaging structure - Google Patents

Abstract

The utility model discloses a packaging structure. The package structure includes: a lower wire structure layer; an electronic element located on the lower conductive line structure layer; a rigidity reinforcing layer located on the electronic component; the packaging layer is used for packaging the electronic element and the rigidity reinforcing layer, wherein the rigidity of the rigidity reinforcing layer is greater than that of the packaging layer; and the upper wire structure layer is positioned on the rigid reinforcing layer and the packaging layer. According to the technical scheme, the rigid reinforcing layer is arranged above the electronic element, so that the warping performance of the packaging structure can be improved at least, and the problems of adverse subsequent wire structure layer feeding operation and substrate attachment caused by poor existing warping performance can be solved. In addition, the side walls of the rigidity reinforcing layer can be exposed by the packaging layer, so that heat dissipation can be better provided for the electronic component.

Description

Packaging structure

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a packaging structure.

Background

In the conventional fan-out stack package (FOPOP, fan-out Package on Package, poP) process, an upper redistribution layer (RDL) 20 is formed over the bottom package 10, and memory elements (not shown) are formed over the upper redistribution layer 20. The bottom package 10 is encapsulated by a molding compound 12 (e.g., EMC (Epoxy Molding Compound, epoxy) molding compound), and then the upper redistribution layer 20 is formed on the upper surface of the molding compound 12 after encapsulation, and the upper surface of the molding compound 12 should be a flat surface for facilitating the subsequent process for the upper redistribution layer 20.

However, the limited ratio of Die (Die) 14 to the amount of molding compound 12 is small (i.e., the amount of molding compound 12 is large) such that the selection of molding compound 12 is limited and the use of a more rigid molding compound 12 is not possible to enhance the warpage behavior of the bottom package 10 because the more rigid molding compound 12 may have greater thermal shrinkage. And, also limited by the coefficient of thermal expansion (CTE, coefficient of thermal expansion) mismatch between the molding compound 12 and the upper redistribution layer 20, results in poor warpage performance. Warpage of the bottom package 10 would be detrimental to subsequent handling of the upper redistribution layer 20. In addition, since warpage performance is poor, if a conventional high temperature mass reflow (mass reflow) process is applied, warpage performance under the high temperature process may be greater than 100 μm, which is disadvantageous for the subsequent use of the mass reflow process to attach the structure shown in fig. 1 to a substrate. Specifically, warpage causes problems of solder ball-to-substrate disconnection (non-joint) after batch reflow, so that attachment to the substrate fails, and the existing failure rate can reach 100%. In addition, because of the warpage, TCB (thermal compression bond, thermocompression bonding) is used during batch reflow to connect individual solder balls to the substrate, however, applying pressure will damage the surface of the upper redistribution layer 20.

Disclosure of Invention

The present utility model provides a package structure that can at least have improved warpage performance, in order to solve the above-mentioned problems of poor warpage performance resulting in disadvantageous subsequent upper redistribution layer operation and subsequent attachment to a substrate.

The technical scheme of the utility model is realized as follows:

according to one aspect of the present utility model, a package structure is provided. The packaging structure comprises: a lower wire structure layer; an electronic element located on the lower conductive line structure layer; a rigidity reinforcing layer located on the electronic component; the packaging layer is used for packaging the electronic element and the rigidity reinforcing layer, and the rigidity of the rigidity reinforcing layer is greater than that of the packaging layer; and the upper wire structure layer is positioned on the rigid reinforcing layer and the packaging layer.

In some embodiments, the upper wire structure layer contacts the stiffening layer.

In some embodiments, the package structure further includes a conductive post located between the upper and lower wire structure layers and encapsulated by the package layer.

In some embodiments, the coefficient of thermal expansion of the rigid reinforcing layer is less than the coefficient of thermal expansion of the encapsulation layer.

In some embodiments, the stiffening layer is formed of the same material as the electronic component.

In some embodiments, the rigidity-enhancing layer has a width in the lateral direction that is greater than a width of the electronic component.

In some embodiments, the sidewalls of the stiffening layer are exposed by the encapsulation layer.

In some embodiments, the package structure further includes a conductive post located between the upper and lower wire structure layers, and the conductive post passes through the stiffening layer.

In some embodiments, the package structure further includes a conductive pillar located between the upper and lower conductive line structure layers, wherein the rigid reinforcement layer further includes another sidewall surrounded by the package layer, and the conductive pillar is located beside the other sidewall of the rigid reinforcement layer.

In some embodiments, the package structure further includes an adhesive layer between the rigid reinforcing layer and the electronic component, the adhesive layer being a heat dissipating material.

According to the technical scheme, the rigid reinforcing layer is arranged above the electronic element, so that the warping performance of the packaging structure can be improved at least, and the problems of adverse subsequent wire structure layer feeding operation and substrate attachment caused by poor existing warping performance can be solved.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic partial cross-sectional view of a prior art package structure.

Fig. 2 is a schematic cross-sectional view of a package structure according to an embodiment of the present utility model.

Fig. 3A is a schematic cross-sectional view of a package structure according to another embodiment of the present utility model.

Fig. 3B is a schematic top view of the package structure shown in fig. 3A.

Fig. 4 is a schematic cross-sectional view of a package structure according to another embodiment of the present utility model.

Fig. 5A-5J are schematic cross-sectional views of stages of forming a package structure according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the utility model, fall within the scope of protection of the utility model.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 2 is a schematic cross-sectional view of a package structure 100 according to an embodiment of the utility model. Referring to fig. 2, the package structure 100 includes a lower conductive line structure layer 110. The lower conductive line structure layer 110 may include at least one dielectric layer 112 and a metal conductive feature 114 embedded in the at least one dielectric layer 112. The number of layers of the at least one dielectric layer 112 may be selected to be any suitable number. In fig. 2, the lower conductive line structure layer 110 includes three dielectric layers 112, and the embodiment is illustrated by taking three dielectric layers 112 as an example. The metal conductive features 114 may include traces, vias, pads, and the like. In some embodiments, the lower wire structure layer 110 may be a redistribution layer. The lower conductive line structure layer 110 may be connected to the substrate 102 by a plurality of solder balls 119.

The package structure 100 further includes an electronic component 104 on the lower wiring structure layer 110. In some embodiments, the electronic component 104 may be a chip. In some embodiments, the material of the electronic component 104 may be silicon. The electronic component 104 may be electrically connected to the lower conductive line structure layer 110 through a plurality of solder balls 117.

The package structure 100 further includes a rigid stiffener layer 120 on the electronic component 104, and an encapsulation layer 130 encapsulating the electronic component 104 and the rigid stiffener layer 120. The material of the encapsulation layer 130 may be a molding compound, for example, an epoxy molding compound. The package structure 100 may further include an upper wire structure layer 140 on the rigid reinforcement layer 120 and the package layer 130. The upper conductive line structure layer 140 may be a redistribution layer. The upper conductive line structure layer 140 may include a plurality of dielectric layers 142 and metal conductive features, such as pads 144, located in the plurality of dielectric layers 142.

The package structure 100 may further include a memory element 150 disposed above the upper conductive line structure layer 140 and electrically connected to the upper conductive line structure layer 140. The memory element 150 may be, for example, a DDR (Double Data Rate SDRAM, double data Rate synchronous dynamic random Access memory). Memory element 150 may be connected to pads 144 of upper wiring structure layer 140 by solder balls 159.

Wherein the rigidity enhancement layer 120 can enhance the rigidity of the portion 106 between the lower conductive line structure layer 110 and the substrate 102, and further can enhance the overall rigidity and warpage behavior of the structure above the substrate 102. In some embodiments, the rigidity reinforcement layer 120 is stiffer than the encapsulation layer 130, such that the rigidity reinforcement layer 120 may serve to enhance rigidity. In some embodiments, the stiffening layer 120 may be made more rigid by selecting the material of the stiffening layer 120. Since young's modulus may be used to represent the rigidity of the solid material, in such embodiments, the material of the rigid reinforcing layer 120 is selected to have a young's modulus greater than that of the encapsulation layer 130, i.e., the young's modulus of the rigid reinforcing layer 120 is greater than that of the encapsulation layer 130. The material of the rigidity-reinforcing layer 120 may also consider the thermal conductivity of the material, and the high thermal conductivity may be beneficial to heat dissipation of the electronic component 104. In some embodiments, the thermal conductivity of the rigid reinforcing layer 120 is not less than the thermal conductivity of the encapsulation layer 130. In some embodiments, the thermal conductivity of the rigid reinforcing layer 120 is not less than the thermal conductivity of the electronic element 104. In some embodiments, the stiffening layer 120 is a non-metallic material with a relatively high resistivity.

The thermal conductivities, resistivities at Room Temperature (RT), and young's moduli at room temperature of the three candidate materials are shown in table 1 below. As shown in table 1, si (silicon) and SiC (silicon carbide) have high young's modulus and high thermal conductivity, and Si and SiC have high resistivity, and thus can be used as a material with rigidity reinforcement. GaAs (gallium arsenide) having a lower young's modulus and thermal conductivity is not suitable for the stiffening layer 120.

TABLE 1

In some embodiments, the material of the stiffening layer 120 may be Si or SiC. In some embodiments, the stiffening layer 120 is formed of the same material as the electronic component 104. For example, the material of both the electronic component 104 and the stiffening layer 120 is Si. In some embodiments, the stiffening layer 120 is formed of a different material than the electronic component 104. For example, the material of the electronic element 104 is SiC, and the material of the rigid reinforcing layer 120 is Si. The various materials listed above are merely examples, and the stiffening layer 120 may be any material capable of stiffening the portion 106.

In the package structure 100, the rigidity and warpage of the portion 106 between the lower conductive line structure layer 110 and the upper conductive line structure layer 140 can be improved by placing the rigidity enhancing layer 120 over the electronic component 104, so that the operation of the upper conductive line structure layer 140 is facilitated. Further, since the rigidity of the portion 106 is improved, the overall rigidity and warpage performance of the structure above the substrate 102 can be improved, and thus the attachment work with the substrate 102 can be facilitated. Specifically, the structure above the substrate 102 may be bonded to the substrate 102 by the plurality of solder balls 119 using a high temperature reflow process, and the warpage of the structure above the substrate 102 may be less than 100 μm during the reflow process, so that the solder balls 119 may be prevented from being disconnected from the substrate 102, and the TCB mode that may damage the surface of the dielectric layer 142 of the upper conductive line structure layer 140 may not be employed.

In some embodiments, the material of the stiffening layer 120 may also be selected such that the coefficient of thermal expansion of the stiffening layer 120 is less than the coefficient of thermal expansion of the encapsulation layer 130. Since the thermal expansion coefficient of the rigid reinforcing layer 120 is smaller than that of the encapsulation layer 130, the warpage performance can be improved. In some embodiments, the material of the stiffening layer 120 may be the same material as the electronic component 104, i.e., a material having the same coefficient of thermal expansion as the electronic component 104. The rigidity reinforcement layer 120 may be made of a material having a thermal expansion coefficient similar to that of the electronic component 104.

With continued reference to fig. 2, the upper surface of the stiffening layer 120 is flush with the upper surface of the encapsulation layer 130. The upper conductive line structure layer 140 contacts the upper surface of the rigidity-enhancing layer 120 and the upper surface of the encapsulation layer 130. The rigidity reinforcement layer 120 may have a width in the lateral direction that is greater than the width of the electronic component 104. The sidewalls of the stiffening layer 120 may protrude from the corresponding sidewalls of the electronic component 104.

The stiffening layer 120 may be attached to the electronic component 104 by an adhesive layer 154. The material of the adhesive layer 154 may be selected as a heat dissipating material. In this way, heat may be dissipated to the electronic component 104 via the adhesive layer 154 and the stiffening layer 120.

The package structure 100 further includes conductive pillars 170. The conductive pillars 170 are located between the upper conductive line structure layer 140 and the lower conductive line structure layer 110. The conductive pillars 170 may electrically connect the upper conductive line structure layer 140 and the lower conductive line structure layer 110. The conductive pillars 170 are also encapsulated by the encapsulation layer 130. In some embodiments, the package structure 100 may further include a passive device 118 disposed at a bottom surface of the lower conductive line structure layer 110. The passive devices 118 may be electrically connected to the lower conductive line structure layer 110. The passive devices 118 may be, for example, integrated passive devices (IPD, integrated Passive Device).

An underfill 182 may be disposed between the lower conductive line structure layer 110 and the substrate 102, and the underfill 182 may encapsulate each solder ball 119 and passive device 118 between the lower conductive line structure layer 110 and the substrate 102. The underfill 182 may also encapsulate the lower portion of the sidewalls of the lower conductive line structure layer 110. An underfill 184 may be disposed between the electronic component 104 and the lower conductive line structure layer 110, and the underfill 184 may encapsulate each solder ball 117 between the electronic component 104 and the lower conductive line structure 110, and may encapsulate a lower portion of a sidewall of the electronic component 104.

Fig. 3A is a schematic cross-sectional view of a package structure 200 according to another embodiment of the utility model. Fig. 3B is a schematic top view of the package structure 200 shown in fig. 3A at line A-A. Referring to fig. 3A to 3B, a side wall 121 of the rigid reinforcing layer 120 is exposed from the encapsulation layer 130. The other three unexposed sidewalls of the stiffening layer 120 remain encapsulated by the encapsulation layer 130. Although one sidewall 121 of the rigid reinforcing layer 120 is shown exposed by the encapsulation layer 130 in fig. 3A to 3B, in other embodiments, multiple sidewalls of the rigid reinforcing layer 120 may be exposed by the encapsulation layer 130. By exposing at least one side wall of the stiffening layer 120, heat dissipation may be better provided for the electronic component 104.

Other aspects of the package structure 200 shown in fig. 3A may be similar to the package structure 100 described with reference to fig. 2, and will not be described again here.

Fig. 4 is a schematic cross-sectional view of a package structure 300 according to another embodiment of the utility model. The package structure 300 shown in fig. 4 differs from the package structure 200 shown in fig. 3A in that at least one conductive post 170' may pass through the stiffening layer 120. The conductive pillars 170' passing through the stiffening layer 120 may electrically connect the lower conductive line structure layer 110 and the upper conductive line structure layer 140. The conductive posts 170' passing through the stiffening layer 120 are located laterally between the sidewalls 121 of the stiffening layer 120 exposed by the encapsulation layer 130 and the electronic component 104.

Fig. 5A-5J are schematic cross-sectional views of stages of forming a package structure according to an embodiment of the utility model. Referring first to fig. 5A, a carrier 510 is provided. A lower conductive line structure layer 110 is formed over the carrier 510. The lower conductive line structure layer 110 may include a multi-layered dielectric layer 112 and a metal conductive feature 114 located in the multi-layered dielectric layer 112. In the present embodiment, the lower conductive line structure layer 110 is shown to include three dielectric layers 112 and three metal conductive features 114. Then, conductive pillars 170 electrically connected to the lower conductive line structure layer 110 are formed on the lower conductive line structure layer 110.

Referring to fig. 5B, the electronic component 104 is flip-chip (FCB, flip Chip Bonding) bonded to the lower conductive trace structure layer 110 by the solder balls 117, and an underfill 184 is formed between the electronic component 104 and the lower conductive trace structure layer 110 to encapsulate each solder ball 117.

Referring to fig. 5C, the rigid reinforcing layer 120 is adhered to the electronic component 104 by an adhesive layer 154.

Referring to fig. 5D, the encapsulation layer 130 encapsulating the electronic component 104, the conductive pillars 170, and the rigidity-enhancing layer 120 is formed using a molding compound. At this time, the upper surface of the rigidity-reinforcing layer 120 may be higher than the upper surface of the Yu Daodian post 170, and the upper surface of the encapsulation layer 130 may be higher than the upper surface of the rigidity-reinforcing layer 120.

Referring to fig. 5E, the upper surfaces of the encapsulation layer 130, the conductive pillars 170, and the rigidity-enhancing layer 120 are planarized by a polishing process such that the upper surfaces of the encapsulation layer 130, the conductive pillars 170, and the rigidity-enhancing layer 120 are flush.

Referring to fig. 5F, an upper conductive line structure layer 140 is formed on the upper surfaces of the encapsulation layer 130, the conductive pillars 170, and the rigidity reinforcement layer 120. The upper conductive line structure layer 140 may include a plurality of dielectric layers 142 and metal conductive features, such as pads 144, located in the plurality of dielectric layers 142. In this embodiment, the upper conductive line structure layer 140 is shown to include two dielectric layers 142 and one pad 144. The pads 144 are exposed by the uppermost dielectric layer 142.

Since the stiffening layer 120 is provided, the warp behavior of the structure shown in fig. 5E can be enhanced, and thus the work of forming the stiffening layer 120 can be facilitated.

Referring to fig. 5G, an additional carrier 520 is attached to the upper wire structure layer 140 by an attachment layer 522. The carrier 510 shown in fig. 5F is then removed.

Referring to fig. 5H, solder balls 119 electrically connected to the lower wiring structure layer 110 are formed at the bottom surface of the lower wiring structure layer 110, and passive devices 118 are bonded at the bottom surface of the lower wiring structure layer 110.

Referring to fig. 5I, the attachment layer 522 and carrier 520 shown in fig. 5H are removed. Then, dicing may be performed to obtain individual intermediate package structures 100'.

Referring to fig. 5J, the intermediate package structure 100' obtained in fig. 5I is bonded to the substrate 102 by means of solder balls 119. In some embodiments, high temperature reflow Cheng Huiliu solder balls 119 are used to bond the intermediate package structure 100' to the substrate 102. Since the stiffening layer 120 is provided, the warpage behavior of the intermediate package structure 100 'is improved, and the warpage of the intermediate package structure 100' during the reflow process may be less than 100 μm. Since the intermediate package structure 100 'has an improved warpage behavior, no disconnection of the solder balls 119 from the substrate 120 occurs during the reflow process even without applying pressure to the intermediate package structure 100' (i.e., without using TCB). In addition, damage to the surface of the dielectric layer 142 of the upper wire structure 140 is also avoided since no pressure may be applied to the intermediate package structure 100'.

An underfill 182 may then be formed between the substrate 102 and the lower conductive line structure layer 110 to encapsulate the individual solder balls 119 and bond the memory element 150 on the pads 144 of the upper conductive line structure layer 140 via solder 159, forming the package structure 100.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the utility model.

Claims (10)

1. A package structure, comprising:

a lower wire structure layer;

an electronic component located on the lower conductive line structure layer;

a rigidity reinforcing layer located on the electronic element;

an encapsulation layer encapsulating the electronic component and the rigidity enhancement layer, the rigidity of the rigidity enhancement layer being greater than the rigidity of the encapsulation layer;

and the upper lead structure layer is positioned on the rigid reinforcing layer and the packaging layer.

2. The package structure of claim 1, wherein the upper conductive line structure layer contacts the rigid reinforcement layer.

3. The package structure of claim 1, further comprising:

and the conductive column is positioned between the upper wire structure layer and the lower wire structure layer and is encapsulated by the encapsulation layer.

4. The package structure of claim 1, wherein the rigid reinforcement layer has a coefficient of thermal expansion that is less than a coefficient of thermal expansion of the package layer.

5. The package structure of claim 1, wherein the stiffening layer is the same material as the electronic component.

6. The package structure of claim 1, wherein the rigidity-enhancing layer has a width in a lateral direction that is greater than a width of the electronic component.

7. The package structure of claim 1, wherein sidewalls of the stiffening layer are exposed by the encapsulation layer.

8. The package structure of claim 1, further comprising:

and the conductive column is positioned between the upper wire structure layer and the lower wire structure layer and penetrates through the rigid reinforcing layer.

9. The package structure of claim 7, further comprising:

and the conductive column is positioned between the upper wire structure layer and the lower wire structure layer, wherein the rigid reinforcement layer further comprises another side wall covered by the packaging layer, and the conductive column is positioned beside the other side wall of the rigid reinforcement layer.

10. The package structure of claim 1, further comprising:

and the bonding layer is positioned between the rigid reinforcing layer and the electronic element, and the bonding layer is made of a heat dissipation material.