CN219554609U - Power distribution circuit and electronic equipment - Google Patents
Power distribution circuit and electronic equipment Download PDFInfo
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- CN219554609U CN219554609U CN202223438549.8U CN202223438549U CN219554609U CN 219554609 U CN219554609 U CN 219554609U CN 202223438549 U CN202223438549 U CN 202223438549U CN 219554609 U CN219554609 U CN 219554609U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The utility model discloses a power distribution circuit and electronic equipment. The power distribution circuit includes: the two bus interfaces are positioned at different positions of the body; the two power control chips are arranged one by one with the two bus interfaces and are respectively connected with the corresponding bus interfaces and the main chip; the two power control chips are also connected with each other, one power control chip is connected with a power supply signal at a corresponding bus interface, when the other power control chip is determined that the other power control chip is not connected with the power supply signal, the charging power of the corresponding bus interface is adjusted to be a first preset charging power, and the other power control chip is informed to adjust the charging power of the corresponding bus interface to be a second preset charging power; the first preset charging power is different from the second preset charging power. Through the mode, the flexibility of the charging port in use can be improved.
Description
Technical Field
The present utility model relates to the field of electronic technologies, and in particular, to a power distribution circuit and an electronic device.
Background
Currently, an electronic device is provided with two bus interfaces for charging an external device. Considering power board power and cost of an electronic device, generally, one of the bus interfaces has higher charging power, and the other bus interface has lower charging power. And one bus interface is arranged on a front panel of the electronic equipment, and the other bus interface is arranged on a side panel of the electronic equipment. The use habits of users on the electronic devices are different, and some users learn the bus interface of the conventional front panel and some users learn the bus interface of the conventional side panel, but because of the setting of the built-in power control chip of the bus interface, the charging power is set by a power list set by the firmware of the power control chip. The firmware of the power control chip is burnt and set when the electronic equipment leaves the factory, and the maximum chargeable power of the bus interface is not adjustable.
And if the charging power is higher, the charging speed is high. If the user wants to use the bus interface with high charging speed, only the bus interface with high charging power at a fixed position can be used, the flexibility is poor, and the user requirements of different use habits cannot be met.
Disclosure of Invention
The utility model provides a power distribution circuit and electronic equipment, which can distribute power to a charging port and improve the flexibility of the use of the charging port.
In order to solve the technical problems, the utility model adopts a technical scheme that: there is provided a power distribution circuit for an electronic device, the electronic device including a power distribution circuit, a main chip, and a body, the power distribution circuit and the main chip being disposed on the body, the power distribution circuit including: the two bus interfaces are positioned at different positions of the body; the two power control chips are arranged one by one with the two bus interfaces and are respectively connected with the corresponding bus interfaces and the main chip; the two power control chips are also connected with each other, one power control chip is connected with a power supply signal at a corresponding bus interface, when the other power control chip is determined that the other power control chip is not connected with the power supply signal, the charging power of the corresponding bus interface is adjusted to be a first preset charging power, and the other power control chip is informed to adjust the charging power of the corresponding bus interface to be a second preset charging power; the first preset charging power is different from the second preset charging power.
Optionally, the power control chip includes: the control chip is respectively connected with the corresponding bus interface and the other power control chip and is used for sending a power adjustment signal to the other power control chip when the corresponding bus interface is connected with the power supply signal, and the other power control chip generates a feedback signal to the control chip based on the power adjustment signal; the power management chip is respectively connected with the corresponding bus interface and the control chip and is used for adjusting the charging power of the corresponding bus interface based on the feedback signal; the feedback signal comprises an enable adjustment signal or a disable adjustment signal, if the other bus interface is not connected with the power supply signal, the other power control chip generates the enable adjustment signal based on the power adjustment signal, and the power management chip adjusts the charging power of the corresponding bus interface to the first preset charging power based on the enable adjustment signal; if the other bus interface is connected with the power supply signal, the other power control chip generates a prohibition adjustment signal based on the power adjustment signal, the power management chip adjusts the charging power of the corresponding bus interface to the first configuration power based on the prohibition adjustment signal, and the other power control chip adjusts the charging power of the corresponding bus interface to the second configuration power; the first configuration power is one of a first preset charging power and a second preset charging power, and the second configuration power is the other of the first preset charging power and the second preset charging power.
Optionally, the bus interface is a TypeC interface.
Optionally, the power distribution circuit further comprises: the first conversion circuit is respectively connected with the bus interface and the main chip and is used for converting a power supply signal of the bus interface so as to charge the main chip by utilizing the converted electric signal; and the second conversion circuit is respectively connected with the other bus interface and the main chip and is used for converting the power supply signal of the other bus interface so as to charge the main chip by utilizing the converted electric signal.
Optionally, the first conversion circuit and the second conversion circuit are both digital interfaces.
Optionally, the main chip is connected to the control chip by using a two-wire synchronous serial bus, and is configured to configure a first preset charging power and a second preset charging power for the corresponding bus interface through the control chip.
In order to solve the technical problems, the utility model adopts another technical scheme that: providing an electronic device comprising a power distribution circuit according to any one of the above technical solutions; a main chip; the main body, the power distribution circuit and the main chip are arranged on the main body.
Optionally, the body includes a circuit board, and the power distribution circuit and the main chip are integrated on the circuit board.
Optionally, the two bus interfaces are respectively disposed at the front and the side of the body.
Optionally, the electronic device further includes a display circuit connected to the main chip for displaying image information of the main chip.
The beneficial effects of the utility model are as follows: different from the prior art, the power distribution circuit is used for electronic equipment, and the electronic equipment comprises a power distribution circuit, a main chip and a body, wherein the power distribution circuit and the main chip are arranged on the body, and the power distribution circuit comprises two bus interfaces and is positioned at different positions of the body; the two power control chips are arranged one by one with the two bus interfaces and are respectively connected with the corresponding bus interfaces and the main chip; the two power control chips are also connected with each other, one power control chip is connected with a power supply signal at a corresponding bus interface, when the other power control chip is determined that the other power control chip is not connected with the power supply signal, the charging power of the corresponding bus interface is adjusted to be a first preset charging power, and the other power control chip is informed to adjust the charging power of the corresponding bus interface to be a second preset charging power; the first preset charging power is different from the second preset charging power. By means of the mode, the power control chip is connected with the power supply signals at the corresponding bus interfaces, when the fact that the other power control chip is not connected with the power supply signals is determined, the charging power of the corresponding bus interface is adjusted to be the first preset charging power, the other power control chip is informed of adjusting the charging power of the other bus interface to be the second preset charging power, dynamic adjustment of power distribution of the two bus interfaces can be achieved, namely, dynamic power distribution can be conducted on the charging ports, and flexibility of use of the charging ports can be improved.
Drawings
For a clearer description of the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of an embodiment of a power distribution circuit according to the present utility model;
FIG. 2 is a schematic diagram of another embodiment of a power distribution circuit of the present utility model;
FIG. 3 is a schematic illustration of the embodiment of FIG. 2;
fig. 4 is a schematic structural diagram of an embodiment of the electronic device of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In order to solve the above-mentioned problems, the present utility model first provides a power distribution circuit, as shown in fig. 1, fig. 1 is a schematic diagram of an embodiment of the power distribution circuit of the present utility model. In this embodiment, the power distribution circuit is used in an electronic device, the electronic device includes a power distribution circuit, a main chip 50 and a main body, the power distribution circuit and the main chip 50 are disposed on the main body, and the power distribution circuit includes: the two bus interfaces and the two power control chips are positioned at different positions of the body; the two power control chips are arranged one by one with the two bus interfaces, and are respectively connected with the corresponding bus interfaces and the main chip 50; the two power control chips are also connected with each other, one power control chip is connected with a power supply signal at a corresponding bus interface, when the other power control chip is determined that the other power control chip is not connected with the power supply signal, the charging power of the corresponding bus interface is adjusted to be a first preset charging power, and the other power control chip is informed to adjust the charging power of the corresponding bus interface to be a second preset charging power; the first preset charging power is different from the second preset charging power.
By means of the above manner, when the power control chip of the embodiment accesses the power supply signal at the corresponding bus interface and determines that the other power control chip is not accessed to the power supply signal, the charging power of the corresponding bus interface is adjusted to the first preset charging power, and the other power control chip is informed to adjust the charging power of the other bus interface to the second preset charging power, so that dynamic adjustment of power distribution of the two bus interfaces can be achieved, namely, dynamic power distribution can be carried out on the charging ports, and flexibility in use of the charging ports can be improved.
Specifically, the power distribution circuit includes a first bus interface 10, a second bus interface 20, a first power control chip 30, and a second power control chip 40. The second bus interface 20 and the first bus interface 10 are located at different positions of the body; the first power control chip 30 is connected with the first bus interface 10 and the main chip 50 respectively; the second power control chip 40 is connected with the second bus interface 20 and the main chip 50 respectively; the first power control chip 30 is further connected to the second power control chip 40, and when the first bus interface 10 is connected to a power supply signal and the second power control chip 40 is determined that the power supply signal is not connected to the first power control chip 40, the first power control chip 30 adjusts the charging power of the first bus interface 10 to a first preset charging power, and notifies the second power control chip 40 to adjust the charging power of the second bus interface 20 to a second preset charging power. Similarly, the second power control chip 40 accesses the power supply signal to the second bus interface 20, and adjusts the charging power of the second bus interface 20 to the first preset charging power when determining that the first power control chip 30 is not accessing the power supply signal, and notifies the first power control chip 30 to adjust the charging power of the first bus interface 10 to the second preset charging power.
Optionally, the first preset charging power is greater than the second preset charging power. In other embodiments, the first preset charging power is less than the second preset charging power.
The present utility model further proposes a power control circuit of another embodiment, which differs from the above-described embodiment: the power control chip includes: the control chip is respectively connected with the corresponding bus interface and the other power control chip and is used for sending a power adjustment signal to the other power control chip when the corresponding bus interface is connected with the power supply signal, and the other power control chip generates a feedback signal to the control chip based on the power adjustment signal; the power management chip is respectively connected with the corresponding bus interface and the control chip and is used for adjusting the charging power of the corresponding bus interface based on the feedback signal; the feedback signal comprises an enable adjustment signal or a disable adjustment signal, and if the other bus interface is not connected with the power supply signal, the other power control chip generates the enable adjustment signal based on the power adjustment signal, and the power management chip adjusts the charging power of the corresponding bus interface to the first preset charging power based on the enable adjustment signal; if the other bus interface is connected with a power supply signal, the other power control chip generates the prohibition adjustment signal based on the power adjustment signal, the power management chip adjusts the charging power of the corresponding bus interface to the first configuration power based on the prohibition adjustment signal, and the other power control chip adjusts the charging power of the corresponding bus interface to the second configuration power; wherein the first configuration power is one of the first preset charging power and the second preset charging power, and the second configuration power is the other of the first preset charging power and the second preset charging power.
Specifically, as shown in fig. 2, fig. 2 is a schematic structural diagram of another embodiment of the power control circuit of the present utility model. The first power control chip 30 includes a first control chip and a first power management chip. The first control chip is respectively connected with the first bus interface 10 and the second power control chip 40, and is used for sending a first power adjustment signal to the second power control chip 40 when the first bus interface 10 is connected with a power supply signal, and the second power control chip 40 generates a first feedback signal to the first control chip based on the first power adjustment signal; the first power management chip is respectively connected with the first bus interface 10 and the first control chip and is used for adjusting the charging power of the first bus interface 10 based on the first feedback signal; the first feedback signal includes an enable adjustment signal or a disable adjustment signal, and if the second bus interface 20 is not connected to the power supply signal, the second power control chip 40 generates the enable adjustment signal based on the first power adjustment signal, and the first power management chip adjusts the charging power of the first bus interface 10 to a first preset charging power based on the enable adjustment signal; if the second bus interface 20 is connected to the power supply signal, the second power control chip 40 generates a disable adjustment signal based on the first power adjustment signal, the first power management chip adjusts the charging power of the first bus interface 10 to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the second bus interface 20 to the second configuration power.
The first control chip sends a first power adjustment signal to the second power control chip 40 when the first bus interface 10 is connected to the power supply signal, and the second power control chip 40 generates a first feedback signal to the first control chip based on the first power adjustment signal. The first power management chip adjusts the charging power of the first bus interface 10 based on the first feedback signal.
If the second bus interface 20 is not connected to the power supply signal and the first bus interface 10 is connected to the power supply signal, the second power control chip 40 generates an enable adjustment signal based on the first power adjustment signal, and the first power management chip adjusts the charging power of the first bus interface 10 to a first preset charging power based on the enable adjustment signal. If the second bus interface 20 is connected to the power supply signal and the first bus interface 10 is also connected to the power supply signal, the second power control chip 40 generates a disable adjustment signal based on the first power adjustment signal, the first power management chip adjusts the charging power of the first bus interface 10 to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the second bus interface 20 to the second configuration power. At this time, the charging power of the first bus interface 10 and the second bus interface 20 does not need to be adjusted, and the first bus interface 10 and the second bus interface 20 are charged according to the first configuration power and the second configuration power which are set inherently.
Optionally, the two bus interfaces include a TypeC interface, that is, the first bus interface 10 and the second bus interface 20 are TypeC interfaces.
The typeC interface is a connection interface of a universal serial bus (Universal Serial Bus, USB) interface, and can support functions of USB standard such as charging, data transmission, display and output.
In an application scenario, as shown in fig. 3, fig. 3 is a specific structural schematic diagram of the embodiment of fig. 2, in this embodiment, the first bus interface 10 is a front TypeC interface, and the second bus interface 20 is a side TypeC interface. The power supply signal can be accessed.
In an application scenario, as shown in fig. 3, the first control chip in this embodiment is a PD IC-1, and the first power management chip is a PMU power chip-1 connected to the PD IC-1. The power driving chip (Power Delivery Integrated Circuit Chip, PD IC) uses the fast charge protocol, PD IC-1 improves the transmission direction of the electric signal through USB cable line and radio frequency connector, expand the working capacity of USB cable line in the power supply system. Can provide higher operating voltage and current amount, has higher output power, and can randomly change the transmission direction of the electric signal. The power management unit (Power Management Unit, PMU) is a highly integrated, power management scheme for portable applications that enables higher power conversion efficiency, lower power consumption, and fewer component counts to accommodate smaller circuit board space.
The PD IC-1 is connected to the pre-TypeC interface and the second power control chip 40, respectively, and is configured to send a first power adjustment signal to the second power control chip 40 when the pre-TypeC interface is connected to a power supply signal, and the second power control chip 40 generates a first feedback signal to the PD IC-1 based on the first power adjustment signal. The PMU power chip-1 is connected with the front-end type C interface and the PD IC-1 respectively and is used for adjusting the charging power of the front-end type C interface based on the first feedback signal. If the side TypeC interface is not connected to the power supply signal, the second power control chip 40 generates an enable adjustment signal based on the first power adjustment signal, and the PMU power chip-1 adjusts the charging power of the front TypeC interface to a first preset charging power based on the enable adjustment signal; if the side TypeC interface is connected to the power supply signal, the second power control chip 40 generates a disable adjustment signal based on the first power adjustment signal, the PMU power chip-1 adjusts the charging power of the front TypeC interface to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the side TypeC interface to the second configuration power.
Optionally, as shown in fig. 2, the second power control chip 40 includes a second control chip and a second power management chip. The second control chip is respectively connected with the second bus interface 20 and the first control chip, and is used for sending a second power adjustment signal to the first control chip when the second bus interface 20 is connected with the power supply signal, and the first power control chip 30 generates a second feedback signal to the second control chip based on the second power adjustment signal; the second power management chip is respectively connected with the second bus interface 20 and the second control chip and is used for adjusting the charging power of the second bus interface 20 based on a second feedback signal; the second feedback signal includes an enable adjustment signal or a disable adjustment signal, and if the first bus interface 10 is not connected to the power supply signal, the first power control chip 30 generates the enable adjustment signal based on the second power adjustment signal, and the second power management chip adjusts the charging power of the second bus interface 20 to the first preset charging power based on the enable adjustment signal; if the first bus interface 10 is connected to the power supply signal, the first power control chip 30 generates a disable adjustment signal based on the second power adjustment signal, the second power management chip adjusts the charging power of the second bus interface 20 to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the first bus interface 10 to the second configuration power.
The second control chip sends a second power adjustment signal to the first control chip when the second bus interface 20 is connected to the power supply signal, and the first power control chip 30 generates a second feedback signal to the second control chip based on the second power adjustment signal. The second power management chip adjusts the charging power of the second bus interface 20 based on the second feedback signal.
If the first bus interface 10 is not connected to the power supply signal and the second bus interface 20 is connected to the power supply signal, the first power control chip 30 generates an enable adjustment signal based on the second power adjustment signal, and the second power management chip adjusts the charging power of the second bus interface 20 to the first preset charging power based on the enable adjustment signal. If the first bus interface 10 is connected to the power supply signal and the second bus interface 20 is also connected to the power supply signal, the first power control chip 30 generates a disable adjustment signal based on the second power adjustment signal, the second power management chip adjusts the charging power of the second bus interface 20 to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the first bus interface 10 to the second configuration power. At this time, the charging power of the first bus interface 10 and the second bus interface 20 also need not be adjusted.
In an application scenario, as shown in fig. 3, the second control chip in this embodiment is a PD IC-2, and the second power management chip is a PMU power chip-2 connected to the PD IC-2.
The PD IC-2 is connected to the side TypeC interface and the above PD IC-1, respectively, and is configured to send a second power adjustment signal to the PD IC-1 when the side TypeC interface is connected to the power supply signal, and the first power control chip 30 generates a second feedback signal to the PD IC-2 based on the second power adjustment signal. And the PMU power chip-2 is respectively connected with the side type C interface and the PD IC-2 and is used for adjusting the charging power of the side type C interface based on the second feedback signal. If the pre-type C interface is not connected to the power supply signal, the first power control chip 30 generates an enable adjustment signal based on the second power adjustment signal, and the PMU power chip-2 adjusts the charging power of the PD IC-2 to a first predetermined charging power based on the enable adjustment signal. If the pre-type c interface is connected to the power supply signal, the first power control chip 30 generates a disable adjustment signal based on the second power adjustment signal, the PMU power chip 2 adjusts the charging power of the side-type c interface to the first configuration power based on the disable adjustment signal, and the second power control chip 40 adjusts the charging power of the pre-type c interface to the second configuration power.
For example, two GPIOs (GPIO 1, GPIO 2) may be used as communication bridges between the PD IC-1 and the PD IC-2, and the maximum charging power that can be reached by the default recorded firmware is 65W on the PD IC-1 of the front type C interface or the PD IC-2 of the side type C interface, and the setting is performed in the firmware of the PD IC-1 and the PD IC-2. If any TypeC interface is accessed to the external device, the PD IC corresponding to the TypeC interface carries out CC communication. If the front-end TypeC interface is accessed to the external device, CC communication is carried out with the PD IC-1. PD IC-1 provides indication information to PD IC-2 through GPIO2, informs PD IC-1 to charge according to 65W, PD IC-2 judges and records the indication information of GPIO2, and informs PD IC-1 through GPIO1 that the operation can be executed. After the PD IC-1 receives the executable information, the charging power of the front-end TypeC interface is set to be 65W.
In this process, the PD IC-2 records the indication information of the GPIO2, where the indication information indicates that there is a TypeC interface already providing the maximum charging power to the external device, then the PD IC-2 automatically reduces the maximum charging power to 15W, and then if there are other external devices accessing the PD IC-2, only 15W of charging power can be used.
Similarly, if the side TypeC interface corresponding to the PD IC-2 is accessed to the external device first, the front TypeC interface corresponding to the PD IC-1 correspondingly reduces the charging power to 15W according to the same operation logic.
If the external device connected to the PD IC-1 is disconnected, after the PD IC-1 completes CC communication, the indication information of the GPIO2 is changed, and the PD IC-2 receives the indication information of the changed GPIO2, which indicates that the front type C interface corresponding to the PD IC-1 is disconnected from the external device, and the maximum charging power of the side type C interface can be adjusted to be 65W.
When the PD IC-1 and the PD IC-2 are simultaneously connected with the external equipment, which external equipment is connected first cannot be distinguished, at the moment, according to default setting, the maximum charging power of the front type C interface corresponding to the PD IC-1 is set to 65W, the maximum charging power of the side type C interface corresponding to the PD IC-2 is set to 15W, and the problem that the power supply load is overlarge due to the fact that the maximum charging power of the two type C interfaces is simultaneously increased to 65W is avoided.
Through the communication coordination of the PD IC-1 and the PD IC-2, the first notebook can always obtain the maximum charging power according to the use habit of the user, the master control is not needed, and the communication coordination efficiency is improved. The PD IC-1 and the PD IC-2 are bridged by two GPIOs as communication. In the case of more than two PD ICs, multiple GPIOs or other communication interfaces may be used to communicate, and embodiments are similar to the communication coordination of PD IC-1 and PD IC-2 described above.
Optionally, as shown in fig. 2, the power distribution circuit further includes a first conversion circuit and a second conversion circuit. The first conversion circuit is connected to a bus interface (e.g. the first bus interface 10) and the main chip 50, respectively, and is configured to convert a power supply signal of the first bus interface 10, so as to charge the main chip 50 by using the converted electrical signal. The second conversion circuit is connected to the other bus interface (e.g. the second bus interface 20) and the main chip 50, respectively, and is configured to convert a power supply signal of the second bus interface 20, so as to charge the main chip 50 by using the converted electrical signal.
Optionally, the first conversion circuit and the second conversion circuit are both digital interfaces.
The digital interface may be TypeC to HDMI, and may output to electronic devices such as a mobile phone, a tablet, a computer, etc. through the TypeC interface, so that an input signal may be converted into a signal of a high-definition multimedia interface (High Definition Multimedia Interface, HDMI).
In an application scenario, as shown in fig. 3, in the present embodiment, the first conversion circuit is TypeC to HDMI-1, and the second conversion circuit is TypeC to HDMI-2. The TypeC to HDMI-1 is connected to the pre-TypeC interface and the main chip 50, and is capable of converting a power supply signal of the pre-TypeC interface, so as to charge the main chip 50 by using the converted electrical signal. The typeC to HDMI-1 is connected with the side typeC interface and the main chip 50 respectively, and can convert the power supply signal of the side typeC interface so as to charge the main chip 50 by using the converted electric signal. The TypeC to HDMI-2 is connected to the side TypeC interface and the main chip 50, respectively, and is configured to convert a power supply signal of the side TypeC interface, so as to charge the main chip 50 by using the converted electrical signal.
Optionally, the main chip 50 is connected to the control chip by using a two-wire synchronous serial bus, and is configured to configure a first preset charging power and a second preset charging power for the corresponding bus interface through the control chip.
Specifically, the main chip 50 is connected to the first control chip and the second control chip by using a two-wire synchronous serial bus, and is configured to configure a first preset charging power and a second charging power for the first bus interface 10 through the first control chip, and is configured to configure a first preset charging power and a second charging power for the second bus interface 20 through the second control chip.
The main chip 50 may utilize a binary synchronous serial bus (Inter-Integrated Circuit, I2C) to configure the first and second predetermined charging powers for the first and second bus interfaces 10 and 20.
In an application scenario, as shown in fig. 3, the binary synchronous serial bus is I2C, the main chip 50 is connected with the PD IC-1 and the PD IC-2 by using the I2C, and can configure the first preset charging power and the second charging power for the front TypeC interface through the PD IC-1, and can configure the first preset charging power and the second charging power for the side TypeC interface through the PD IC-2. PD IC-1 and PD IC-2 may also be connected to PMU power chip-1 and PMU power chip-2 using I2C, respectively.
In order to solve the above-mentioned problems, the present utility model further provides an electronic device, as shown in fig. 4, fig. 4 is a schematic structural diagram of an embodiment of the electronic device of the present utility model, where the electronic device of the present utility model includes a power distribution circuit 51, a main chip 50 and a main body 60. The power distribution circuit 51 and the main chip 50 are disposed on the main body 60. When the power distribution circuit 51 is connected to an external device, the power distribution of the two bus interfaces in the power distribution circuit 51 can be dynamically adjusted, i.e. the power of the charging port can be dynamically distributed, and the flexibility of the use of the charging port can be improved.
The specific structure and operation principle of the power distribution circuit 51 can be referred to the above embodiments.
Optionally, the body 60 includes a circuit board on which the power distribution circuit 51 and the main chip 50 are integrated.
Optionally, the electronic device further comprises a display circuit connected to the main chip 50 for displaying image information of the main chip 50.
In other embodiments, the electronic device may be a tablet, or may be other intelligent electronic devices. The display circuit can be a flat panel display screen or other intelligent electronic equipment display screens. The display circuit is capable of displaying image information of the main chip 50.
Optionally, two bus interfaces are disposed at the front and side of the body 60, respectively, that is, as a front interface and a side interface of the electronic device.
In describing embodiments of the present utility model, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present utility model will be understood in detail by those of ordinary skill in the art.
In embodiments of the utility model, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The foregoing description is only illustrative of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present utility model.
Claims (10)
1. A power distribution circuit for an electronic device, the electronic device including the power distribution circuit, a main chip, and a body, the power distribution circuit and the main chip being disposed on the body, the power distribution circuit comprising:
the two bus interfaces are positioned at different positions of the body;
the two power control chips are arranged one by one with the two bus interfaces, and are respectively connected with the corresponding bus interfaces and the main chip;
the two power control chips are also connected with each other, one power control chip is connected with a power supply signal at the corresponding bus interface, and when the other power control chip is determined that the other power control chip is not connected with the power supply signal, the charging power of the corresponding bus interface is adjusted to be a first preset charging power, and the other power control chip is informed to adjust the charging power of the corresponding bus interface to be a second preset charging power;
the first preset charging power is different from the second preset charging power.
2. The power distribution circuit of claim 1 wherein the power control chip comprises:
the control chip is respectively connected with the corresponding bus interface and the other power control chip and is used for sending a power adjustment signal to the other power control chip when the corresponding bus interface is connected with the power supply signal, and the other power control chip generates a feedback signal to the control chip based on the power adjustment signal;
the power management chip is respectively connected with the corresponding bus interface and the control chip and is used for adjusting the charging power of the corresponding bus interface based on the feedback signal;
the feedback signal comprises an enable adjustment signal or a disable adjustment signal, and if the other bus interface is not connected with the power supply signal, the other power control chip generates the enable adjustment signal based on the power adjustment signal, and the power management chip adjusts the charging power of the corresponding bus interface to the first preset charging power based on the enable adjustment signal; if the other bus interface is connected with a power supply signal, the other power control chip generates the prohibition adjustment signal based on the power adjustment signal, the power management chip adjusts the charging power of the corresponding bus interface to the first configuration power based on the prohibition adjustment signal, and the other power control chip adjusts the charging power of the corresponding bus interface to the second configuration power;
wherein the first configuration power is one of the first preset charging power and the second preset charging power, and the second configuration power is the other of the first preset charging power and the second preset charging power.
3. The power distribution circuit of claim 1 wherein the bus interface is a TypeC interface.
4. The power distribution circuit of claim 1, further comprising:
the first conversion circuit is respectively connected with the bus interface and the main chip and is used for converting a power supply signal of the bus interface so as to charge the main chip by utilizing the converted electric signal;
and the second conversion circuit is respectively connected with the other bus interface and the main chip and is used for converting the power supply signal of the other bus interface so as to charge the main chip by utilizing the converted electric signal.
5. The power distribution circuit of claim 4 wherein the first and second conversion circuits are digital interfaces.
6. The power distribution circuit of claim 2 wherein the master chip is coupled to the control chip using a two-wire synchronous serial bus for configuring the first preset charging power and the second preset charging power for the corresponding bus interface via the control chip.
7. An electronic device, comprising;
the power distribution circuit of any one of claims 1 to 6;
a main chip;
the power distribution circuit and the main chip are arranged on the body.
8. The electronic device of claim 7, wherein the body comprises a circuit board, the power distribution circuit and the main die being integrated on the circuit board.
9. The electronic device of claim 7, wherein the two bus interfaces are disposed on a front and side of the body, respectively.
10. The electronic device of claim 8, further comprising a display circuit coupled to the main chip for displaying image information of the main chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223438549.8U CN219554609U (en) | 2022-12-21 | 2022-12-21 | Power distribution circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223438549.8U CN219554609U (en) | 2022-12-21 | 2022-12-21 | Power distribution circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219554609U true CN219554609U (en) | 2023-08-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223438549.8U Active CN219554609U (en) | 2022-12-21 | 2022-12-21 | Power distribution circuit and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN219554609U (en) |
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2022
- 2022-12-21 CN CN202223438549.8U patent/CN219554609U/en active Active
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