CN219534533U - Silicon controlled rectifier device - Google Patents

Abstract

The utility model discloses a silicon controlled rectifier device. The silicon controlled rectifier device includes a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer. The first silicon outer layer is coupled to the first silicon intermediate layer. The first silicon intermediate layer is coupled to the second silicon intermediate layer. The second silicon intermediate layer is coupled to the second silicon outer layer. The silicon controlled rectifier device further includes a cathode terminal coupled to the first silicon outer layer and a gate terminal coupled to the first silicon intermediate layer. One or more third silicon layers are coupled to the second silicon outer layer. The anode terminal is coupled to one or more third silicon layers and the second silicon outer layer.

Description

Silicon controlled rectifier device

Technical Field

The present disclosure relates generally to the field of solid state current control devices, and more particularly to unidirectional silicon controlled rectifiers.

Background

A Silicon Controlled Rectifier (SCR) includes four layers and provides current control. It may be referred to as a type of thyristor. Some silicon controlled rectifiers are used in systems where high power and/or high voltage needs to be controlled. For example, SCR may be used in medium to high voltage Alternating Current (AC) power control systems (e.g., power regulators, motor controllers, etc.). Further, SCR may be used to rectify high power AC signals in high voltage Direct Current (DC) power transmission. Welding and other similar processes rely on SCR for current control. SCR can also be used as a switch.

Some SCRs may be designed to be unidirectional, wherein current is conducted in only one direction. Other SCRs may be bi-directional, allowing current to flow in either direction. Positive current into the gate of the SCR may trigger the operation of the SCR, unlike a triode for alternating current (TRIAC), which may be triggered using positive or negative current applied to its gate. However, conventional SCR is affected by an increase in PNP current gain and an increase in current leakage at high temperatures, which increases noise and reduces SCR performance.

Disclosure of Invention

The following summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In some embodiments, the present subject matter relates to a Silicon Controlled Rectifier (SCR) device. The SCR may include a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer. The first silicon outer layer may be coupled to the first silicon intermediate layer. The first silicon intermediate layer may be coupled to the second silicon intermediate layer. The second silicon intermediate layer may be coupled to the second silicon outer layer. The SCR may also include a cathode terminal coupled to the first silicon outer layer and a gate terminal coupled to the first silicon intermediate layer. One or more third silicon layers may be coupled to the second silicon outer layer. The anode terminal may be coupled to one or more third silicon layers and the second silicon outer layer.

In some embodiments, the present subject matter may include one or more of the following optional features. The first silicon outer layer may be coupled to the first silicon intermediate layer via a first junction. The first silicon intermediate layer may be coupled to the second silicon intermediate layer via a second junction. The second silicon intermediate layer may be coupled to the second silicon outer layer via a third junction.

In some embodiments, the second silicon outer layer may be configured to be shortened using one or more predetermined dimensions to produce a shortened second silicon outer layer. One or more third silicon layers may be coupled to the shortened second silicon outer layer. The anode terminal may be coupled to one or more third silicon layers and the shortened second silicon outer layer.

In some embodiments, the one or more predetermined dimensions may include a length of the second silicon outer layer. The length may be about three (3) millimeters.

In some embodiments, the device may be at least one of the following: PNPN silicon controlled rectifier structure, NPNP silicon controlled rectifier structure, and any combination thereof.

In some embodiments, the first silicon outer layer may be an n+ layer. The first silicon intermediate layer may be a P layer. The second silicon interlayer may be an N-layer. The second silicon outer layer may be a P layer. The one or more third silicon layers may be n+ layers.

In some embodiments, one or more third silicon layers may be coupled to the second silicon intermediate layer.

In some embodiments, the present subject matter relates to a method for manufacturing a silicon controlled rectifier device. The method may include providing a first silicon outer layer, a second silicon outer layer, a first silicon intermediate layer, and a second silicon intermediate layer; coupling the first silicon outer layer to the first silicon intermediate layer via a first junction, coupling the first silicon intermediate layer to the second silicon intermediate layer via a second junction, and coupling the second silicon intermediate layer to the second silicon outer layer via a third junction; coupling the cathode terminal to the first silicon outer layer and the gate terminal to the first silicon intermediate layer; shortening the second silicon outer layer using one or more predetermined dimensions to produce a shortened second silicon outer layer; coupling one or more third silicon layers to the shortened second silicon outer layer; and coupling the anode terminal to the one or more third silicon layers and the shortened second silicon outer layer.

The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate some aspects of the subject matter disclosed herein and, together with the description, help explain some principles associated with the disclosed embodiments. In the drawings of which there are shown,

FIG. 1 illustrates an exemplary silicon controlled rectifier;

FIG. 2 illustrates another exemplary silicon controlled rectifier;

FIG. 3 illustrates an exemplary silicon controlled rectifier according to some embodiments of the present subject matter; and

fig. 4 illustrates an exemplary process according to some embodiments of the present subject matter.

The figures are not necessarily drawn to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict exemplary embodiments of the present subject matter, and therefore should not be considered as limiting the scope. In the drawings, like numbering represents like elements.

Moreover, certain elements of some of the figures may be omitted and/or not shown to scale for clarity of illustration. The cross-sectional view may be in the form of a "slice" and/or "near-sighted" cross-sectional view, omitting certain background lines that would otherwise be visible in a "true" cross-sectional view for clarity of illustration. Moreover, some reference numerals may be omitted from some of the figures for clarity.

Detailed Description

Various methods in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of systems and methods are shown. The devices, systems, components, etc. may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present subject matter to those skilled in the art.

To address these and other potential drawbacks of currently available solutions, one or more embodiments of the present subject matter relate to methods, systems, articles of manufacture, and the like, among other possible advantages, to provide a unidirectional silicon controlled rectifier device that can be configured to provide current control while reducing PNP current gain and current leakage at high temperatures, thereby improving noise immunity of the device.

Silicon Controlled Rectifiers (SCR) are typically made of silicon and are used to rectify or convert Alternating Current (AC) to Direct Current (DC). SCR can be used to regulate power, invert, and perform various other functions. SCR can handle high currents and voltages, which is useful in a variety of industrial applications.

The SCR includes three terminals, anode (a), cathode (K) and gate (G). The SCR may be turned on or off by controlling one or more bias conditions and/or inputs to the gate terminal. The SCR is configured as a four-layer semiconductor device forming an NPNP or PNPN structure. In view of these structures, the SCR further includes three junctions J1, J2, and J3. The anode terminal is the positive electrode and is coupled to the P layer of the structure. The cathode terminal is a negative electrode and is coupled to the N-layer. Finally, the gate terminal is a control terminal.

The SCR can operate in one or more different modes depending on the polarity of the voltage and the input to the gate terminal. The operating modes of the SCR may include a forward blocking mode, a forward conduction mode, and a reverse blocking mode. In the forward blocking mode, a positive voltage is applied to the anode terminal and a negative voltage is applied to the cathode terminal. The gate terminal is open-circuited and has no input signal applied to it. Upon application of a voltage, junctions J1 and J3 become forward biased and junction J2 becomes reverse biased. Since J2 is reverse biased, the width of the depletion region increases, preventing conduction and allowing a small amount of current to flow from J1 to J3.

In the forward blocking mode, junction J2 becomes depleted due to avalanche breakdown resulting from the application of an increased amount of voltage to the SCR breakdown voltage. As a result of the avalanche breakdown, the SCR will allow current to flow through it, causing the SCR to be forward biased, otherwise no current flows through the SCR.

In the forward conduction mode, the SCR is in a conducting state and thus conducts current therethrough. The SCR may conduct current when the applied forward bias voltage increases beyond the breakdown voltage or a positive voltage is applied to the gate terminal. When a forward bias voltage is applied between the anode terminal and the cathode terminal, the J2 junction is depleted due to avalanche breakdown, thereby causing the SCR to conduct; however, this also results in a reduction of SCR lifetime.

In the reverse blocking mode, a positive voltage is applied to the negative cathode terminal, and a negative voltage is applied to the positive anode terminal, while no signal is applied to the gate terminal. Application of such a signal causes the J1 and J3 junctions to become reverse biased and the J2 junction to become forward biased. Thus, no current flows through the SCR. However, a small amount of current leakage can occur due to the drifting charge carriers in the forward biased J2 junction, but this amount of leakage is insufficient to turn the SCR on.

Fig. 1 illustrates an exemplary Silicon Controlled Rectifier (SCR) 100.SCR 100 may include a four-layer structure that includes outer N-layer 102 and outer P-layer 108, and intermediate P-layer 104 and intermediate N-layer 106. The outer layers 102, 108 may be heavily doped and the intermediate layers 104, 106 may be lightly doped. Layer 108 and layer 106 may be separated by junction J1 107. Layer 106 and layer 104 may be separated by junction J2 105. Layer 104 and layer 102 may be separated by junction J3 103.

SCR 100 may also include an anode terminal or electrode 110, which may be a positive terminal, connected to P-layer 108. A cathode terminal or electrode 114, which may be a negative terminal, may be connected to the N-layer 102, which in turn may be a positive terminal. A gate terminal or electrode 112, which may be a positive terminal, may be connected to the intermediate layer P104. The heavy doping of the outer layers 102, 108 may allow for connection of the terminals/electrodes 114, 110, respectively.

As described above, to cause the SCR to conduct current, the forward bias voltage between the anode terminal 110 and the cathode terminal 114 may be increased beyond the breakdown voltage of the SCR, and/or a positive voltage may be applied to the gate terminal 112. In the first case, the free electrons in the anode terminal 110 and holes in the cathode terminal 114 can gain a large amount of energy and accelerate to a higher speed. Such energetic accelerated electrons can collide with atoms and generate additional (e.g., millions) of charge carriers. This causes the depletion region in junction J2 105 to break down, allowing current to flow through SCR 100, corresponding to the on state of SCR 100. As described above, this may result in significant losses and reduce the operational life of the SCR 100.

In the second case, a positive voltage (e.g., a small voltage) may be applied to the gate terminal 112. This causes the gate terminal 112 to become forward biased, narrowing the depletion region at junction J2 105. As such, applying a positive voltage between gate terminal 112 and between anode terminal 110 and cathode terminal 114 may be configured to allow current to flow through SCR 100 and through the depletion region at junction J2 105.

Fig. 2 illustrates another exemplary Silicon Controlled Rectifier (SCR) 200. Similar to SCR 100, SCR 200 may include a four-layer structure having an outer n+ layer 202 and an outer P layer 208, and an intermediate P layer 204 and an intermediate N-layer 206. As discussed above (not shown in FIG. 2), the layers 202-208 may be separated by respective junctions J1-J3.

SCR 200 may also include an anode terminal or electrode 210, which may be connected to P-layer 208.SCR 200 may also include a cathode terminal or electrode 214, which may be connected to n+ layer 202. Further, a gate terminal or electrode 212 of SCR 200 may be connected to intermediate P-layer 204.

Fig. 2 shows an exemplary structure of a conventional silicon controlled rectifier. In particular, in SCR 200, outer P layer 209 may be configured to extend the entire length of anode terminal 210. As such, such existing structures of SCR 200 may be prone to increased PNP current gain. Furthermore, during operation, SCR 200 may be susceptible to current leakage at high temperatures. This in turn reduces the noise immunity and performance of the SCR 200.

Fig. 3 illustrates an exemplary unidirectional Silicon Controlled Rectifier (SCR) 300 according to some embodiments of the present subject matter. As shown in fig. 3, SCR 300 may include a multi-layer structure. It may include an outer positive n+ layer 302 coupled to an intermediate P layer 304 via, for example, a junction (not shown in fig. 3). The intermediate P layer 304 may be coupled to the intermediate negative layer N-306 via, for example, another junction (not shown in fig. 3). The intermediate N-layer 306 may be coupled to the outer P layer 308 and the one or more outer positive n+ layers 311 (a, b) via, for example, yet another junction (not shown in fig. 3).

The positive n+ layer 311 (a, b) may be provided in combination with the external P layer 308. Layer 311 may be configured to shorten the length of outer P-layer 308. Each layer 311 (a, b) may be configured to be smaller than the length of the outer layer 308. The layers 311 (a, b) may have equal and/or different lengths. The length of each layer 311a and 311b may be determined according to the particular application of SCR 300. In some exemplary non-limiting embodiments of the present subject matter, each layer 311 (a, b) may be approximately 3 millimeters long. It will be appreciated that layer 311 may have any other desired dimensions.

Further, in some exemplary embodiments, one or more of the layers 311 (a, b) may have a thickness that is less than the thickness of the outer P layer 308. Alternatively or additionally, the thickness of layer 311 may be the same as and/or greater than the thickness of outer P-layer 308.

In some example embodiments, a single junction may be configured to separate the middle N-layer 306 from the outer P layer 308 and the n+ layer 311 (a, b). Alternatively or additionally, multiple junctions may be created to separate one or more or each of layers 308 and 311 (a, b) from layer 306 (e.g., one junction may separate layers 306 and 308, another junction may separate layer 306 from 311a, and/or yet another junction may separate layers 306 from 311 b).

In some embodiments, SCR 300 may include a cathode terminal or electrode 314, which may be coupled to external n+ layer 302. The outer layer 302 may have a length that is greater than the length of the cathode terminal 314. Alternatively or additionally, the length of the outer layer 302 may be the same as and/or shorter than the length of the cathode terminal 314.

SCR 300 may also include a gate terminal or electrode 312. The gate terminal 312 may be coupled to the intermediate P-layer 304. As shown in fig. 3, the intermediate P layer 304 may be configured to exceed the entire length of the outer n+ layer 302. Alternatively or additionally, the length of the intermediate P-layer 304 may be any desired length.

Further, SCR 300 may include an anode terminal or electrode 310. The anode terminal 310 may be coupled to one or both of the n+ layers 311 (a, b) and the external P layer 308. In particular, the length of the anode terminal 310 may be greater than the length of the outer P layer 308. Further, the length of the anode terminal 310 may be configured to be long enough to accommodate at least a portion (and/or all) of the length of each of the n+ layers 311 (a, b).

In some embodiments, adding n+ layers 311 (a, b) on one or both sides of the outer P layer 308 in the SCR 300 and coupling them to the anode terminal 310 may be configured to improve the performance of the SCR 300 under various conditions. In particular, the combination of the n+ layer 311 and the outer P layer 308 may be configured to reduce current leakage typically associated with conventional SCR at higher operating temperatures. Further, the shortened P layer 308 and the added n+ layer 311 may be configured to be able to reduce PNP current gain during operation. Another advantage of the structure of SCR 300 of the present subject matter is that it can be configured to improve noise immunity of the device during operation.

In some embodiments, as described above, SCR 300 may be configured as a unidirectional SCR. It may be configured to operate according to one or more of the SCR operating principles discussed above.

Fig. 4 illustrates an exemplary process 400 for manufacturing a silicon controlled rectifier in accordance with some embodiments of the present subject matter. The process 400 may be used to assemble an SCR 300 such as that shown in fig. 3. At 402, a first silicon outer layer (e.g., outer n+ layer 302), a second silicon outer layer (e.g., outer P layer 308), a first silicon intermediate layer (e.g., intermediate P layer 304), and a second silicon intermediate layer (e.g., intermediate N-layer 306) may be provided.

At 404, the layers 302-308 may be configured to be coupled according to the structure of the SCR 300 shown in fig. 3. For example, without a particular order, the outer n+ layer 302 may be configured to be coupled to the intermediate P layer 304 via a first junction (not shown in fig. 3, but such as junction J3 103 shown in fig. 1). The intermediate P layer 304 may then be coupled to the intermediate N-layer 306 via a second junction (not shown in fig. 3, but such as junction J2 105 shown in fig. 1). The intermediate N-layer 306 may be coupled to the outer P-layer 308 via a third junction (not shown in fig. 3, but such as junction J1 107 shown in fig. 1).

At 406, a cathode terminal (e.g., cathode terminal 314) may be coupled to the first silicon outer layer (e.g., outer n+ layer 302). Additionally, a gate terminal (e.g., gate terminal 312) may be coupled to the first silicon intermediate layer (e.g., intermediate P layer 304).

At 408, the second silicon outer layer (e.g., layer 308) may be shortened using one or more predetermined dimensions to create or create a shortened second silicon outer layer. For example, the length of the second silicon outer layer may be shortened (and/or shortened to a predetermined length). It may be shortened on one or more sides, for example as shown in fig. 3. As a non-limiting example, the second silicon outer layer may be shortened by 3 millimeters on each side.

At 410, one or more third silicon layers (e.g., n+ layer 311 (a, b), as shown in fig. 3) may be coupled to the shortened second silicon outer layer. For example, a third silicon layer may be coupled on each side of the shortened second silicon outer layer, as shown in fig. 3.

At 412, an anode terminal (e.g., anode terminal 310 as shown in fig. 3) can be coupled to the shortened second silicon outer layer and the one or more third silicon layers. For example, the anode terminal 310 may be coupled to the shortened outer P layer 308 and the n+ layer 311, as shown in fig. 3.

It is to be appreciated that operations 402-412 may be performed in any desired order. The above procedure may also be equally applicable to NPNP and PNPN type structures, whereby the external P and/or external N layers (respectively) may be shortened for the purpose of inserting N and/or P layers (respectively) and/or any other type of layer.

The components and features of the above-described devices may be implemented using any combination of discrete circuits, application Specific Integrated Circuits (ASICs), logic gates and/or single chip architectures. Furthermore, the features of the device may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware, and/or software elements may be collectively or individually referred to herein as "logic" or "circuitry.

It should be appreciated that the exemplary devices shown in the above block diagrams may represent one functionally descriptive example of many potential implementations. Thus, the division, omission or inclusion of block functions depicted in the accompanying figures does not imply that the hardware components, circuits, software, and/or elements that perform these functions will necessarily be divided, omitted, or included in the embodiments.

Some embodiments may be described using the expression "one embodiment" or "an embodiment" along with their derivatives. The terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" (or a derivative thereof) in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, unless otherwise indicated, the above features are believed to be useful together in any combination. Thus, any of the features discussed separately may be used in combination with one another unless it is noted that the features are not compatible with one another.

It is emphasized that the abstract is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment. In the appended claims, the terms "including" and "in which" are used as the plain-english equivalents of the terms "comprising", "wherein", respectively. Furthermore, the terms "first," "second," "third," and the like are used merely as labels, and are not intended to impose numerical requirements on their objects. Furthermore, the use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Thus, the terms "comprising," "including," or "having," and variations thereof, are open-ended and are used interchangeably herein.

For convenience and clarity, terms such as "top," "bottom," "upper," "lower," "vertical," "horizontal," "lateral," "transverse," "radial," "inner," "outer," "left," and "right" may be used herein to describe relative placement and orientation of features and components, each with respect to the geometry and orientation of other features and components in the perspective, exploded perspective, and cross-sectional views provided herein. The terminology is not intended to be limiting and includes the words specifically mentioned, derivatives thereof and words of similar import.

The foregoing includes examples of the disclosed architecture. It is, of course, not possible to describe every conceivable combination of components and/or methodologies, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.

The foregoing description of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to the present utility model may claim the disclosed subject matter in a different manner and may generally include any one or more of the limitations disclosed or otherwise demonstrated herein in a variety of manners.

All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are only used for identification purposes to aid the reader's understanding of the present disclosure, and do not create limitations, particularly as to the position, orientation, or use of the present disclosure. Unless otherwise indicated, connective references (e.g., attachment, coupling, connection, and engagement) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements. Thus, a connective reference does not necessarily infer that two elements are directly connected and in fixed relation to each other.

Moreover, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but rather are used to distinguish one feature from another. The drawings are for illustrative purposes only and the sizes, positions, sequences and relative sizes reflected in the drawings may vary.

The scope of the present disclosure is not limited by the specific embodiments described herein. Indeed, various other embodiments and modifications of the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Accordingly, such other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, the present disclosure is described herein in the context of particular embodiments in a particular environment for a particular purpose. Those of ordinary skill in the art will recognize that the usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below are to be construed in view of the full breadth and spirit of the present disclosure as described herein.

Claims (17)

1. A silicon controlled rectifier device, comprising:

a first silicon outer layer;

a second silicon outer layer;

a first silicon interlayer;

a second silicon intermediate layer, wherein the first silicon outer layer is coupled to the first silicon intermediate layer, the first silicon intermediate layer is coupled to the second silicon intermediate layer, and the second silicon intermediate layer is coupled to the second silicon outer layer;

a cathode terminal coupled to the first silicon outer layer;

a gate terminal coupled to the first silicon interlayer;

one or more third silicon layers coupled to the second silicon outer layer; and

an anode terminal coupled to the one or more third silicon layers and the second silicon outer layer.

2. The silicon controlled rectifier device of claim 1 wherein the first silicon outer layer is coupled to the first silicon intermediate layer via a first junction.

3. The silicon controlled rectifier device of claim 2 wherein the first silicon interlayer is coupled to the second silicon interlayer via a second junction.

4. The silicon controlled rectifier device of claim 3 wherein the second silicon intermediate layer is coupled to the second silicon outer layer via a third junction.

5. The silicon controlled rectifier device of claim 1 wherein the second silicon outer layer is configured to be shortened using one or more predetermined dimensions to produce a shortened second silicon outer layer.

6. The silicon controlled rectifier device of claim 5 wherein the one or more third silicon layers are coupled to the shortened second silicon outer layer.

7. The silicon controlled rectifier device of claim 6 wherein the anode terminal is coupled to the one or more third silicon layers and the shortened second silicon outer layer.

8. The silicon controlled rectifier device of claim 5 wherein the one or more predetermined dimensions include a length of the second silicon outer layer.

9. The silicon controlled rectifier device of claim 8 wherein said length is about three (3) millimeters.

10. The silicon controlled rectifier device of claim 1 wherein the silicon controlled rectifier device is at least one of: PNPN silicon controlled rectifier structure, NPNP silicon controlled rectifier structure and arbitrary combination thereof.

11. The silicon controlled rectifier device of claim 1 wherein the first silicon outer layer is an n+ layer.

12. The silicon controlled rectifier device of claim 11 wherein the first silicon interlayer is a P layer.

13. The silicon controlled rectifier device of claim 12 wherein the second silicon intermediate layer is an N layer.

14. The silicon controlled rectifier device of claim 13 wherein the second silicon outer layer is a P layer.

15. The silicon controlled rectifier device of claim 14 wherein the one or more third silicon layers are n+ layers.

16. The silicon controlled rectifier device of claim 1 wherein the one or more third silicon layers are coupled to the second silicon interlayer.

17. A silicon controlled rectifier device, comprising:

a first silicon outer layer;

a second silicon outer layer;

a first silicon interlayer;

a second silicon intermediate layer, wherein the first silicon outer layer is coupled to the first silicon intermediate layer via a first junction, the first silicon intermediate layer is coupled to the second silicon intermediate layer via a second junction, and the second silicon intermediate layer is coupled to the second silicon outer layer via a third junction;

a cathode terminal coupled to the first silicon outer layer;

a gate terminal coupled to the first silicon interlayer;

one or more third silicon layers coupled to the second silicon outer layer; and

an anode terminal coupled to the one or more third silicon layers and the second silicon outer layer.