CN219497780U - Semiconductor packaging structure - Google Patents

Abstract

The utility model provides a semiconductor packaging structure, one embodiment of which comprises: a wafer including a non-active surface; the seed layer is arranged on the non-active surface; the heat dissipation piece is matched with the wafer to define a flow passage communicated with the outside; and the heat conduction piece is filled between the heat dissipation piece and the seed layer. In the manufacturing method, the seed layer is arranged on the non-active surface of the wafer, the heat dissipation piece is arranged above the non-active surface, and the heat conduction piece is formed by adopting a chemical deposition method to fill the space between the seed layer and the heat dissipation piece, so that heat generated by the wafer can be dissipated outwards through the seed layer arranged on the non-active surface, the heat conduction piece and the heat dissipation piece.

Description

Semiconductor packaging structure

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure.

Background

In a semiconductor package structure, in order to dissipate heat from a die (die), a thermal interface material (TIM, thermal Interface Materials) or an Adhesive (Adhesive) is generally disposed on a back surface of the die (or referred to as a non-active surface of the die), and then a heat sink is disposed on the thermal interface material or the Adhesive, so that the heat is dissipated from the die through the thermal interface material or the Adhesive and the heat sink.

However, even if a thermal interface material with high heat dissipation capability is used to achieve a better heat dissipation effect, due to the limitation of material characteristics, for example, the thermal conductivity coefficient of the known thermal interface material is still low, often only 3 to 5 watts, and after the product performance and power are improved in the future, the heat dissipation effect will be difficult to meet the requirements.

Disclosure of Invention

The utility model provides a semiconductor packaging structure, which comprises: a wafer including a non-active surface; the seed layer is arranged on the non-active surface; the heat dissipation piece is matched with the wafer to define a flow passage communicated with the outside; and the heat conduction piece is filled between the heat dissipation piece and the seed layer.

In some alternative embodiments, the semiconductor package structure further includes: at least two first supporting pieces which are arranged at intervals and are connected with the heat dissipation piece and the seed layer, and the first supporting pieces, the heat dissipation piece and the wafer are matched to define the flow channel.

In some alternative embodiments, the first support is embedded in the thermally conductive member.

In some alternative embodiments, the first support comprises a gel and a filler dispersed in the gel.

In some alternative embodiments, the filler abuts the heat sink and the seed layer.

In some alternative embodiments, the semiconductor package structure further includes: the substrate is arranged on one side of the wafer away from the heat dissipation piece so as to define the flow channel in a matching way.

In some alternative embodiments, the heat sink includes a thermally conductive portion that connects the thermally conductive member.

In some alternative embodiments, the heat sink further includes an extension extending from the thermally conductive portion toward the substrate and spaced apart from the substrate.

In some alternative embodiments, the semiconductor package structure further includes: at least two second support members connecting the extension portion of the heat sink and the substrate, the second support members, the heat sink and the die cooperatively define the flow channel.

In some alternative embodiments, the substrate has a ground line, and the semiconductor package further includes: and a conductive member connecting the heat dissipation member and the substrate ground line.

As described above, in order to improve the heat dissipation efficiency of the die in the conventional semiconductor package structure, the present utility model provides a semiconductor package structure, which includes: a wafer including a non-active surface; the seed layer is arranged on the non-active surface; the heat dissipation piece is matched with the wafer to define a flow passage communicated with the outside; and the heat conduction piece is filled between the heat dissipation piece and the seed layer. In the manufacturing method, a seed layer is arranged on the non-active surface (or called the back surface, the back surface and the passive surface of the wafer) of the wafer, then a heat dissipation piece is arranged above the non-active surface, and a heat conduction piece is formed by adopting a chemical deposition method to fill the space between the seed layer and the heat dissipation piece, so that heat generated by the wafer can be dissipated outwards through the seed layer, the heat conduction piece and the heat dissipation piece which are arranged on the non-active surface.

Drawings

Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

fig. 1 is a schematic structural view of a semiconductor package structure 10 according to one embodiment of the present utility model;

fig. 2 is a horizontal cross-sectional view of the semiconductor package 10 shown in fig. 1 along a broken line AA';

fig. 3 is an enlarged partial schematic view of a rectangular dashed frame in the semiconductor package structure 10 shown in fig. 1;

fig. 4 is a schematic structural view of a semiconductor package structure 40 according to an embodiment of the present utility model;

fig. 5 is a horizontal sectional view of the semiconductor package 40 shown in fig. 4 along a dotted line CC';

fig. 6 is a schematic structural view of a semiconductor package structure 60 according to one embodiment of the present utility model;

fig. 7 is a schematic structural view of a semiconductor package structure 70 according to one embodiment of the present utility model;

fig. 8 is a schematic structural view of a semiconductor package structure 80 according to one embodiment of the present utility model;

fig. 9-11 are schematic structural views of a semiconductor package 10 according to the present utility model at various stages of manufacture.

Reference numerals/symbol description:

11-wafer, 11 a-non-active surface, 112-seed layer, 12-heat sink, 121-heat conducting part, 122-extension part, 13-heat conducting part, 131-metal layer, 14-runner, 15-first support, 151-filler, 16-substrate, 161-grounding circuit, 17-second support, 18-conductive part, 19-chemical liquid inlet and outlet, 21-water-cooling or air-cooling heat sink.

Detailed Description

The following description of the embodiments of the present utility model is given by way of illustration and example only, and the technical problems and effects achieved by the present utility model will be readily apparent to those skilled in the art from the descriptions of the present utility model. It should be understood that the specific embodiments described herein are merely illustrative of the relevant technical solutions and are not limiting of the utility model. In addition, for convenience of description, only parts related to the related technical solutions are shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present utility model should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present utility model, so that the present utility model has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present utility model, should still fall within the scope covered by the technical content disclosed in the present utility model. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the utility model for which the utility model may be practiced, but rather for relative changes or modifications without materially altering the technical context.

In addition, the embodiments of the present utility model and the features in the embodiments may be combined with each other without collision. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor package structure 10 according to an embodiment of the utility model.

As shown in fig. 1, the semiconductor package structure 10 includes: wafer 11, seed layer 112, heat sink 12 and heat conductive member 13. Wherein:

the wafer 11 includes an inactive surface 11a, and the seed layer 112 is disposed on the inactive surface 11a. The heat conducting member 13 is filled between the heat dissipating member 12 and the seed layer 112, and the heat dissipating member 12 and the die 11 cooperate to define a flow channel 14 communicating with the outside.

Here, the wafer 11 may be various types of bare wafers (i.e., die), and the present utility model is not particularly limited thereto. For example, wafer 11 may be a logic chip, a memory chip, a microelectromechanical system (MEMS) chip, a radio frequency chip, or the like.

In some embodiments, the heat sink 12 may be a metal heat sink, such as a heat sink fin or a heat sink post, although the structure and shape of the heat sink 12 is not limited to the pattern shown in fig. 1.

In some embodiments, the heat sink 12 may be composed of a metallic material having a relatively high thermal conductivity, such as copper, aluminum, or the like.

The heat conductive member 13 is used for heat conduction, and may include various high heat conductive materials to improve heat dissipation efficiency, such as a metal material of copper, aluminum, or the like, and may be a non-metal material such as graphite or silicon, or the like. The thermal conductivity of the thermal conductive member 13 may be greater than the thermal conductivity of the thermal interface material.

Here, the flow path 14 is a passage through which chemical liquid flows in forming the heat conductive member 13 by a chemical deposition method. Here, the electroless deposition method may be, for example, a microfluidic chemical interconnect (MELI, microfluidic Electroless Interconnection) method.

The wafer 11 in the semiconductor package structure 10 can dissipate heat from the seed layer 112, the heat conducting member 13 and the heat dissipating member 12 disposed on the non-active surface 11a, and compared with the prior art in which the thermal interface material or the adhesive and the heat dissipating member are disposed on the back of the wafer, the thermal interface material or the adhesive is replaced by the seed layer 112 and the heat conducting member 13, and since the seed layer 112 is made of metal, the thermal conductivity of the metal is far greater than that of the thermal interface material or the adhesive (as known in the prior art, the thermal conductivity of the metal is often greater than 50 watts and even may reach 100 watts, and the thermal conductivity of the thermal interface material is generally between 3 watts and 5 watts), and the thermal conductivity of the heat conducting member 13 is far greater than that of the thermal interface material or the adhesive, so the thermal conductivity of the semiconductor package structure 10 is improved.

In some alternative embodiments, as shown in fig. 1, the semiconductor package structure 10 may further include: at least two first supporting members 15 disposed at intervals and connecting the heat sink 12 and the seed layer 112, the first supporting members 15, the heat sink 12 and the die 11 cooperate to define the flow channel 14. Here, the first support 15 may employ various materials for fixing the heat sink 12 to the seed layer 112 and having a heat conductive function. For example, the first support 15 may be various thermal interface materials or adhesives. In some alternative embodiments, the first support 15 may also be made of an adhesive material that does not have a heat conducting function.

In some alternative embodiments, the first support 15 may be embedded in the heat conducting member 13. For example, as shown in fig. 2, fig. 2 is a horizontal cross-sectional view of the semiconductor package 10 shown in fig. 1 along a broken line AA'. As can be seen from fig. 2, the semiconductor package 10 may include four first supporting members 15 disposed at four top corners of the heat conductive member 13. In the process of forming the heat conducting member 13 by using the chemical deposition method, the first supporting member 15, the heat dissipating member 12 and the wafer 11 cooperate to define the flow channel 14. Note that, the semiconductor package 10 shown in fig. 1 may be a longitudinal sectional view along a broken line BB' of the semiconductor package 10 shown in fig. 2.

In some alternative embodiments, please refer to fig. 3, fig. 3 is an enlarged partial schematic view of a rectangular dashed box in the semiconductor package structure 10 shown in fig. 1. As shown in fig. 3, the first support 15 may include a gel and a Filler 151 (i.e., filler) dispersed in the gel. Alternatively, the filler 151 may be metal particles, so that the metal particles in the filler 151 may increase the thermal conductivity of the first support 15, thereby increasing the thermal conductivity of the wafer 11.

In some alternative embodiments, the filler 151 in the gel of the first support 15 may abut against the heat sink 12 and the seed layer 112, respectively. That is, the vertical distance between the heat sink 12 and the seed layer 112 may be controlled by the size of the filler 151 in the gel of the first support 15, and thus the thickness of the heat conductive member 13 filled between the heat sink 12 and the seed layer 112 may be controlled. In other words, the size of the filler 151 in the gel of the first supporting member 15 may be selected according to actual needs during the manufacturing process, so as to control the thickness of the heat conducting member 13, and further, the time for forming the heat conducting member 13 may be controlled by controlling the thickness of the heat conducting member 13. For example, in forming the heat conductive member 13 by the chemical deposition method, the time for forming the heat conductive member 13 by the chemical deposition may be controlled by controlling the size of the filler 151 in the gel of the first support member 15. In some alternative embodiments, the filler 151 may have a diameter between 5 microns and 25 microns.

In some alternative embodiments, as shown in fig. 1, the semiconductor package structure 10 may further include: a substrate 16. The substrate 16 is disposed on a side of the die 11 away from the heat sink 12 to cooperatively define the flow channel 14.

In some alternative embodiments, as shown in fig. 1, the heat sink 12 may include a heat conductive portion 121 to which the heat conductive member 13 is connected.

In some alternative embodiments, as shown in fig. 1, the heat sink 12 may further include an extension 122 extending from the thermally conductive portion 121 toward the substrate 16 and spaced apart from the substrate 16.

In some alternative embodiments, as shown in fig. 1, the substrate 16 may have a ground line 161, and the semiconductor package 10 may further include a conductive member 18 connecting the extension 122 of the heat spreader 12 and the ground line 161 of the substrate 16. The conductive element 18 may, on the one hand, secure the heat sink 12 to the surface of the substrate 16; on the other hand, since the heat sink 12 is usually made of metal and has a signal shielding function, the heat sink 12 is electrically connected to the ground line 161 of the substrate 16 through the conductive member 18, and thus the heat sink 12 can realize a signal shielding effect (Shielding performance) on the chip 11.

Referring now to fig. 4 and 5, fig. 4 is a schematic structural view of a semiconductor package 40 according to an embodiment of the present utility model, and fig. 5 is a horizontal sectional view of the semiconductor package 40 shown in fig. 4 along a broken line CC'. The semiconductor package structure 40 as shown in fig. 4 is similar to the semiconductor package structure 10 shown in fig. 1, except that:

the semiconductor package structure 40 does not include the first supporting member 15, but includes at least two second supporting members 17, wherein the second supporting members 17 connect the extension portion 122 of the heat spreader 12 and the substrate 16, and the second supporting members 17, the heat spreader 12 and the die 11 cooperate to define the flow channel 14.

Here, the second support 17 may employ various materials for fixing the heat sink 12 to the substrate 16. For example, the second support 17 may be various adhesives or thermal interface materials. Here, the distance between the heat sink 12 and the seed layer 112 may be adjusted by adjusting the thickness of the second support 17, and thus the thickness of the heat conductive member 13 filled between the heat sink 12 and the seed layer 112 may be controlled. In other words, the thickness of the heat conductive member 13 can be controlled by selecting the thickness of the second supporting member 17 according to actual needs during the manufacturing process. Alternatively, the second support 17 may comprise a gel and a Filler (i.e. Filler, not shown in fig. 4) dispersed in the gel. Further, the thickness of the heat conductive member 13 can be controlled by controlling the size of the filler in the colloid of the second supporting member 17.

With respect to the semiconductor package structure 10, the semiconductor package structure 40 controls the thickness of the heat conductive member 13 not by the first support 15 connecting the heat sink 12 and the seed layer 112, but by the second support 17 connecting the extension 122 of the heat sink 12 and the substrate 16. In addition, since the first supporting member 15 is not disposed between the seed layer 112 and the heat dissipation member 12 in the semiconductor package structure 40, but only the heat conduction member 13, the heat conduction coefficient of the heat conduction member 13 is high, and the heat dissipation effect is better than that of the semiconductor package structure 10.

As can be seen from fig. 5, the semiconductor package structure 40 may include four second supporting members 17 disposed at four top corners of the heat sink 12. In the process of forming the heat conducting member 13 by using the chemical deposition method, the second supporting member 17, the heat dissipating member 12 and the wafer 11 cooperate to define the flow channel 14. Note that, the semiconductor package structure 40 shown in fig. 4 may be a longitudinal sectional view along a broken line DD' of the semiconductor package structure 40 shown in fig. 5.

Referring now to fig. 6, fig. 6 is a schematic structural diagram of a semiconductor package structure 60 according to one embodiment of the present utility model. The semiconductor package structure 60 as shown in fig. 6 is similar to the semiconductor package structure 10 shown in fig. 1, except that: the conductive element 18 is not included in the semiconductor package structure 60, i.e., the extension 122 of the heat spreader 12 does not contact the substrate 16. In this way, the flow and discharge of the chemical liquid can be more facilitated in the process of forming the heat conductive member 13 by the MELI method. In addition, after the semiconductor package structure 60 is formed into a finished product, air flow inside and outside the heat sink 12 is facilitated.

Referring now to fig. 7, fig. 7 is a schematic structural diagram of a semiconductor package structure 70 according to one embodiment of the present utility model. The semiconductor package structure 70 as shown in fig. 7 is similar to the semiconductor package structure 60 shown in fig. 6, except that: the semiconductor package structure 70 may further include a water-cooled or air-cooled heat sink 21 disposed outside the heat sink 12 to facilitate further heat dissipation.

Referring now to fig. 8, fig. 8 is a schematic diagram of a semiconductor package 80 according to one embodiment of the utility model. The semiconductor package structure 80 as shown in fig. 8 is similar to the semiconductor package structure 10 shown in fig. 1, except that: the heat sink 12 in the semiconductor package structure 80 includes only the heat conductive portion 121, and does not include the extension portion 122. It will be appreciated that the conductive element 18 is also not included. In this way, similar to the semiconductor package structure 60, the flow and discharge of the chemical liquid can be more facilitated in the process of forming the heat conductive member 13 using the MELI method. In addition, after the semiconductor package 80 is formed into a finished product, air flow inside and outside the heat sink 12 is facilitated.

Optionally, the semiconductor package 80 may further include a water-cooled or air-cooled heat sink (not shown in fig. 8) disposed outside the heat sink 12 to facilitate further heat dissipation.

Referring now to fig. 9-11, fig. 9-11 are schematic illustrations of a semiconductor package 10 according to the present utility model at various stages of fabrication.

The figures have been simplified in order to facilitate a better understanding of aspects of the present utility model.

Referring to fig. 9, a seed layer 112 is formed on the inactive surface 11a of the wafer 11.

Here, the seed layer 112 may be formed on the inactive face 11a of the wafer 11 before the wafer 11 is bonded to the substrate 16, or the seed layer 112 may be formed on the inactive face 11a of the wafer 11 after the wafer 11 is bonded to the substrate 16. For example, the seed layer 112 may be formed by physical vapor deposition or chemical vapor deposition, and is not particularly limited herein.

Referring to fig. 10, a first support 15 is formed on the seed layer 112, and then the heat sink 12 is disposed on the first support 15 to fix the heat sink 12 on the seed layer 112 using the first support 15. Here, a pressing force may be applied during the process of placing the heat sink 12 on the first support 15, so that the filler in the gel of the first support 15 is abutted against the heat sink 12 and the seed layer 112, so that the vertical distance between the heat sink 12 and the seed layer 112 is controlled by the size of the filler in the gel of the first support 15.

For example, the first support 15 may be a thermal interface material. The thermal interface material may adhere the heat sink 12 to the seed layer 112 due to its tackiness and good thermal conductivity.

Referring to fig. 11, the heat conductive member 13 and the conductive member 18 are formed using the MELI method.

The current method for realizing the butt joint between metals can be as follows:

(1) And (5) reflow soldering. Reflow (Reflow) methods connect metals by using Solder (Solder), however, the Reflow process is relatively high, typically up to two hundred degrees celsius, and even some low melting Reflow processes up to 170-180 degrees celsius. And high temperatures may cause adverse effects such as deformation, warpage, etc. of the product.

(2) Copper-copper butt joint. The copper-copper butt joint method is adopted to realize the butt joint between metals at the temperature of hundreds of DEG C, and the pressure on the product in the copper-copper butt joint process is also relatively large. For products that have wafers bonded, if a large pressure is applied to the back of the wafer, the product quality may be adversely affected, such as by deformation of the product, because the wafer is already bonded.

The method of MELI is to deposit a new metal layer on the metal surface by chemical liquid, and the temperature during the deposition process is relatively low, typically several tens of degrees Celsius, for example 30 to 50 degrees Celsius. At the lower temperature, the product is not easy to deform, and the product quality can be improved.

It should be noted that, the space between the inner side of the heat dissipation element 12 and the sidewall of the wafer 11 and the top of the seed layer 112 may form the flow channel 14, the chemical liquid may enter the flow channel 14 through the liquid inlet/outlet 19, and the metal surface contacting with the chemical liquid will form a new metal layer, i.e. the heat conduction element 13 and the electric conduction element 18.

Since the seed layer 112 and the heat conducting portion 121 of the heat dissipation element 12 are both made of metal materials, when the chemical liquid medicine flows through the gap between the seed layer 112 and the heat conducting portion 121 of the heat dissipation element 12, under the action of the chemical liquid medicine, a new metal layer is gradually formed in the direction of the seed layer 112 towards the surface of the heat dissipation element 12, and meanwhile, a new metal layer is gradually formed in the direction of the heat conducting portion 121 of the heat dissipation element 12 towards the surface of the seed layer 112, and after the metal layers formed in the two directions are finally contacted, the heat conducting element 13 is formed.

In addition, since the extension portion 122 of the heat sink 12 is also made of a metal material, the ground line 161 of the substrate 16 is also made of a metal material, and a portion of the substrate 16 where the ground line 161 is exposed from the substrate 16 and is left facing the surface of the heat sink 12 is also made of a metal material, when the chemical solution flows through the gap between the surface of the substrate 16 where the ground line 161 is exposed from the substrate 16 and is facing the surface of the heat sink 12 and the extension portion 122 of the heat sink 12, a new metal layer is gradually formed in the direction of the surface of the ground line 161 of the heat sink 12 by the ground line 161, and a new metal layer is gradually formed in the direction of the surface of the extension portion 122 of the heat sink 12 facing the surface of the ground line 161 of the substrate 16, and the metal layers formed in the two directions are finally contacted to form the conductive member 18. And no new metal layer is formed for the areas of the surface of the substrate 16 facing the heat sink 12 where no metal material is provided. In general, the areas of the surface of the substrate 16 facing the heat sink 12 where the metal material is not provided may be provided with a green paint, and no metal layer is formed on the surface of the green paint.

It will be appreciated that, since the heat sink 12 itself is made of a metal material, when the chemical liquid flows through each surface of the heat sink 12, each surface of the heat sink 12 may be formed with a corresponding thin metal layer, and reference is made to fig. 8. In practice, temporary nonmetallic materials (e.g., adhesive tape) may be provided on the surface of the heat sink 12 where no metallic layer is required to be formed, and the nonmetallic materials may be removed later.

The method for manufacturing the semiconductor packaging structure provided by the utility model can achieve similar technical effects as the semiconductor packaging structure, and is not repeated here.

As used herein, the terms "substantially," "about," and "approximately" are used to indicate and explain minor variations. For example, when used in connection with a numerical value, the term may refer to a range of variation of less than or equal to the corresponding numerical value of + -10%, such as a range of variation of less than or equal to + -5%, less than or equal to + -4%, less than or equal to + -3%, less than or equal to + -2%, less than or equal to + -1%, less than or equal to + -0.5%, less than or equal to + -0.1%, or less than or equal to + -0.05%. As another example, the thickness of a film or layer may be "substantially uniform" to refer to an average thickness of the film or layer that is less than or equal to a standard deviation of ± 10%, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1% or less than or equal to ± 0.05% standard deviation. The term "substantially coplanar" may refer to two surfaces lying within 50 μm along the same plane (such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane). Two components may be considered to be "substantially aligned" if, for example, the two components overlap or overlap within 200 μm, 150 μm, 100 μm, 50 μm, 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. Two surfaces or components may be considered "substantially perpendicular" if the angle between them is, for example, 90 ° ± 10 ° (such as ± 5 °, ±4 °, ±3°, ±2°, ±1°, ±0.5 °, ±0.1°, or ± 0.05 °). When used in connection with an event or circumstance, the terms "substantially," "substantial," "about," and "approximately" can refer to the precise occurrence of the event or circumstance and the very close proximity of the event or circumstance.

Claims (10)

1. A semiconductor package structure, comprising:

a wafer including a non-active surface;

the seed layer is arranged on the non-active surface;

the heat dissipation piece is matched with the wafer to define a flow passage communicated with the outside;

and the heat conduction piece is filled between the heat dissipation piece and the seed layer.

2. The semiconductor package according to claim 1, wherein the semiconductor package further comprises:

at least two first supporting pieces which are arranged at intervals and are connected with the heat dissipation piece and the seed layer, and the first supporting pieces, the heat dissipation piece and the wafer are matched to define the flow channel.

3. The semiconductor package according to claim 2, wherein the first support is embedded in the thermally conductive member.

4. The semiconductor package according to claim 2, wherein the first support comprises a gel and a filler dispersed in the gel.

5. The semiconductor package according to claim 4, wherein the filler is abutted against the heat sink and the seed layer.

6. The semiconductor package according to claim 1, wherein the semiconductor package further comprises:

the substrate is arranged on one side of the wafer away from the heat dissipation piece so as to define the flow channel in a matching way.

7. The semiconductor package according to claim 6, wherein the heat sink includes a heat conductive portion connected to the heat conductive member.

8. The semiconductor package according to claim 7, wherein the heat spreader further comprises an extension extending from the thermally conductive portion toward the substrate and spaced apart from the substrate.

9. The semiconductor package according to claim 8, wherein the semiconductor package further comprises:

at least two second support members connecting the extension portion of the heat sink and the substrate, the second support members, the heat sink and the die cooperatively define the flow channel.

10. The semiconductor package according to claim 6, wherein the substrate has a ground line, and the semiconductor package further comprises:

and a conductive member connecting the heat dissipation member and the ground line of the substrate.