CN219459023U - Low-noise fully-differential capacitance amplifying device - Google Patents
Low-noise fully-differential capacitance amplifying device Download PDFInfo
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- CN219459023U CN219459023U CN202320053535.XU CN202320053535U CN219459023U CN 219459023 U CN219459023 U CN 219459023U CN 202320053535 U CN202320053535 U CN 202320053535U CN 219459023 U CN219459023 U CN 219459023U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The utility model provides a low-noise fully-differential capacitance amplifying device which is applied to an implanted chip and comprises a first-stage amplifying module, a second-stage amplifying module, a third-stage amplifying module and a reset switch module; the non-inverting input end and the inverting input end of the first-stage amplifying module are respectively a non-inverting input end and an inverting input end of the low-noise fully-differential capacitance amplifying device, and a pair of differential input ends are formed; the input end of the reset switch module is respectively connected with the input ends of the first-stage amplifying module, the second-stage amplifying module and the third-stage amplifying module, the output end of the reset switch module is respectively connected with the output ends of the first-stage amplifying module, the second-stage amplifying module and the third-stage amplifying module, the in-phase output end and the opposite-phase output end of the third-stage amplifying module are respectively the opposite-phase output end and the in-phase output end of the low-noise full-differential capacitor amplifying device, a pair of differential output ends is formed, the low-noise full-differential capacitor amplifying device has the advantages of low noise and low power consumption, and meanwhile the influence of offset voltage on output signals is eliminated.
Description
Technical Field
The utility model relates to the technical field of chip signal amplification, in particular to a low-noise fully-differential capacitance amplification device.
Background
The signals are bioelectric signals generated by nerve cell activities, carry corresponding physiological and pathological information of the brain, and have important research significance in medical diagnosis, scientific exploration and engineering application. The signals can be used for carrying out auxiliary diagnosis and mechanism research on brain diseases such as epilepsy, parkinsonism and the like.
In order to meet the needs of signal research, a signal acquisition system is required to complete the acquisition, collection and processing of signals. The implanted chip is usually required to collect human nerve response signals, the nerve response signals are usually small, the amplitude of the nerve response signals is usually only millivolt level or even hundred microvolts level, the nerve response signals are easily interfered by external noise in the process of collection and transmission, the prior art is that the signals are amplified through an analog front end such as a programmable gain amplifier (PmgrammableGainAmplifier, PGA), the amplified signals are converted into digital signals through an ADC (analog to digital converter), the digital signals are numbered, and the digital signals are transmitted to an external machine through a coupling coil. However, the prior art also has the problems that the noise is too large, and the output saturation is caused by the operational amplifier imbalance in the chip, so that the human body implanted chip cannot work normally.
Disclosure of Invention
The utility model provides a low-noise fully-differential capacitance amplifying device, which aims to reduce noise and power consumption of a chip when acquiring nerve signals.
In order to achieve the above purpose, the utility model provides a low-noise fully differential capacitance amplifying device, which is applied to an implanted chip and comprises a first-stage amplifying module, a second-stage amplifying module, a third-stage amplifying module and a reset switch module;
the non-inverting input end and the inverting input end of the first-stage amplifying module form a pair of differential input ends of the low-noise fully-differential capacitance amplifying device;
the non-inverting input end of the first-stage amplifying module is respectively connected with the positive electrode of an electrode for collecting signals in the implanted chip and the first input end of the reset switch module, and the inverting input end of the first-stage amplifying module is respectively connected with the negative electrode of the electrode and the second input end of the reset switch module;
the in-phase output end of the first-stage amplifying module is respectively connected with the first output end of the reset switch module, the in-phase input end of the second-stage amplifying module and the third input end of the reset switch module, and the opposite-phase output end of the first-stage amplifying module is respectively connected with the second output end of the reset switch module, the opposite-phase input end of the second-stage amplifying module and the fourth input end of the reset switch module;
the in-phase output end of the second-stage amplifying module is respectively connected with the third output end of the reset switch module, the in-phase input end of the third-stage amplifying module and the fifth input end of the reset switch module, and the opposite-phase output end of the second-stage amplifying module is respectively connected with the fourth output end of the reset switch module, the opposite-phase input end of the third-stage amplifying module and the sixth input end of the reset switch module;
the in-phase output end of the third-stage amplifying module is respectively connected with the fifth output end of the reset switch module and the first input end of the ADC conversion module, and the opposite-phase output end of the third-stage amplifying module is respectively connected with the sixth output end of the reset switch module and the second input end of the ADC conversion module;
the in-phase output end and the anti-phase output end of the third-stage amplifying module form a pair of differential output ends of the low-noise fully-differential capacitance amplifying device.
Further, the first stage amplifying module includes:
the first fully differential operational amplifier, the first control switch, the second control switch, the first input capacitor, the first feedback capacitor, the second input capacitor and the second feedback capacitor;
the first end of the first control switch is the in-phase input end of the first-stage amplifying module, the second end of the first control switch is connected with the first end of the first input capacitor, the second end of the first input capacitor and the second end of the first input capacitor are respectively connected with the first input end of the first full-differential operational amplifier, the first end of the second input capacitor and the first end of the first reset switch in the reset switch module, the second end of the first reset switch in the reset switch module is respectively connected with the second end of the second input capacitor and the first output end of the first full-differential operational amplifier, and the first output end of the first full-differential operational amplifier is connected with the in-phase input end of the second-stage amplifying circuit;
the first end of the second control switch is an inverting input end of the first-stage amplifying module, the second end of the second control switch is connected with the first end of the first feedback capacitor, the second end of the first feedback capacitor is respectively connected with the second input end of the first fully differential operational amplifier, the first end of the second feedback capacitor and the first end of the second reset switch in the reset switch module, the second end of the second reset switch in the reset switch module is respectively connected with the second end of the second feedback capacitor and the second output end of the fully differential operational amplifier, and the second output end of the first fully differential operational amplifier is connected with the inverting input end of the second-stage amplifying circuit.
Further, the second stage amplifying module includes:
a second fully differential operational amplifier, a third input capacitor, a third feedback capacitor, a fourth input capacitor, a fourth feedback capacitor, a third control switch, a fourth control switch, a fifth input capacitor and a sixth input capacitor;
the first end of the third input capacitor is respectively connected with the first output end of the first full differential operational amplifier and the first end of the fourth input capacitor, the second end of the fourth input capacitor is connected with the first end of the third control switch, the second end of the third control switch is connected with the second end of the third input capacitor, the second end of the third input capacitor is respectively connected with the first input end of the second full differential operational amplifier, the first end of the third feedback capacitor and the first end of the third reset switch in the reset switch module, the second end of the third reset switch in the reset switch module is respectively connected with the second end of the third feedback capacitor and the first output end of the second full differential operational amplifier, and the first output end of the second full differential operational amplifier is connected with the in-phase input end of the third stage amplifying module;
the first end of the fifth input capacitor is respectively connected with the second output end of the first full differential operational amplifier and the first end of the sixth input capacitor, the second end of the sixth input capacitor is connected with the first end of the fourth control switch, the second end of the fourth control switch is connected with the second end of the fifth input capacitor, the second end of the fifth input capacitor is respectively connected with the second input end of the second full differential operational amplifier, the first end of the fourth feedback capacitor and the first end of the fourth reset switch in the reset switch module, the second end of the fourth reset switch in the reset switch module is respectively connected with the second end of the fourth feedback capacitor and the second output end of the second full differential operational amplifier, and the second output end of the second full differential operational amplifier is connected with the inverting input end of the third stage amplifying module.
Further, the third stage amplification module includes:
a third fully differential operational amplifier, a seventh input capacitance, a fifth feedback capacitance, an eighth input capacitance, a sixth feedback capacitance, a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch;
the first end of the seventh input capacitor is respectively connected with the first output end of the second full differential operational amplifier and the first end of the fifth control switch, the second end of the seventh input capacitor is respectively connected with the first input end of the third full differential operational amplifier, the first end of the fifth feedback capacitor and the first end of the fifth reset switch in the reset switch module, the second end of the fifth reset switch in the reset switch module is respectively connected with the second end of the fifth feedback capacitor and the first output end of the third full differential operational amplifier, the first output end of the third full differential operational amplifier is connected with the first end of the seventh control switch, and the second end of the seventh control switch is connected with the second end of the sixth control switch to serve as an inverting output end of the third-stage amplifying module;
the first end of the eighth input capacitor is respectively connected with the second output end of the second full differential operational amplifier and the first end of the sixth control switch, the second end of the eighth input capacitor is respectively connected with the second input end of the third full differential operational amplifier, the first end of the sixth feedback capacitor and the first end of the sixth reset switch in the reset switch module, the second end of the sixth reset switch in the reset switch module is respectively connected with the second end of the sixth feedback capacitor and the second output end of the third full differential operational amplifier, the second output end of the third full differential operational amplifier is connected with the first end of the eighth control switch, and the second end of the eighth control switch is connected with the second end of the eighth control switch to serve as the in-phase output end of the third-stage amplifying module.
Further, the first stage amplifying module further includes: a ninth control switch and a tenth control switch;
the first end of the ninth control switch is connected with the first end of the tenth control switch and grounded, the second end of the ninth control switch is connected with the second end of the first control switch, and the second end of the tenth control switch is connected with the second end of the second control switch.
Further, the gain of the first stage amplification module is determined by the ratio of the first input capacitance to the first feedback capacitance or by the ratio of the second input capacitance to the second feedback capacitance;
the gain of the second-stage amplifying module is determined by the ratio of the sum of the third input capacitor and the fourth input capacitor to the third feedback capacitor, or by the ratio of the sum of the fifth input capacitor and the sixth input capacitor to the fourth feedback capacitor;
the gain of the third stage amplification module is determined by the ratio of the seventh input capacitance to the fifth feedback capacitance or by the ratio of the eighth input capacitance to the sixth feedback capacitance.
Further, the first fully differential operational amplifier, the second fully differential operational amplifier and the third fully differential operational amplifier each have a pair of differential inputs and a pair of differential outputs, and each of the first fully differential operational amplifier, the second fully differential operational amplifier and the third fully differential operational amplifier is composed of an operational amplifier and a common mode feedback circuit.
Preferably, the low noise fully differential capacitive amplifying means has selectable gain values of 40db, 50db, 60db and 70db.
The scheme of the utility model has the following beneficial effects:
compared with the prior art, the utility model has the advantages of low noise and low power consumption; since the noise mainly originates from the first-stage amplifying module, the input noise of the utility model can be greatly reduced by reducing the input noise of the first-stage amplifying module, especially 1/f noise; because the input signal frequency is lower, the typical switching frequency of the utility model is 500KHz, the power consumption can be very low by optimizing the three-stage amplifying module, and meanwhile, the reset switch module is arranged to release the low-noise fully differential capacitance amplifying device step by step, thereby eliminating the influence of offset voltage of the first-stage operational amplifier and the second-stage operational amplifier on the output signal, increasing the detection range of the input signal and preventing the amplifier from being saturated.
Other advantageous effects of the present utility model will be described in detail in the detailed description section which follows.
Drawings
FIG. 1 is a system block diagram of an embodiment of the present utility model;
FIG. 2 is a schematic diagram of an embodiment of the present utility model;
FIG. 3 is a timing diagram of an embodiment of the present utility model;
FIG. 4 is a graph showing the variation of the differential amplified signal output by an embodiment of the present utility model;
FIG. 5 is a noise test result obtained by testing a circuit platform according to an embodiment of the present utility model.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, the technical features of the different embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.
As shown in fig. 1, an embodiment of the present utility model provides a low noise fully differential capacitive amplifying device, which is applied to an implanted chip and includes a first stage amplifying module OPA1, a second stage amplifying module OPA2, a third stage amplifying module OPA3 and a reset switch module;
the non-inverting input end and the inverting input end of the first-stage amplification module OPA1 are respectively a non-inverting input end and an inverting input end of the low-noise fully-differential capacitive amplification device, and the non-inverting input end and the inverting input end of the first-stage amplification module OPA1 form a pair of differential input ends PGA_INP and PGA_INN of the low-noise fully-differential capacitive amplification device;
the non-inverting input end of the first-stage amplification module OPA1 is respectively connected with the positive electrode of an electrode for collecting signals in an implanted chip and the first input end of the reset switch module, and the inverting input end of the first-stage amplification module OPA1 is respectively connected with the negative electrode of the electrode and the second input end of the reset switch module;
the in-phase output end of the first-stage amplification module OPA1 is respectively connected with the first output end of the reset switch module, the in-phase input end of the second-stage amplification module OPA2 and the third input end of the reset switch module, and the anti-phase output end of the first-stage amplification module OPA1 is respectively connected with the second output end of the reset switch module, the anti-phase input end of the second-stage amplification module OPA2 and the fourth input end of the reset switch module;
the in-phase output end of the second-stage amplification module OPA2 is respectively connected with the third output end of the reset switch module, the in-phase input end of the third-stage amplification module OPA3 and the fifth input end of the reset switch module, and the anti-phase output end of the second-stage amplification module OPA2 is respectively connected with the fourth output end of the reset switch module, the anti-phase input end of the third-stage amplification module OPA3 and the sixth input end of the reset switch module;
the in-phase output end of the third-stage amplification module OPA3 is respectively connected with the fifth output end of the reset switch module and the first input end of the ADC conversion module, and the opposite-phase output end of the third-stage amplification module OPA3 is respectively connected with the sixth output end of the reset switch module and the second input end of the ADC conversion module;
the in-phase output end and the opposite-phase output end of the third-stage amplification module OPA3 are respectively an opposite-phase output end and an in-phase output end of the low-noise fully-differential capacitive amplification device, and the in-phase output end and the opposite-phase output end of the third-stage amplification module OPA3 form a pair of differential output ends OUTN and OUTP of the low-noise fully-differential capacitive amplification device.
In the embodiment of the utility model, the chip can be a human body implantation chip or an animal body implantation chip, the implantation chip comprises a signal acquisition module, namely an electrode, the low-noise fully-differential capacitance amplifying device, the ADC conversion module and the output module, the chip is implanted into a human body or an animal body, nerve signals of the human body or the animal are acquired through the acquisition module, the nerve signals are transmitted to the low-noise fully-differential capacitance amplifying device provided by the embodiment of the utility model for signal amplification, the amplified signals are transmitted to the ADC conversion module for conversion, and finally the converted signals are output to external equipment through the output module.
The embodiment of the utility model has a Reset phase and an amplification phase, and before the signal starts to be amplified, a first-stage amplification module OPA1, a second-stage amplification module OPA2 and a third-stage amplification module OPA3 are all in a Reset state, at the moment, a Reset switch module is in a high level, and a low-noise fully-differential capacitance amplification device outputs a differential signal of 0V; when the amplification is started, the non-inverting input end and the inverting input end of the first-stage amplification module OPA1 are respectively connected with the positive electrode and the negative electrode of the electrode for collecting signals, after a period of stability, the reset switch module is converted into a low level, so that the first-stage amplification module OPA1, the second-stage amplification module OPA2 and the third-stage amplification module OPA3 are reset once, and the low-noise fully-differential capacitance amplification device starts to amplify signals detected by the electrodes.
Specifically, as shown in fig. 2, the first stage amplification module OPA1 includes:
a first fully differential operational amplifier OP1, a first control switch K1, a second control switch K2, a first input capacitance C1, a first feedback capacitance FC1, a second input capacitance C2, and a second feedback capacitance FC2;
the first end of the first control switch K1 is the in-phase input end of the first-stage amplifying module OPA1, the second end of the first control switch K1 is connected with the first end of the first input capacitor C1, the second end and the second end of the first input capacitor C1 are respectively connected with the first input end of the first fully differential operational amplifier OP1, the first end of the second input capacitor C2 and the first end of the first reset switch SR1 in the reset switch module, the second end of the first reset switch SR1 in the reset switch module is respectively connected with the second end of the second input capacitor C2 and the first output end of the first fully differential operational amplifier OP1, and the first output end of the first fully differential operational amplifier OP1 is connected with the in-phase input end of the second-stage amplifying circuit;
the first end of the second control switch K2 is an inverting input end of the first-stage amplifying module OPA1, the second end of the second control switch K2 is connected with the first end of the first feedback capacitor FC1, the second end of the first feedback capacitor FC1 is respectively connected with the second input end of the first fully differential operational amplifier OP1, the first end of the second feedback capacitor FC2 and the first end of the second reset switch SR2 in the reset switch module, the second end of the second reset switch SR2 in the reset switch module is respectively connected with the second end of the second feedback capacitor FC2 and the second output end of the fully differential operational amplifier, and the second output end of the first fully differential operational amplifier OP1 is connected with the inverting input end of the second-stage amplifying circuit.
Specifically, as shown in fig. 2, the second-stage amplification module OPA2 includes:
the second fully differential operational amplifier OP2, the third input capacitor C3, the third feedback capacitor FC3, the fourth input capacitor C4, the fourth feedback capacitor FC4, the third control switch K3, the fourth control switch, the fifth input capacitor C5 and the sixth input capacitor C6;
the first end of the third input capacitor C3 is respectively connected with the first output end of the first fully differential operational amplifier OP1 and the first end of the fourth input capacitor C4, the second end of the fourth input capacitor C4 is connected with the first end of the third control switch K3, the second end of the third control switch K3 is connected with the second end of the third input capacitor C3, the second end of the third input capacitor C3 is respectively connected with the first input end of the second fully differential operational amplifier OP2, the first end of the third feedback capacitor FC3 and the first end of the third reset switch SR3 in the reset switch module, the second end of the third reset switch SR3 in the reset switch module is respectively connected with the second end of the third feedback capacitor FC3 and the first output end of the second fully differential operational amplifier OP2, and the first output end of the second fully differential operational amplifier OP2 is connected with the in-phase input end of the third stage amplifying module OPA 3;
the first end of the fifth input capacitor C5 is connected to the second output end of the first fully differential operational amplifier OP1 and the first end of the sixth input capacitor C6, the second end of the sixth input capacitor C6 is connected to the first end of the fourth control switch, the second end of the fourth control switch is connected to the second end of the fifth input capacitor C5, the second end of the fifth input capacitor C5 is connected to the second input end of the second fully differential operational amplifier OP2, the first end of the fourth feedback capacitor FC4 and the first end of the fourth reset switch SR4 in the reset switch module, the second end of the fourth reset switch SR4 in the reset switch module is connected to the second end of the fourth feedback capacitor FC4 and the second output end of the second fully differential operational amplifier OP2, and the second output end of the second fully differential operational amplifier OP2 is connected to the inverting input end of the third stage amplifying module OPA 3.
Specifically, as shown in fig. 2, the third stage amplification module OPA3 includes:
a third fully differential operational amplifier OP3, a seventh input capacitor C7, a fifth feedback capacitor FC5, an eighth input capacitor C8, a sixth feedback capacitor FC6, a fifth control switch K5, a sixth control switch K6, a seventh control switch K7 and an eighth control switch K8;
the first end of the seventh input capacitor C7 is respectively connected with the first output end of the second fully differential operational amplifier OP2 and the first end of the fifth control switch K5, the second end of the seventh input capacitor C7 is respectively connected with the first input end of the third fully differential operational amplifier OP3, the first end of the fifth feedback capacitor FC5 and the first end of the fifth reset switch SR5 in the reset switch module, the second end of the fifth reset switch SR5 in the reset switch module is respectively connected with the second end of the fifth feedback capacitor FC5 and the first output end of the third fully differential operational amplifier OP3, the first output end of the third fully differential operational amplifier OP3 is connected with the first end of the seventh control switch K7, and the second end of the seventh control switch K7 is connected with the second end of the sixth control switch K6 to serve as an inverting output end of the third-stage amplifying module OPA 3;
the first end of the eighth input capacitor C8 is connected to the second output end of the second fully differential operational amplifier OP2 and the first end of the sixth control switch K6, the second end of the eighth input capacitor C8 is connected to the second input end of the third fully differential operational amplifier OP3, the first end of the sixth feedback capacitor FC6 and the first end of the sixth reset switch SR6 in the reset switch module, the second end of the sixth reset switch SR6 in the reset switch module is connected to the second end of the sixth feedback capacitor FC6 and the second output end of the third fully differential operational amplifier OP3, the second output end of the third fully differential operational amplifier OP3 is connected to the first end of the eighth control switch K8, and the second end of the eighth control switch K8 is connected to the second end of the eighth control switch K8 as the in-phase output end of the third stage amplifying module OPA 3.
Specifically, the first stage amplification module OPA1 further includes: a ninth control switch K9 and a tenth control switch K10;
the first end of the ninth control switch K9 is connected to the first end of the tenth control switch K10 and grounded GND, the second end of the ninth control switch K9 is connected to the second end of the first control switch K1, and the second end of the tenth control switch K10 is connected to the second end of the second control switch K2.
In the embodiment of the present utility model, when the ninth control switch K9 and the tenth control switch K10 are turned off, the first control switch K1 and the second control switch K2 are respectively connected to the positive electrode and the negative electrode of the electrode for collecting signals.
Specifically, the gain of the first stage amplifying module OPA1 is determined by the ratio of the first input capacitance C1 to the first feedback capacitance FC1 or by the ratio of the second input capacitance C2 to the second feedback capacitance FC2;
that is, when c1/fc1=30 or c2/fc2=30, the gain of the first-stage amplification module OPA1 is 30 times;
the gain of the second-stage amplifying module OPA2 is determined by the ratio of the sum of the third input capacitor C3 and the fourth input capacitor C4 to the third feedback capacitor FC3 or by the ratio of the sum of the fifth input capacitor C5 and the sixth input capacitor C6 to the fourth feedback capacitor FC 4;
that is, when the signal GS5070 input to the third control switch K3 is at a low level, the third control switch K3 is turned off, the fourth input capacitor C4 is not turned on, or when the signal GS5070 input to the fourth control switch K4 is at a low level, the fourth control switch K4 is turned off, the sixth input capacitor C6 is not turned on, that is, c3/fc3=10/3 or c5/fc4=10/3, and the gain of the second stage amplifying module OPA2 is 10/3 times;
when the signal GS5070 input to the third control switch K3 is at a high level, the third control switch K3 is closed, the fourth input capacitor C4 is connected in parallel with the third input capacitor C3, or when the signal GS5070 input to the fourth control switch K4 is at a high level, the fourth control switch K4 is closed, the sixth input capacitor C6 is connected in parallel with the fifth input capacitor, that is, (c3+c4)/fc3=10 or (c5+c6)/fc4=10/3, and the gain of the second-stage amplifying module OPA2 is 10 times;
the gain of the third stage amplification module OPA3 is determined by the ratio of the seventh input capacitance C7 to the fifth feedback capacitance FC5 or by the ratio of the eighth input capacitance C8 to the sixth feedback capacitance FC 6;
i.e. when C7/fc5=10 or C8/fc6=10, the gain of the third stage amplification module OPA3 is 10 times.
In the embodiment of the utility model, when the gain of the system configuration is 100, only the first-stage amplifying module OPA1 and the second-stage amplifying module OPA2 need to be turned on, the gain set by the first-stage amplifying module OPA1 is 30 times, the signal GS5070 input to the fourth control switch K4 and the sixth control switch K6 is low level, the second-stage amplifying module OPA2 is set to 10/3 times the gain, the third-stage amplifying module OPA3 is turned off, the signal GS4050 input to the fifth control switch K5 and the sixth control switch K6 cause the fifth control switch K5 and the sixth control switch K6 to be turned on, and the signal GS6070 input to the seventh control switch K7 and the eighth control switch K8 cause the seventh control switch K7 and the eighth control switch K8 to be turned off;
when the gain of the system configuration is 300, only the first-stage amplifying module OPA1 and the second-stage amplifying module OPA2 are required to be turned on, the gain set by the first-stage amplifying module OPA1 is 30 times, the signals GS5070 input to the fourth control switch K4 and the sixth control switch K6 are both high level, so that the third control switch K3 and the fourth control switch K4 are both closed, the fourth input capacitor C4 is connected with the third input capacitor C3 in parallel, or the sixth input capacitor C6 is connected with the fifth input capacitor in parallel, the second-stage amplifying module OPA2 is set with 10 times of gain, the third-stage amplifying module OPA3 is turned off, the signals GS4050 input to the fifth control switch K5 and the sixth control switch K6 are both closed, and the signals GS6070 input to the seventh control switch K7 and the eighth control switch K8 are both opened;
when the gain of the system configuration is 1000, the three-stage amplifying modules are required to be all on, the gain set by the first-stage amplifying module OPA1 is 30 times, the signal GS5070 input to the fourth control switch K4 and the sixth control switch K6 is low level, the gain set by the second-stage amplifying module OPA2 is 10/3 times, the signal GS4050 input to the fifth control switch K5 and the sixth control switch K6 is enabled to enable the fifth control switch K5 and the sixth control switch K6 to be both off, the signal GS6070 input to the seventh control switch K7 and the eighth control switch K8 is enabled to enable the seventh control switch K7 and the eighth control switch K8 to be both on, and the gain of the third-stage amplifying module OPA3 is 10 times;
when the gain of the system configuration is 3000, the three-stage amplifying modules are all required to be turned on, the gain set by the first-stage amplifying module OPA1 is 30 times, the signals GS5070 input to the fourth control switch K4 and the sixth control switch K6 are all high levels, so that the third control switch K3 and the fourth control switch K4 are all closed, the fourth input capacitor C4 is connected in parallel with the third input capacitor C3, or the sixth input capacitor C6 is connected in parallel with the fifth input capacitor, the second-stage amplifying module OPA2 is set to 10 times of the gain, the signals GS4050 input to the fifth control switch K5 and the sixth control switch K6 are all opened, the signals GS6070 input to the seventh control switch K7 and the eighth control switch K8 are all closed, and the gain of the third-stage amplifying module OPA3 is 10 times.
Specifically, the first fully differential operational amplifier OP1, the second fully differential operational amplifier OP2, and the third fully differential operational amplifier OP3 each have a pair of differential inputs and a pair of differential outputs, and the first fully differential operational amplifier OP1, the second fully differential operational amplifier OP2, and the third fully differential operational amplifier OP3 are each composed of an operational amplifier and a common mode feedback circuit.
Before the low-noise fully-differential capacitive amplification device starts signal amplification, the first-stage amplification module OPA1, the second-stage amplification module OPA2 and the third-stage amplification module OPA3 are all in a reset state, at this time, signals of the first reset switch RS1, the second reset switch RS2, the third reset switch RS3, the fourth reset switch RS4, the fifth reset switch RS5 and the sixth reset switch RS6 are all placed at a high level, and the low-noise fully-differential capacitive amplification PGA outputs differential signals of 0V; after amplification is started, the first end of the first control switch K1 and the first end of the second control switch K2 are respectively connected with the positive electrode and the negative electrode by switching off the ninth control switch K9 and the tenth control switch K10, when the system stably operates for a period of time, the first reset switch RS1, the second reset switch RS2, the third reset switch RS3, the fourth reset switch RS4, the fifth reset switch RS5 and the sixth reset switch RS6 sequentially pull the low level, the first fully differential operational amplifier OP1, the second fully differential operational amplifier OP2 and the third fully differential operational amplifier OP3 sequentially release the reset state, the low-noise fully differential capacitor amplification device starts to differentially amplify signals detected by the electrodes and inputs the signals to the ADC conversion module, the time sequence diagram is shown in fig. 3, when the fifth reset switch RS5 and the sixth reset switch RS6 pull the low level, the change curves of the signals amplified by the low-noise fully differential capacitor amplification device are shown in fig. 4, the increment of the signals amplified by the embodiment of the utility model is shown in fig. 4, the reset signals of each stage are acquired by the polarity signals of each stage and the signals are acquired and the same, and the data input and the data are processed in a later period is convenient.
Specifically, the embodiment of the utility model is carried on a test circuit platform for noise and offset voltage testing, the test result is shown in fig. 5, the average noise is 7.6uV and less than 8uV, the offset voltage is 8.9uV and less than 9uV, and the noise mainly comes from the first-stage amplifying module OPA1.
Specifically, the low noise fully differential capacitive amplifying device may select gain values of 40db, 50db, 60db and 70db; because the amplification of 40db, 50db, 60db and 70db is 100, 300, 1000 and 3000 times, respectively, the human body signal size is millivolt level to hundred microvolts level, and the input range of the subsequent ADC can be satisfied by 100, 300, 1000 and 3000 times amplification.
Compared with the prior art, the embodiment of the utility model has the advantages of low noise and low power consumption, wherein the noise and the offset voltage are respectively 10 percent and 1 percent of those of the prior art; since the noise mainly originates from the first-stage amplifying module, the input noise of the utility model can be greatly reduced by reducing the input noise of the first-stage amplifying module, especially 1/f noise; because the input signal frequency is lower, the typical switching frequency of the embodiment of the utility model is 500KHz, the power consumption can be very low by optimizing the three-stage amplifying module, and meanwhile, the reset switch module is arranged to release the low-noise fully differential capacitance amplifying device step by step, thereby eliminating the influence of offset voltage of the first-stage operational amplifier and the second-stage operational amplifier on the output signal, increasing the detection range of the input signal and preventing the amplifier from being saturated.
While the foregoing is directed to the preferred embodiments of the present utility model, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present utility model, and such modifications and adaptations are intended to be comprehended within the scope of the present utility model.
Claims (8)
1. A low-noise fully differential capacitance amplifying device is characterized in that the device is applied to an implanted chip,
the device comprises a first-stage amplifying module, a second-stage amplifying module, a third-stage amplifying module and a reset switch module;
the non-inverting input end and the inverting input end of the first-stage amplifying module form a pair of differential input ends of the low-noise fully-differential capacitance amplifying device;
the non-inverting input end of the first-stage amplifying module is respectively connected with the positive electrode of an electrode for collecting signals in the implanted chip and the first input end of the reset switch module, and the inverting input end of the first-stage amplifying module is respectively connected with the negative electrode of the electrode and the second input end of the reset switch module;
the in-phase output end of the first-stage amplifying module is respectively connected with the first output end of the reset switch module, the in-phase input end of the second-stage amplifying module and the third input end of the reset switch module, and the opposite-phase output end of the first-stage amplifying module is respectively connected with the second output end of the reset switch module, the opposite-phase input end of the second-stage amplifying module and the fourth input end of the reset switch module;
the in-phase output end of the second-stage amplifying module is respectively connected with the third output end of the reset switch module, the in-phase input end of the third-stage amplifying module and the fifth input end of the reset switch module, and the opposite-phase output end of the second-stage amplifying module is respectively connected with the fourth output end of the reset switch module, the opposite-phase input end of the third-stage amplifying module and the sixth input end of the reset switch module;
the in-phase output end of the third-stage amplifying module is respectively connected with the fifth output end of the reset switch module and the first input end of the ADC conversion module, and the opposite-phase output end of the third-stage amplifying module is respectively connected with the sixth output end of the reset switch module and the second input end of the ADC conversion module;
and the in-phase output end and the anti-phase output end of the third-stage amplification module form a pair of differential output ends of the low-noise fully-differential capacitance amplification device.
2. The low noise fully differential capacitive amplifying device of claim 1, wherein the first stage amplifying module comprises:
the first fully differential operational amplifier, the first control switch, the second control switch, the first input capacitor, the first feedback capacitor, the second input capacitor and the second feedback capacitor;
the first end of the first control switch is the in-phase input end of the first-stage amplifying module, the second end of the first control switch is connected with the first end of the first input capacitor, the second end of the first input capacitor is connected with the first input end of the first fully-differential operational amplifier, the first end of the second input capacitor and the first end of a first reset switch in the reset switch module respectively, the second end of the first reset switch in the reset switch module is connected with the second end of the second input capacitor and the first output end of the first fully-differential operational amplifier respectively, and the first output end of the first fully-differential operational amplifier is connected with the in-phase input end of the second-stage amplifying module;
the first end of the second control switch is an inverting input end of the first-stage amplifying module, the second end of the second control switch is connected with the first end of the first feedback capacitor, the second end of the first feedback capacitor is respectively connected with the second input end of the first fully differential operational amplifier, the first end of the second feedback capacitor and the first end of the second reset switch in the reset switch module, the second end of the second reset switch in the reset switch module is respectively connected with the second end of the second feedback capacitor and the second output end of the fully differential operational amplifier, and the second output end of the first fully differential operational amplifier is connected with the inverting input end of the second-stage amplifying module.
3. The low noise fully differential capacitive amplifying device of claim 2, wherein the second stage amplifying module comprises:
a second fully differential operational amplifier, a third input capacitor, a third feedback capacitor, a fourth input capacitor, a fourth feedback capacitor, a third control switch, a fourth control switch, a fifth input capacitor and a sixth input capacitor;
the first end of the third input capacitor is respectively connected with the first output end of the first fully differential operational amplifier and the first end of the fourth input capacitor, the second end of the fourth input capacitor is connected with the first end of the third control switch, the second end of the third control switch is connected with the second end of the third input capacitor, the second end of the third input capacitor is respectively connected with the first input end of the second fully differential operational amplifier, the first end of the third feedback capacitor and the first end of a third reset switch in the reset switch module, the second end of the third reset switch in the reset switch module is respectively connected with the second end of the third feedback capacitor and the first output end of the second fully differential operational amplifier, and the first output end of the second fully differential operational amplifier is connected with the in-phase input end of the third stage amplifying module;
the first end of the fifth input capacitor is respectively connected with the second output end of the first full differential operational amplifier and the first end of the sixth input capacitor, the second end of the sixth input capacitor is connected with the first end of the fourth control switch, the second end of the fourth control switch is connected with the second end of the fifth input capacitor, the second end of the fifth input capacitor is respectively connected with the second input end of the second full differential operational amplifier, the first end of the fourth feedback capacitor and the first end of the fourth reset switch in the reset switch module, the second end of the fourth reset switch in the reset switch module is respectively connected with the second end of the fourth feedback capacitor and the second output end of the second full differential operational amplifier, and the second output end of the second full differential operational amplifier is connected with the inverting input end of the third stage amplifying module.
4. The low noise fully differential capacitive amplifying device according to claim 3, wherein the third stage amplifying module comprises:
a third fully differential operational amplifier, a seventh input capacitance, a fifth feedback capacitance, an eighth input capacitance, a sixth feedback capacitance, a fifth control switch, a sixth control switch, a seventh control switch, and an eighth control switch;
the first end of the seventh input capacitor is respectively connected with the first output end of the second fully differential operational amplifier and the first end of the fifth control switch, the second end of the seventh input capacitor is respectively connected with the first input end of the third fully differential operational amplifier, the first end of the fifth feedback capacitor and the first end of a fifth reset switch in the reset switch module, the second end of the fifth reset switch in the reset switch module is respectively connected with the second end of the fifth feedback capacitor and the first output end of the third fully differential operational amplifier, the first output end of the third fully differential operational amplifier is connected with the first end of the seventh control switch, and the second end of the seventh control switch is connected with the second end of the sixth control switch to serve as an inverting output end of the third stage amplifying module;
the first end of the eighth input capacitor is respectively connected with the second output end of the second full differential operational amplifier and the first end of the sixth control switch, the second end of the eighth input capacitor is respectively connected with the second input end of the third full differential operational amplifier, the first end of the sixth feedback capacitor and the first end of a sixth reset switch in the reset switch module, the second end of the sixth reset switch in the reset switch module is respectively connected with the second end of the sixth feedback capacitor and the second output end of the third full differential operational amplifier, the second output end of the third full differential operational amplifier is connected with the first end of the eighth control switch, and the second end of the eighth control switch is connected with the second end of the eighth control switch to serve as an in-phase output end of the third stage amplifying module.
5. The low noise fully differential capacitive amplifying device of claim 2, wherein the first stage amplifying module further comprises: a ninth control switch and a tenth control switch;
the first end of the ninth control switch is connected with the first end of the tenth control switch and grounded, the second end of the ninth control switch is connected with the second end of the first control switch, and the second end of the tenth control switch is connected with the second end of the second control switch.
6. The low-noise fully differential capacitive amplifying device according to claim 4, wherein,
the gain of the first stage amplification module is determined by the ratio of the first input capacitance to the first feedback capacitance or by the ratio of the second input capacitance to the second feedback capacitance;
the gain of the second-stage amplifying module is determined by the ratio of the sum of the third input capacitor and the fourth input capacitor to the third feedback capacitor, or by the ratio of the sum of the fifth input capacitor and the sixth input capacitor to the fourth feedback capacitor;
the gain of the third stage amplification module is determined by the ratio of the seventh input capacitance to the fifth feedback capacitance or by the ratio of the eighth input capacitance to the sixth feedback capacitance.
7. The low noise fully differential capacitive amplifying device according to claim 4, wherein the first fully differential operational amplifier, the second fully differential operational amplifier and the third fully differential operational amplifier each have a pair of differential inputs and a pair of differential outputs, and wherein the first fully differential operational amplifier, the second fully differential operational amplifier and the third fully differential operational amplifier each are composed of an operational amplifier and a common mode feedback circuit.
8. The low noise fully differential capacitive amplifying device of claim 7, wherein the low noise fully differential capacitive amplifying device has selectable gain values of 40db, 50db, 60db and 70db.
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