CN219420603U - Two-stage combined circuit for realizing interleaved parallel connection of LLC circuits - Google Patents
Two-stage combined circuit for realizing interleaved parallel connection of LLC circuits Download PDFInfo
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- CN219420603U CN219420603U CN202320650302.8U CN202320650302U CN219420603U CN 219420603 U CN219420603 U CN 219420603U CN 202320650302 U CN202320650302 U CN 202320650302U CN 219420603 U CN219420603 U CN 219420603U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The utility model discloses a two-stage combined circuit for realizing interleaved parallel connection of LLC circuits, which comprises a first LLC circuit and a second LLC circuit which are arranged in parallel, a first BUCK circuit which is connected with the input end of the first LLC circuit and forms a main loop, a second BUCK circuit which is connected with the input end of the second LLC circuit and forms a secondary loop, and a peripheral control circuit for controlling the main loop and the secondary loop. The direct current voltages output by the two BUCK circuits are respectively connected into the two LLC main circuits, the two LLC circuits work in a fixed-frequency resonance state, the driving square waves are staggered by 180 degrees in phase, and the ripple current of the output end after parallel rectification contains larger direct current components, so that the burden of an output filter capacitor is greatly reduced.
Description
Technical Field
The utility model relates to the field of power chargers or DC/DC power supplies, in particular to a two-stage combined circuit for realizing interleaved parallel connection of LLC circuits.
Background
Currently, the main circuit of a high-power converter, especially the main circuit used in the high-voltage output occasion, mostly adopts LLC topology. Since the output current peak-to-peak value of the LLC is too large, a great challenge is faced in low-voltage high-current applications.
In order to solve the problems, the prior art solves the problems that the root mean square value of LLC output current ripple can be reduced from 48% in single-path to 12% in staggered parallel connection through LLC staggered parallel connection, so that the staggered parallel LLC output current ripple is similar to the traditional circuit current ripple with output filter inductance, and the design difficulty of LLC can be greatly reduced.
For example, application number 201910052465.4 discloses a parallel interleaved LLC circuit comprising: the first equalization capacitor is connected with the anode of the power supply in series, and the other end of the second equalization capacitor is connected with the cathode of the power supply; the system comprises a first LLC resonant converter and a second LLC resonant converter, wherein the output end of the first LLC resonant converter is connected with the output end of the second LLC resonant converter in parallel, the input end of the first LLC resonant converter is connected with a first equalizing capacitor in parallel, and the input end of the second LLC resonant converter is connected with a second equalizing capacitor in parallel; and the control circuit is respectively connected with the two LLC resonant converters and used for controlling the two LLC resonant converters to perform staggered parallel connection operation.
The interleaved parallel LLC circuit controls the two LLC resonant converters through the control circuit, so that the interleaved parallel connection of the two LLC resonant converters can be realized, but the current balance problem of the two circuits is not solved.
Accordingly, there is a need for an improvement in such a structure to overcome the above-described drawbacks.
Disclosure of Invention
It is an object of the utility model to provide a two-stage combining circuit for implementing interleaved parallel of LLC circuits,
the technical aim of the utility model is realized by the following technical scheme:
a two-stage combination circuit for realizing LLC circuit staggered parallel connection comprises
A first LLC circuit and a second LLC circuit arranged in parallel,
a first BUCK circuit connected with the input end of the first LLC circuit and forming a main loop,
a second BUCK circuit connected with the input end of the second LLC circuit and forming a secondary loop,
and peripheral control circuitry for controlling the primary loop and the secondary loop.
Further, the peripheral control circuit comprises a PWM control chip and an MCU connected with the PWM control chip; the PWM control chip is connected with the first BUCK circuit and controls the main loop by outputting PWM control pulse; the MCU is respectively connected with the PWM control chip, the first BUCK circuit and the second BUCK circuit, replicates the PWM control pulse, and adjusts the phase and the pulse width of the PWM control pulse according to the acquired current values of the first BUCK circuit and the second BUCK circuit to obtain a phase staggered secondary loop control signal.
Further, the input ends of the first BUCK circuit and the second BUCK circuit are connected with a direct current power supply, and the output ends of the first BUCK circuit and the second BUCK circuit are respectively connected with the first LLC circuit or the second LLC circuit.
Further, the first BUCK circuit comprises a current transformer CT1, one end of the current transformer CT1 is connected with a direct current power supply, the other end of the current transformer CT1 is connected with a main switching tube Q1, the main switching tube Q1 is connected with a DR1 port of the MCU, the other end of the main switching tube Q1 is connected with an inductor L1 and a diode D1, and current output by the first BUCK circuit is filtered by a capacitor C1 and then is input into the first LLC circuit.
Further, the second BUCK circuit comprises a current transformer CT2, one end of the current transformer CT2 is connected with a direct current power supply, the other end of the current transformer CT2 is connected with a main switching tube Q2, the main switching tube Q2 is connected with a DR2 port of the MCU, the other end of the main switching tube Q2 is connected with an inductor L2 and a diode, and current output by the BUCK circuit is filtered by a capacitor C2 and then is input into the second LLC circuit.
Further, the first LLC circuit includes a main switching tube Q3 and a main switching tube Q4 connected in series, the main switching tube Q3 and the main switching tube Q4 and the main switching tube Q5 and the main switching tube Q6 connected in series form a full-bridge front and rear arm, a resonance capacitor LS1 is disposed between the main switching tube Q3 and the main switching tube Q4, the resonance capacitor LS1 is connected with one end of a transformer T1, and a diode D3 and a diode D4 are disposed at the other end of the transformer T1.
Further, the second LLC circuit includes a main switching tube Q7 and a main switching tube Q8 connected in series, the main switching tube Q7 and the main switching tube Q8, and the main switching tube Q9 and the main switching tube Q10 connected in series form a full-bridge front and rear arm, a resonance capacitor LS2 is disposed between the main switching tube Q7 and the main switching tube Q8, the resonance capacitor LS2 is connected with one end of a transformer T2, and a diode D5 and a diode D6 are disposed at the other end of the transformer T2.
The drive signals of the first LLC circuit and the second LLC circuit are fixed frequency staggered drive signals, and the drive signals come from the output of the MCU.
In summary, the utility model has the following beneficial effects:
1. the circuit combines the traditional PWM and LLC two stages, can exert respective advantages, has overall efficiency not lower than that of a single-stage circuit, and can adapt to wide-range load change. The LLC circuit works in a resonant state at fixed frequency, and the output ripple current is greatly reduced after the LLC circuit is connected in parallel in a staggered mode.
2. The circuit adjusting configuration still belongs to PWM, and compared with a monopole LLC circuit, the circuit has the advantages of simple loop design, large output range and wide load adjusting range.
3. The circuit can adopt MCU digital processing except PWM analog control, does not need closed-loop algorithm, and can be realized by simple programming.
Drawings
Fig. 1 is a schematic diagram of a two-stage combining circuit for implementing interleaved parallel connection of LLC circuits in accordance with the utility model.
Fig. 2 is a schematic diagram of a peripheral control circuit according to the present utility model.
Detailed Description
In order that the manner in which the above-recited features, advantages, objects and advantages of the utility model are obtained, a more particular description of the utility model will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
As shown in fig. 1 and 2, the present utility model provides a two-stage combining circuit for implementing interleaved parallel connection of LLC circuits, comprising
A first LLC circuit and a second LLC circuit arranged in parallel,
a first BUCK circuit connected with the input end of the first LLC circuit and forming a main loop,
a second BUCK circuit connected with the input end of the second LLC circuit and forming a secondary loop,
and peripheral control circuitry for controlling the primary loop and the secondary loop.
The peripheral control circuit comprises a PWM control chip and an MCU connected with the PWM control chip; the PWM control chip is connected with the first BUCK circuit and controls the main loop by outputting PWM control pulse; the MCU is respectively connected with the PWM control chip, the first BUCK circuit and the second BUCK circuit, replicates the PWM control pulse, and adjusts the phase and the pulse width of the PWM control pulse according to the acquired current values of the first BUCK circuit and the second BUCK circuit to obtain a phase staggered secondary loop control signal.
The input ends of the first BUCK circuit and the second BUCK circuit are connected with a direct current power supply, and the output ends of the first BUCK circuit and the second BUCK circuit are respectively connected with the first LLC circuit or the second LLC circuit.
The first BUCK circuit comprises a current transformer CT1, one end of the current transformer CT1 is connected with a direct current power supply, the other end of the current transformer CT1 is connected with a main switching tube Q1, the main switching tube Q1 is connected with a DR1 port of the MCU, the other end of the main switching tube Q1 is connected with an inductor L1 and a diode D1, and current output by the first BUCK circuit is filtered by a capacitor C1 and then is input into the first LLC circuit.
The second BUCK circuit comprises a current transformer CT2, one end of the current transformer CT2 is connected with a direct current power supply, the other end of the current transformer CT2 is connected with a main switching tube Q2, the main switching tube Q2 is connected with a DR2 port of the MCU, the other end of the main switching tube Q2 is connected with an inductor L2 and a diode, and current output by the BUCK circuit is filtered by a capacitor C2 and then is input into the second LLC circuit.
The first LLC circuit comprises a main switching tube Q3 and a main switching tube Q4 which are connected in series, the main switching tube Q3 and the main switching tube Q4 and the main switching tube Q5 and the main switching tube Q6 which are connected in series form a full-bridge front and rear arm, a resonance capacitor LS1 is arranged between the main switching tube Q3 and the main switching tube Q4, the resonance capacitor LS1 is connected with one end of a transformer T1, and a diode D3 and a diode D4 are arranged at the other end of the transformer T1.
The second LLC circuit comprises a main switching tube Q7 and a main switching tube Q8 which are connected in series, the main switching tube Q7 and the main switching tube Q8, a main switching tube Q9 and a main switching tube Q10 which are connected in series form a full-bridge front and rear arm, a resonance capacitor LS2 is arranged between the main switching tube Q7 and the main switching tube Q8, the resonance capacitor LS2 is connected with one end of a transformer T2, and a diode D5 and a diode D6 are arranged at the other end of the transformer T2.
The drive signals of the first LLC circuit and the second LLC circuit are fixed frequency staggered drive signals, and the drive signals come from the output of the MCU.
Examples
CT1, CT2 are current sampling transformers of the previous stage BUCK circuit, and Q1, Q2 (STW 40N 90) connected at the back are main switching tubes of the BUCK circuit. The driving signals are derived from DR1 and DR2 output by MCU (TMS 320F28035 PAGQ). The PWM control pulse is accessed to the MCU by the output terminal DR of U1 (UCC 3842). After MCU processing, two phase-staggered driving signals are generated.
The output of the front-stage BUCK is filtered by C1 and C2 and then is connected into the LLC main circuit connected in parallel with the rear stage. The two LLC circuits are connected in parallel at the output terminal, and in view of the LLC drive signal being a pair of square waves 180 degrees phase shifted generated by the MCU, the output direct current which can be synthesized at the output terminal C3 has a current ripple which is far lower than that of a common single-stage LLC circuit. Even under the condition of large current of the output 120A, the filtering function can be completed by simply setting 1-2 electrolytic capacitors.
One path of BUCK serving as a main control is directly driven by a PWM special chip, the other path of BUCK is driven by an MCU, the MCU copies a similar pulse driving signal when sampling a main PWM driving pulse, and the MCU circuit finely adjusts an output auxiliary loop driving signal according to two paths of BUCK current values obtained by sampling so as to realize current dynamic balance between the two paths.
The two LLC circuits are in parallel operation under the resonance condition, the optimal efficiency can be obtained during staggered driving, and low-ripple direct current can be output after simple filtering because the rectified output contains relatively large direct current components. The BUCK circuit with the two input ends connected in parallel can enable ripple current of the input ends to reach the minimum state through adjustment of the second driving phase.
When the mains supply works normally, the input direct current source can be from the direct rectification output of the mains supply, or can be the output end of the PFC circuit. The BUCK circuits with the two inputs connected in parallel work at the same frequency, and the phases can be staggered, so that ripple current at the input end can be reduced. One of the paths is directly driven by the PWM chip, and the output duty ratio of the other path can be finely adjusted by the MCU so as to balance the output power of the two paths.
The direct current voltages output by the two BUCK circuits are respectively connected into the two LLC main circuits, the two LLC circuits work in a fixed-frequency resonance state, the driving square waves are staggered by 180 degrees in phase, and ripple currents at the output ends after parallel rectification contain larger direct current components, so that the burden of output filter capacitors is greatly reduced.
The circuit is very suitable for the occasion of outputting low-voltage large current and wide-range output voltage of a high-power supply. No very complex digital control and precisely symmetrical device processing requirements are required. The circuit can meet the requirement of wider input and output voltage fluctuation. The method can realize high-efficiency isolation transformation, has simple and clear principle, and is particularly suitable for use in high-power three-phase or single-phase chargers such as vehicle-mounted chargers and forklift chargers.
In this document, the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", "vertical", "horizontal", etc. refer to the directions or positional relationships based on those shown in the drawings, and are merely for clarity and convenience of description of the expression technical solution, and thus should not be construed as limiting the present utility model.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
The foregoing has shown and described the basic principles, principal features and advantages of the utility model. It will be understood by those skilled in the art that the present utility model is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present utility model, and various changes and modifications may be made without departing from the spirit and scope of the utility model, which is defined in the appended claims. The scope of the utility model is defined by the appended claims and equivalents thereof.
Claims (8)
1. A two-stage combining circuit for realizing interleaved parallel connection of LLC circuits, which is characterized by comprising
A first LLC circuit and a second LLC circuit arranged in parallel,
a first BUCK circuit connected with the input end of the first LLC circuit and forming a main loop,
a second BUCK circuit connected with the input end of the second LLC circuit and forming a secondary loop,
and peripheral control circuitry for controlling the primary loop and the secondary loop.
2. The two-stage combining circuit for implementing interleaved parallel of LLC circuits according to claim 1 wherein said peripheral control circuit comprises a PWM control chip, and an MCU connected to the PWM control chip; the PWM control chip is connected with the first BUCK circuit and controls the main loop by outputting PWM control pulse; the MCU is respectively connected with the PWM control chip, the first BUCK circuit and the second BUCK circuit, replicates the PWM control pulse, and adjusts the phase and the pulse width of the PWM control pulse according to the acquired current values of the first BUCK circuit and the second BUCK circuit to obtain a phase staggered secondary loop control signal.
3. The two-stage combining circuit for realizing interleaved parallel of LLC circuits according to claim 2, wherein the input terminals of the first and second BUCK circuits are connected to a dc power supply, and the output terminals of the first and second BUCK circuits are connected to the first or second LLC circuits, respectively.
4. The two-stage combining circuit for realizing interleaved parallel connection of LLC circuits according to claim 3, wherein the first BUCK circuit comprises a current transformer CT1, one end of the current transformer CT1 is connected with a dc power supply, the other end of the current transformer CT1 is connected with a main switching tube Q1, the main switching tube Q1 is connected with a DR1 port of the MCU, the other end of the main switching tube Q1 is connected with an inductor L1 and a diode D1, and the current output by the first BUCK circuit is input into the first LLC circuit after being filtered by a capacitor C1.
5. The two-stage combining circuit for realizing interleaved parallel connection of LLC circuits according to claim 3, wherein the second BUCK circuit comprises a current transformer CT2, one end of the current transformer CT2 is connected with a dc power supply, the other end of the current transformer CT2 is connected with a main switching tube Q2, the main switching tube Q2 is connected with a DR2 port of the MCU, the other end of the main switching tube Q2 is connected with an inductor L2 and a diode, and the current output by the BUCK circuit is filtered by a capacitor C2 and then input into the second LLC circuit.
6. The two-stage combining circuit for realizing interleaved parallel connection of LLC circuits according to claim 2, wherein the first LLC circuit includes a main switching tube Q3 and a main switching tube Q4 connected in series, the main switching tube Q3 and the main switching tube Q4 and a main switching tube Q5 and a main switching tube Q6 connected in series form front and rear arms of a full bridge, a resonance capacitor LS1 is provided between the main switching tube Q3 and the main switching tube Q4, the resonance capacitor LS1 is connected with one end of a transformer T1, and the other end of the transformer T1 is provided with a diode D3 and a diode D4.
7. The two-stage combining circuit for realizing interleaved parallel connection of LLC circuits according to claim 2, wherein the second LLC circuit includes a main switching tube Q7 and a main switching tube Q8 connected in series, the main switching tube Q7 and the main switching tube Q8 and a main switching tube Q9 and a main switching tube Q10 connected in series form front and rear arms of a full bridge, a resonance capacitor LS2 is provided between the main switching tube Q7 and the main switching tube Q8, the resonance capacitor LS2 is connected with one end of a transformer T2, and the other end of the transformer T2 is provided with a diode D5 and a diode D6.
8. The two-stage combining circuit for implementing LLC circuit interleaving in parallel according to claim 2, wherein the drive signals of the first and second LLC circuits are fixed frequency interleaved drive signals, which are derived from the output of the MCU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320650302.8U CN219420603U (en) | 2023-03-29 | 2023-03-29 | Two-stage combined circuit for realizing interleaved parallel connection of LLC circuits |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320650302.8U CN219420603U (en) | 2023-03-29 | 2023-03-29 | Two-stage combined circuit for realizing interleaved parallel connection of LLC circuits |
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| CN219420603U true CN219420603U (en) | 2023-07-25 |
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| CN202320650302.8U Active CN219420603U (en) | 2023-03-29 | 2023-03-29 | Two-stage combined circuit for realizing interleaved parallel connection of LLC circuits |
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