CN219393399U - High voltage thyristor device - Google Patents
High voltage thyristor device Download PDFInfo
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- CN219393399U CN219393399U CN202222864493.6U CN202222864493U CN219393399U CN 219393399 U CN219393399 U CN 219393399U CN 202222864493 U CN202222864493 U CN 202222864493U CN 219393399 U CN219393399 U CN 219393399U
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Abstract
The utility model provides a high-voltage thyristor device. The high voltage thyristor includes a two-step isolation structure that locates the electric field peak at a location remote from the isolation structure's insulating layer, providing better operation at high voltages.
Description
Technical Field
Embodiments relate to the field of circuit protection devices including thyristor devices.
Background
Semiconductor devices, such as thyristors, may be designed according to a particular application. For some applications, known thyristors have been designed as planar semiconductor devices, which may include an isolation diffuser positioned towards the edge of the semiconductor die in which the thyristor device is formed. However, operating at high voltages (such as above 1600V) can be challenging for such thyristor devices.
It is with respect to these and other considerations that the present disclosure is provided.
Disclosure of Invention
In one embodiment, a high voltage thyristor device is provided. The high voltage thyristor device may include a substrate layer formed inside the substrate and including a first type of polarity. The high voltage thyristor device may further include: a first dopant layer disposed on a first portion of the first major surface of the substrate, the first dopant layer comprising a second type of polarity; and a second dopant layer disposed on a second major surface of the substrate opposite the first major surface, the second dopant layer comprising a second type of polarity. The high voltage thyristor device may further comprise a third dopant layer having a first type of polarity disposed on the second portion of the first major surface. The high voltage thyristor device may further include: a first two-step isolation structure formed on the first major surface and extending from the first major surface into the substrate layer; and a second two-step isolation structure formed on the second major surface and extending from the second major surface into the substrate layer.
In a further embodiment, a high voltage thyristor device is provided that includes an N-layer formed inside a substrate. The high voltage thyristor device may further include: a first P layer disposed on a first portion of the first major surface of the substrate; a second P layer disposed on a second major surface of the substrate opposite the first major surface; and an n+ layer disposed on the second portion of the first major surface within the first P layer. The high voltage thyristor device may further comprise a plurality of two-step isolation structures formed on the first and second major surfaces.
Drawings
FIG. 1A illustrates one implementation of a high voltage thyristor device according to an embodiment of the disclosure;
fig. 1B illustrates another implementation of a high voltage thyristor device according to an embodiment of the disclosure;
fig. 1C illustrates yet another implementation of a high voltage thyristor device according to an embodiment of the disclosure;
fig. 1D illustrates another implementation of a high voltage thyristor device according to an embodiment of the disclosure;
FIG. 1E shows a top view of the isolation structure of the embodiment of FIG. 1A;
fig. 2A shows simulation results of a high voltage thyristor device having a two-step isolation structure according to an embodiment of the present disclosure; and
fig. 2B shows simulation results for a reference device with a single step isolation structure.
Detailed Description
The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. The embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope thereof to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
In the following description and/or claims, the terms "over … …," "overlying … …," "disposed over … …," and "above" may be used in the following description and claims. "on … …," "overlying … …," "disposed on … …," and "above" may be used to indicate that two or more elements are in direct physical contact with each other. Furthermore, the terms "on … …," "overlying … …," "disposed over … …," and "above" may mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is above another but not in contact with each other, and that there may be another element or elements between the two elements.
In various embodiments, novel apparatus structures for forming high voltage thyristor devices are provided.
Fig. 1A-1D illustrate a number of different implementations of a thyristor device according to embodiments of the present disclosure. In general, a thyristor device according to the present embodiment may include a substrate layer that is formed inside a substrate and has a first type of polarity. The thyristor device may further include a first dopant layer disposed on a first portion of the first major surface of the substrate, wherein the first dopant layer has a polarity of a second type opposite the first type. The thyristor device may further include a second dopant layer disposed on a second major surface of the substrate opposite the first major surface, the second dopant layer also having a second type of polarity. In addition, the thyristor device may further include a third dopant layer disposed on the second portion of the first major surface, the third dopant layer having a polarity of the first type. The thyristor device may further include: a first two-step isolation structure formed on the first major surface and extending from the first major surface into the substrate layer; and a second two-step isolation structure formed on the second major surface and extending from the second major surface into the substrate layer.
Turning now to fig. 1A, a thyristor device 100 is shown formed in a substrate 102 comprising a substrate layer 104 having a first polarity type, and in this particular case shown in fig. 1A, the substrate 102 is an N-type substrate. According to some embodiments of the present disclosure, the dopant concentration of the N-type dopant may range from 2e13/cm 3 And 1e14/cm 3 Between them.
The thyristor device 100 may include a first dopant layer 106 disposed on a first surface, in this example a top major surface, of the substrate 102. As shown, the first dopant layer 106 is a P layer having a second type of polarity. Thus, the first dopant layer 106 forms a P/N junction with the substrate layer 104. In various embodiments, the dopant concentration of the first dopant layer 106 may range from 5e13/cm 3 To 3e16/cm 3 。
The thyristor device 100 further comprises a second dopant layer 108, which is arranged on a second main surface of the substrate 102, opposite to the first main surface, in this example meaning the lower main surface. According to the present embodiment, the second dopant layer 108 is formed of a second type of polarity, in this example a P-type dopant. In particular, the second dopant layer 108 mayWith a density of 5e13/cm 3 To 3e16/cm 3 Dopant concentration in the range. Thus, the interior of the substrate 102 forms a substrate layer 104 that maintains N-type polarity.
The thyristor device 100 further comprises a third dopant layer 110 disposed on a second portion of the first major surface of the substrate 102. As shown in fig. 1A, the third dopant layer 110 has a first type of polarity, in this case an n+ layer in the particular embodiment shown. In particular, the dopant concentration of the patterned layer 110 is 5e15/cm 3 To 2e20/cm 3 Within a range of (2). According to an embodiment of the present disclosure, the third dopant layer 110 is interspersed with the second dopant layer 108.
In general, adjustments to the precise patterning of the third dopant layer 110 may be used to adjust the electrical characteristics of the thyristor device 100. As shown in fig. 1A, the thyristor device 100 may further have: a cathode contact 112 disposed to contact the third dopant layer; a gate contact 114 separated from the cathode contact 112 by a spacer 126 and disposed in contact with the first dopant layer 106; and an anode contact 111 disposed to contact the second dopant layer 108.
The thyristor device 100 may further include: a first two-step isolation structure 120 formed on and extending from the first major surface (upper surface in the drawing) into the substrate layer 104; and a second two-step isolation structure 120A formed on the second main surface and extending from the second main surface (lower surface) into the substrate layer 104. In the particular embodiment of fig. 1A, the first two-step isolation structure 120 and the second two-step isolation structure 120A each include an inner isolation structure 122 arranged as a mesa (mesa) and an outer isolation structure 124 arranged as a trench (moat). The mesa and trench may each include an insulating layer, such as an oxide, disposed in the surface region.
As shown, a lower portion of the trench extends into the substrate layer 104, and an upper portion of the trench extends to a major surface of the substrate, wherein the major surface is either the first major surface or the second major surface. In the particular embodiment shown, the substrate 102 includes a first edge (left side) and a second edge (right side), wherein the trench of the first two-step isolation structure and the trench of the second two-step isolation structure do not intersect the first edge or the second edge. Such a configuration may reduce defects in the thyristor device 100, as it will be appreciated that the edge of the substrate 102 may be formed by dicing a semiconductor wafer. During the dicing process to form the thyristor device 100, the dicing does not intersect the insulating layer (such as oxide), thus avoiding the creation of possible defects due to dicing through such oxide layers.
Turning now to fig. 1B, a thyristor device 100A formed in a substrate 102 and including a substrate layer 104, the substrate layer 104 having a first polarity type; in this particular case shown in fig. 1B, the substrate layer 104 has an N-type polarity. In general, the thyristor device 100A may be arranged similarly to the thyristor device 100, with similar features being identically labeled. The thyristor device 100A differs from the thyristor device 100 in that although the third dopant layer 110A is still an n+ layer, it is continuous over the first major surface. Accordingly, the electrical characteristics of the thyristor device 100A may be slightly different from those of the thyristor device 100. In particular, by varying the amount of n+ portions on the first major surface between the third dopant layer 110A and the implementation of the third dopant layer 110, the gate trigger current rating may be varied depending on the desired device characteristics. For example, in general, the gate trigger current of the thyristor device 100 may be greater than 1mA, while in the thyristor device 100A, the gate trigger current may be less than 200 μΑ.
Turning now to fig. 1C, a thyristor device 100C is shown, which is formed in a substrate 102 and includes a substrate layer 104 having a first polarity type, as in fig. 1A and 1B, and in this particular case is an N-type substrate, as shown in fig. 1C. In general, the thyristor device 100B may be arranged similarly to the thyristor device 100 and the thyristor device 100A, with similar features being identically labeled. The thyristor device 100B differs from the thyristor device 100 and the thyristor device 100A in that the two-step isolation structure has a slightly different structure. In particular, a first two-step isolation structure 130 and a second two-step isolation structure 130A are shown on the first and second major surfaces of the substrate 102, respectively. Each of the first two-step isolation structure 130 and the second two-step isolation structure 130A includes an inner isolation structure 122 arranged as a first mesa and an outer isolation structure 124A arranged as a second mesa, wherein the second mesa extends into the substrate layer 104.
Turning now to fig. 1D, a thyristor device 100C is shown formed in a substrate 102 and comprising a substrate layer 104 of a first polarity type, and in this particular case an N-type substrate, shown in fig. 1C. In general, the thyristor device 100C may be arranged similarly to the thyristor device 100B, with similar features being identically labeled. The thyristor device 100C differs from the thyristor device 100C in that, although the third dopant layer 110A is still an n+ layer, it is continuous over the first major surface. Accordingly, the electrical characteristics of the thyristor device 100C may be slightly different from those of the thyristor device 100B. In particular, as described above, the gate trigger current rating may vary depending on the desired device characteristics. For example, in general, the gate trigger current of the thyristor device 100B may be greater than 1mA, while in the thyristor device 100C, the gate trigger current may be less than 200 μa.
Fig. 1E shows a top view of the isolation structure of the embodiment of fig. 1A. According to embodiments of the present disclosure, a two-step isolation structure may be formed by first performing a deep-grid lithography (deep grid photolithography) and silicon etching process (feature 152 of fig. 1E), followed by a shallow-grid lithography and silicon etching process (feature 150).
An advantage of this embodiment is that during operation of the thyristor device manufactured according to the above structure, peaks in the electric field do not extend into the first two-step isolation structure. This makes such a thyristor device suitable for withstanding high voltage operation of at least 1.6 kV.
To illustrate this advantage, fig. 2A shows simulation results for a high voltage thyristor device having a two-step isolation structure according to an embodiment of the present disclosure, while fig. 2B shows simulation results for a reference device having a single-step isolation structure. In fig. 2A, the peak P of the electric field is well away from the insulating layer of the second two-step isolation structure 120A at 2.5kv Vr. In fig. 2B, at 1.6kV Vr, the peak P in the electric field is within the insulating layer of the illustrated single step isolation layer.
In summary, the present embodiment provides an improved high voltage thyristor device that is better able to withstand high voltage operation due to the provision of a two-step isolation structure. Such a two-step isolation structure tends to locate peaks in the electric field within the bulk of the substrate, away from the insulating layer of the isolation structure, under high voltage Vr conditions.
Although the present embodiment has been disclosed with reference to some embodiments, many modifications, substitutions and changes can be made to the described embodiments without departing from the field and scope of the present disclosure as defined in the appended claims. Thus, the present disclosure is not limited to the embodiments described, but has the full scope defined by the language of the following claims and equivalents thereof.
Claims (15)
1. A high voltage thyristor device, comprising:
a substrate layer formed inside the substrate and including a first type of polarity;
a first dopant layer disposed on a first portion of the first major surface of the substrate, the first dopant layer comprising a second type of polarity;
a second dopant layer disposed on a second major surface of the substrate opposite the first major surface, the second dopant layer comprising the second type of polarity;
a third dopant layer disposed on a second portion of the first major surface, the third dopant layer comprising the first type of polarity;
a first two-step isolation structure formed on the first major surface and extending from the first major surface into the substrate layer; and
a second two-step isolation structure formed on the second major surface and extending from the second major surface into the substrate layer.
2. The high voltage thyristor device of claim 1,
the substrate layer includes an N-region, the first dopant layer includes a first P-layer, the second dopant layer includes a second P-layer, and the third dopant layer includes an n+ layer.
3. The high voltage thyristor device of claim 2,
the third dopant layer includes a plurality of n+ regions.
4. The high voltage thyristor device of claim 2, further comprising:
a first contact disposed on a first portion of the first major surface;
a gate contact disposed on a second portion of the first major surface; and
an anode contact disposed on the second major surface.
5. The high voltage thyristor device of claim 1, wherein the first two-step isolation structure and the second two-step isolation structure each comprise:
an internal isolation structure arranged as a mesa; and
an external isolation structure arranged as a trench.
6. The high voltage thyristor device of claim 5, wherein a lower portion of the trench extends into the substrate layer, and wherein an upper portion of the trench extends to a major surface of the substrate, the major surface being the first major surface or the second major surface.
7. The high voltage thyristor device of claim 6, wherein the substrate comprises a first edge and a second edge, wherein the trench does not intersect the first edge or the second edge.
8. The high voltage thyristor device of claim 1, wherein the first two-step isolation structure and the second two-step isolation structure each comprise:
an internal isolation structure arranged as a first mesa; and
an external isolation structure arranged as a second mesa, wherein the second mesa extends into the substrate layer.
9. A high voltage thyristor device, comprising:
an N-layer formed inside the substrate;
a first P layer disposed on a first portion of the first major surface of the substrate;
a second P layer disposed on a second major surface of the substrate opposite the first major surface;
an n+ layer disposed within the first P layer at a second portion of the first major surface; and
a plurality of two-step isolation structures formed on the first major surface and the second major surface.
10. The high voltage thyristor device of claim 9,
the n+ layer includes a plurality of n+ regions.
11. The high voltage thyristor device of claim 10, further comprising:
a first contact disposed on the n+ layer;
a gate contact disposed on a portion of the first P layer; and
an anode contact disposed on the second P layer.
12. The high voltage thyristor device of claim 9, wherein a first isolation structure of the plurality of two-step isolation structures is formed on the first major surface and a second isolation structure of the plurality of two-step isolation structures is formed on the second major surface, wherein each of the first isolation structure and the second isolation structure comprises:
an internal isolation structure arranged as a mesa; and
an external isolation structure arranged as a trench.
13. The high voltage thyristor device of claim 12, wherein a lower portion of the trench extends into the N-layer, and wherein an upper portion of the trench extends to a major surface of the substrate, the major surface being the first major surface or the second major surface.
14. The high voltage thyristor device of claim 13, wherein the substrate comprises a first edge and a second edge, wherein the trench does not intersect the first edge or the second edge.
15. The high voltage thyristor device of claim 9, wherein a first isolation structure of the plurality of two-step isolation structures is formed on the first major surface and a second isolation structure of the plurality of two-step isolation structures is formed on the second major surface, wherein the first isolation structure and the second isolation structure each comprise:
an internal isolation structure arranged as a first mesa; and
an external isolation structure arranged as a second mesa, wherein the second mesa extends into the N-layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202222864493.6U CN219393399U (en) | 2022-10-27 | 2022-10-27 | High voltage thyristor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222864493.6U CN219393399U (en) | 2022-10-27 | 2022-10-27 | High voltage thyristor device |
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| CN219393399U true CN219393399U (en) | 2023-07-21 |
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| CN202222864493.6U Active CN219393399U (en) | 2022-10-27 | 2022-10-27 | High voltage thyristor device |
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