CN219352274U

CN219352274U - Array substrate and display panel

Info

Publication number: CN219352274U
Application number: CN202320328279.0U
Authority: CN
Inventors: 陈国朵; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-07-14
Anticipated expiration: 2033-02-20

Abstract

The application relates to an array substrate and display panel, array substrate includes the display region and is located the fan-shaped wiring district of display region one side, and array substrate includes and follows the display region and extend to fan-shaped a plurality of signal lines of wiring district, wherein, in fan-shaped wiring district, the signal line range upon range of arrangement is in two-layer metal level at least, and the signal line has interconnect's sharp portion and kink, and is located the length of the sharp portion of upper metal layer and be less than the length of the sharp portion that is located its lower floor's metal layer. The array substrate can reduce the risk of climbing and breaking or short-circuiting of the signal wires in the fan-shaped wiring area, and improves the reliability of the display panel.

Description

Array substrate and display panel

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.

Background

In fan-shaped wiring area (Fanout) design of small-sized display, because the wiring space is small and single-layer metal wiring cannot be realized, part of signal wires need to be designed in a jumper manner, so that laminated design of a plurality of signal wires exists in the fan-shaped wiring area. But there is a risk of a hill-climbing wire break or a short circuit in the laminated portion of the signal wire during the process.

Disclosure of Invention

The purpose of the application is to provide an array substrate, a preparation method thereof and a display panel, which can reduce the risk of climbing broken wires or short circuits of partial signal wires in a fan-shaped wiring area and improve the reliability of the display panel.

In a first aspect, an embodiment of the present application provides an array substrate, including a display area and a fan-shaped wiring area located at one side of the display area, where the array substrate includes a plurality of signal lines extending from the display area to the fan-shaped wiring area, the signal lines are stacked and arranged in at least two metal layers in the fan-shaped wiring area, the signal lines have a straight line portion and a bending portion that are connected to each other, and a length of the straight line portion located in an upper metal layer is smaller than a length of the straight line portion located in a lower metal layer.

In one possible embodiment, the bending portion includes a transition portion and a diagonal portion, the transition portion connects the straight portion and the diagonal portion, and the diagonal portion located in the upper metal layer and the diagonal portion located in the lower metal layer at least partially overlap each other.

In one possible embodiment, the width of the transition portion located in the upper metal layer is greater than the width of the overlapping portion of the diagonal portion located in the upper metal layer and the diagonal portion located in the lower metal layer.

In one possible embodiment, a part of the signal lines located in the fan-shaped wiring region and the corresponding signal lines located in the display region are electrically connected with each other through the transfer hole.

In one possible implementation, the array substrate includes a substrate, and a first metal layer, an insulating layer, and a second metal layer sequentially formed on the substrate, where in the display area, a plurality of signal lines are located on the second metal layer, and in the fan-shaped wiring area, a part of the signal lines are transferred Kong Tiaoxian from the second metal layer to the first metal layer through a transfer located on the insulating layer.

In one possible implementation manner, the first metal layer comprises a first signal line etched in the fan-shaped wiring region; the second metal layer comprises a second signal line etched in the fan-shaped wiring area, and the first signal line is intersected with the transition part of the second signal line.

In one possible embodiment, the length of the straight line portion located in the second metal layer is smaller than the length of the straight line portion located in the first metal layer, and the oblique line portion located in the second metal layer and the oblique line portion located in the first metal layer at least partially overlap each other.

In one possible embodiment, the width of the transition portion located in the second metal layer is W1, the width of the overlapping portion of the diagonal portion located in the second metal layer and the diagonal portion located in the first metal layer is W2, and the following condition is satisfied: w1> W2.

In one possible embodiment, w2=1/3×w1 to 1/2×w1.

In a third aspect, an embodiment of the present application provides a display panel, including: an array substrate as hereinbefore described.

According to the array substrate and the display panel provided by the embodiment of the application, the part of the signal wires in the fan-shaped wiring area are arranged in the at least two metal layers in a stacked mode, each signal wire is provided with the straight line part and the bending part which are connected with each other, and the length of the straight line part in the upper metal layer is smaller than that of the straight line part in the lower metal layer. Because in the partial signal line of fan-shaped wiring district, the signal line that is located upper strata metal level is preceding its lower floor's metal level signal line kink and is set up, can reduce the climbing broken line or the short circuit risk of partial signal line that is located upper strata metal level in fan-shaped wiring district, improves display panel's reliability.

Drawings

Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.

Fig. 1 shows a schematic structural diagram of an array substrate provided in an embodiment of the present application;

FIG. 2 is a schematic diagram showing the structure of a fan-shaped wiring region in the related art;

FIG. 3 shows an enlarged schematic view of the fan-shaped routing area of FIG. 1;

FIG. 4 is a schematic cross-sectional view of the fan-shaped wiring region in FIG. 3;

fig. 5 shows a schematic structural diagram of a display panel according to an embodiment of the present application.

Reference numerals illustrate:

1. an array substrate; AA. A display area; FA. A fan-shaped wiring area; l, signal line; l1, a bending part; l11, transition; l12, diagonal line parts; l2, straight line portion; H. a transfer hole;

10. a substrate base; 11. a first metal layer; 111. a first signal line; 12. an insulating layer; 13. a second metal layer; 131. and a second signal line.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing an example of the present application. In the drawings and the following description, at least some well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 shows a schematic structural diagram of an array substrate provided in an embodiment of the present application; fig. 2 is a schematic structural view showing a sector-shaped wiring region in the related art, and fig. 3 is an enlarged schematic structural view showing the sector-shaped wiring region in fig. 1.

As shown in fig. 1 and 3, an embodiment of the present application proposes an array substrate, including a display area AA and a fan-shaped routing area FA located at one side of the display area AA, where the array substrate includes a plurality of signal lines L extending from the display area AA to the fan-shaped routing area FA, and optionally, the signal lines L are data lines.

In the fan-shaped routing area FA, the signal lines L are stacked in at least two metal layers, the signal lines L have a straight line portion L2 and a bent portion L1 that are connected to each other, and the length of the straight line portion L2 located in the upper metal layer is smaller than that of the straight line portion L2 located in the lower metal layer. The straight line portion L2 of the fan-shaped wiring area FA is disposed parallel to the signal line L of the display area.

As shown in fig. 2, in the related art, the data lines of the fan-shaped routing area FA are stacked in two metal layers, and the data lines of the upper metal layer are longer than the data lines of the lower metal layer in turn, so that the data lines of the upper metal layer are more likely to climb and break at the overlapping positions of the metal layers than the data lines of the lower metal layer, and short circuits are likely to occur during the manufacturing process.

In order to solve the above technical problem, in the embodiment of the present application, the signal line L located on the upper metal layer is bent before the signal line L located on the lower metal layer, that is, the length of the straight line portion L2 of the signal line L of the upper metal layer is smaller than the length of the straight line portion L2 of the signal line L of the lower metal layer, so that the overlapping portion of the signal line L of the upper metal layer and the signal line L of the lower metal layer avoids the bending portion L1 of the upper metal layer, and the signal line L of the upper metal layer is prevented from climbing and breaking at the corner of the bending portion L1, thereby reducing the risk of short circuit in the process.

Specifically, as shown in fig. 1 and 3, the array substrate includes a plurality of data lines, a portion of the data lines extend from the display area AA to the fan-shaped wiring area FA and are all located in the same metal layer, and another portion of the data lines jumper into other metal layers in the fan-shaped wiring area FA, i.e. a portion of the data lines in the fan-shaped wiring area FA are stacked and arranged in at least two metal layers, for example, in two metal layers. The signal line L has a straight portion L2 and a bent portion L1 connected to each other, and the end of the bent portion L1 extends to a bonding region, which may be electrically connected to the flip chip film.

In the two metal layers of the fan-shaped wiring area FA, after the data wire of the uppermost metal layer extends at the straight line part L2 for a preset distance, the data wire of the lower metal layer is bent to form a bent part L1, after the data wire of the upper metal layer is crawled for a certain distance, the bent parts L1 of the two data wires are bent to form a bent part L1, and a certain distance is reserved between the bent part L1 of the signal wire L of the upper metal layer and the bent part L1 of the signal wire L of the lower metal layer, so that the overlapping part of the metal layers is avoided, the bent part L1 of the signal wire L of the upper metal layer is prevented from being climbed and broken, and the risk of short circuit in the process is further reduced.

It can be understood that the signal lines L such as the data lines of the fan-shaped routing area FA may be disposed in three or more metal layers, and the signal lines L of the fan-shaped routing area FA are disposed in three metal layers, for example, the bent portion L1 of the signal line L of the uppermost metal layer turns before the bent portion L1 of the signal line L of the middle metal layer below, the bent portion L1 of the signal line L of the middle metal layer turns before the bent portion L1 of the signal line L of the lowermost metal layer, and the bent portions L1 of the signal lines L of the three metal layers are staggered, so that the situation that the bent portions L1 climb and break at the overlapping position can be avoided, and the risk of short circuit in the process is reduced.

According to the array substrate provided by the embodiment of the application, the part of the signal lines L positioned in the fan-shaped wiring area FA are arranged in at least two metal layers which are arranged in a stacked mode, each signal line L is provided with the straight line part L2 and the bending part L1 which are connected with each other, and the length of the straight line part L2 positioned in the upper metal layer is smaller than that of the straight line part L2 positioned in the lower metal layer. In the partial signal lines L of the fan-shaped wiring area FA, the signal lines L positioned on the upper metal layer are bent before the signal lines L positioned on the lower metal layer, so that the risk of climbing and breaking or short-circuiting of the partial signal lines L positioned on the upper metal layer in the fan-shaped wiring area FA can be reduced, and the reliability of the display panel is improved.

In some embodiments, the bending portion L1 includes a transition portion L11 and a diagonal portion L12, where the transition portion L11 connects the straight portion L2 and the diagonal portion L12, and the diagonal portion L12 located in the upper metal layer and the diagonal portion L12 located in the lower metal layer at least partially overlap each other.

As shown in fig. 3, the length of the straight line portion L2 located in the upper metal layer is smaller than that of the straight line portion L2 located in the lower metal layer, so that the signal line L located in the upper metal layer is bent before the signal line L located in the lower metal layer. The oblique line part L12 positioned on the upper metal layer and the oblique line part L12 positioned on the lower metal layer are at least partially overlapped with each other, so that the wiring space of the fan-shaped wiring area FA can be greatly reduced under the condition that the same resolution and the total number of data lines are kept unchanged, and the narrow frame design is realized.

In some embodiments, the width of the transition portion L11 located in the upper metal layer is greater than the width of the overlapping portion of the diagonal line portion L12 located in the upper metal layer and the diagonal line portion L12 located in the lower metal layer.

As shown in fig. 3, the transition portion L11 is located between the straight portion L2 and the oblique line portion L12, and the signal lines L of the adjacent two metal layers intersect at the transition portion L11 and overlap each other at the oblique line portion L12. The width of the transition part L11 positioned on the upper metal layer is larger than that of the oblique line part L12 which is formed by mutually overlapping two adjacent layers, so that the connection strength of the signal line L of the upper metal layer at the bending part L1 can be further improved, and the risks of climbing broken lines and short circuits are reduced.

Fig. 4 shows a schematic cross-sectional structure of the fanout area in fig. 3.

In some embodiments, a portion of the signal lines L located in the fan-shaped wiring area FA and the corresponding signal lines L located in the display area are electrically connected to each other through the transfer hole H.

As shown in fig. 3 and fig. 4, a part of signal lines L located in the fan-shaped wiring area FA and corresponding signal lines L located in the display area are located in different metal layers, and are electrically connected with each other through a transfer hole H. The other part of the signal lines L in the fan-shaped wiring area FA and the corresponding signal lines L in the display area are positioned in the same metal layer, the two parts of the signal lines L are intersected at the transition part L11 of the fan-shaped wiring area FA, and the two parts of the signal lines L are mutually overlapped at the oblique line part L12 so as to reduce the wiring space of the fan-shaped wiring area FA.

In some embodiments, the array substrate includes a substrate 10, a first metal layer 11, an insulating layer 12, and a second metal layer 13 sequentially formed on the substrate 10, in the display area AA, a plurality of signal lines L are located on the second metal layer 13, in the fan-shaped routing area FA, a portion of the signal lines L are jumped from the second metal layer 13 to the first metal layer 11 through a via H located on the insulating layer 12.

In one example, as shown in fig. 4, the signal lines L located in the fan-shaped wiring area FA are arranged in the first metal layer 11 and the second metal layer 13 which are stacked, a part of the signal lines L is jumped to the first metal layer 11 from the second metal layer 13 through the transfer hole H located in the insulating layer 12, the signal lines of the first metal layer 11 and the second metal layer 13 intersect at the transition portion L11 of the fan-shaped wiring area FA, and overlap each other at the oblique line portion L12 to reduce the wiring space of the fan-shaped wiring area FA.

In other examples, the signal lines L located in the fan-shaped routing area FA are arranged in three metal layers which are stacked, a part of the signal lines L are located in the uppermost metal layer, a part of the signal lines L are jumped to the middle metal layer through the transfer holes H, another part of the signal lines L are jumped to the lowermost metal layer through the transfer holes H, and the transfer holes H are staggered with each other. Under the condition of keeping the same resolution and the total number of the data lines unchanged, the wiring space of the fan-shaped wiring area FA can be further reduced, and the narrow frame design is realized.

In some embodiments, the first metal layer 11 includes a first signal line 111 etched in the fan-shaped wiring area FA; the second metal layer 13 includes a second signal line 131 etched in the fan-shaped wiring region FA, and the first signal line 111 intersects with a transition portion L11 of the second signal line 131.

Since the transition portion L11 of the first signal line 111 and the second signal line 131 intersect, the intersection at the corner, that is, the intersection of the straight line portion L2 and the transition portion L11, can be avoided, so that the risk of the climbing and breaking or the short circuit of the partial signal line L located in the second metal layer 13 in the fan-shaped routing area FA can be reduced, and the reliability of the array substrate can be improved.

Further, the length of the straight line portion L2 located in the second metal layer 13 is smaller than the length of the straight line portion L2 located in the first metal layer 11, and the oblique line portion L12 located in the second metal layer 13 and the oblique line portion L12 located in the first metal layer 11 overlap each other at least partially.

Since the length of the straight line portion L2 located on the second metal layer 13 is smaller than that of the straight line portion L2 located on the first metal layer 11, the signal line L located on the second metal layer 13 is bent before the signal line L located on the first metal layer 11, and the oblique line portion L12 located on the second metal layer 13 and the oblique line portion L12 located on the first metal layer 11 are at least partially overlapped with each other, so that the wiring space of the fan-shaped wiring area FA can be greatly reduced under the condition that the same resolution and the total number of data lines are kept unchanged, and a narrow frame design is realized.

Further, if the width of the transition portion L11 located in the second metal layer 13 is W1 and the width of the overlapping portion between the oblique line portion L12 located in the second metal layer 13 and the oblique line portion L12 located in the first metal layer 11 is W2, the following condition is satisfied: w1> W2.

Since the width W1 of the transition portion L11 of the second metal layer 13 is greater than the width W2 of the oblique line portion L12 where the first metal layer 11 and the second metal layer 13 overlap each other, the connection strength of the signal line L of the second metal layer 13 at the bending portion L1 can be further improved, and the risk of climbing a broken line and short circuit can be reduced.

Further, the width W1 of the transition portion L11 and the width W2 of the mutually overlapping portion at the second metal layer 13 also satisfy the following condition: w2=1/3×w1 to 1/2×w1. In one example, w1=10 μm, w2=0.4 μm to 0.5 μm. The arrangement meets the electrical connection performance and the climbing line width requirement.

The embodiment of the application also provides a display panel, which comprises any one of the array substrates. The display panel can be implemented as a Liquid Crystal Display (LCD) panel or an Organic Light Emitting Diode (OLED) display panel, for example, and is applied to any product or component having a display function, such as a smart phone, an electronic book, a tablet computer, a wearable device, a digital photo frame, a navigator, and the like.

In one example, as shown in fig. 5, the display panel is an OLED display panel, and includes an array substrate 100, and a pixel defining layer 200, a light emitting structure 210, a cathode layer 220, and an encapsulation layer 230 on the array substrate 100.

The pixel defining layer 200 includes a plurality of pixel openings, and the light emitting layer 210 includes a plurality of light emitting elements distributed in an array, each light emitting element corresponding to a pixel opening of the pixel defining layer 200, the pixel opening exposing the anode electrode 110 of the array substrate 100. The light emitting element further includes a light emitting structure 210 on the anode 110 and a cathode layer 220 on the light emitting structure 210.

The encapsulation layer 230 is located on a side of the cathode layer 220 facing away from the array substrate 100. The encapsulation layer 230 includes a first inorganic layer, an organic layer, and a second inorganic layer, which are sequentially stacked. The inorganic material has good light transmission performance and good water-oxygen barrier performance. The organic layer is a patterned organic layer, which has high elasticity, and the organic layer is sandwiched between the first inorganic layer and the second inorganic layer, so that the cracking of the inorganic film can be inhibited, the stress between inorganic substances can be released, and the flexibility of the whole packaging layer 230 can be improved, thereby realizing reliable flexible packaging.

In another example, the display panel may also be a liquid crystal display panel, including an array substrate, a color film substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.

According to the display panel provided by the embodiment of the application, the part of the signal lines L of the array substrate, which are positioned in the fan-shaped wiring area FA, are arranged in at least two metal layers which are arranged in a stacked manner, each signal line L is provided with the bending part L1, and the shortest distance between the bending part L1 of the upper metal layer and the display area AA is smaller than the shortest distance between the bending part L1 of the lower metal layer and the display area AA. In the partial signal lines L of the fan-shaped wiring area FA, the signal lines L positioned on the upper metal layer are bent before the signal lines L positioned on the lower metal layer, so that the risk of climbing and breaking or short-circuiting of the partial signal lines L positioned on the upper metal layer in the fan-shaped wiring area FA can be reduced, and the reliability of the display panel is improved.

It should be readily understood that the terms "on … …", "above … …" and "above … …" in this application should be interpreted in the broadest sense such that "on … …" means not only "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes the meaning of "not only" on something "or" above "but also" above "or" above "without intermediate features or layers therebetween (i.e., directly on something).

The term "substrate base" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. In addition, the substrate base may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate comprising a display area and a fan-shaped wiring area positioned at one side of the display area, the array substrate comprising a plurality of signal wires extending from the display area to the fan-shaped wiring area, characterized in that,

in the fan-shaped wiring area, the signal wires are arranged in at least two layers of metal layers in a stacked mode, the signal wires are provided with straight line parts and bending parts which are connected with each other, and the length of the straight line parts positioned on the upper layer of metal layers is smaller than that of the straight line parts positioned on the lower layer of metal layers.

2. The array substrate of claim 1, wherein the bending portion includes a transition portion and a diagonal portion, the transition portion connects the straight portion and the diagonal portion, and the diagonal portion on the upper metal layer and the diagonal portion on the lower metal layer overlap each other at least partially.

3. The array substrate of claim 2, wherein the transition portion of the upper metal layer has a width greater than a width of a portion of the layer where the diagonal portion overlaps with the diagonal portion of the lower metal layer.

4. The array substrate of claim 1, wherein a portion of the signal lines located in the fan-shaped wiring region and the corresponding signal lines located in the display region are electrically connected to each other through a transfer hole.

5. The array substrate according to claim 2, wherein the array substrate comprises a substrate and a first metal layer, an insulating layer and a second metal layer sequentially formed on the substrate, the plurality of signal lines are located on the second metal layer in the display area, and part of the signal lines are jumped to the first metal layer from the second metal layer through a transfer hole located on the insulating layer in the fan-shaped wiring area.

6. The array substrate of claim 5, wherein the first metal layer comprises first signal lines etched in the fan-shaped wiring region; the second metal layer comprises a second signal line etched in the fan-shaped wiring region, and the first signal line is intersected with the transition part of the second signal line.

7. The array substrate of claim 5, wherein the length of the straight line portion located in the second metal layer is smaller than the length of the straight line portion located in the first metal layer, and the diagonal line portion located in the second metal layer and the diagonal line portion located in the first metal layer at least partially overlap each other.

8. The array substrate of claim 5, wherein the width of the transition portion at the second metal layer is W1, the width of the overlapping portion between the oblique line portion at the second metal layer and the oblique line portion at the first metal layer is W2, and the following condition is satisfied: w1> W2.

9. The array substrate of claim 8, wherein,

W2＝1/3*W1～1/2*W1。

10. a display panel, comprising: the array substrate of any one of claims 1 to 9.