CN219329260U - Packaging structure - Google Patents
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- CN219329260U CN219329260U CN202223433523.4U CN202223433523U CN219329260U CN 219329260 U CN219329260 U CN 219329260U CN 202223433523 U CN202223433523 U CN 202223433523U CN 219329260 U CN219329260 U CN 219329260U
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- 238000004806 packaging method and process Methods 0.000 title abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 230000032798 delamination Effects 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- IYHHRZBKXXKDDY-UHFFFAOYSA-N BI-605906 Chemical compound N=1C=2SC(C(N)=O)=C(N)C=2C(C(F)(F)CC)=CC=1N1CCC(S(C)(=O)=O)CC1 IYHHRZBKXXKDDY-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- STBLNCCBQMHSRC-BATDWUPUSA-N (2s)-n-[(3s,4s)-5-acetyl-7-cyano-4-methyl-1-[(2-methylnaphthalen-1-yl)methyl]-2-oxo-3,4-dihydro-1,5-benzodiazepin-3-yl]-2-(methylamino)propanamide Chemical compound O=C1[C@@H](NC(=O)[C@H](C)NC)[C@H](C)N(C(C)=O)C2=CC(C#N)=CC=C2N1CC1=C(C)C=CC2=CC=CC=C12 STBLNCCBQMHSRC-BATDWUPUSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229940125878 compound 36 Drugs 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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Abstract
本实用新型涉及一种封装结构,封装结构包括线路层。线路层包括介电层和焊盘,焊盘内埋于介电层内,并且焊盘由介电层的顶表面暴露,焊盘的上表面与介电层的顶表面对齐。封装结构还包括金属层,金属层设置在焊盘与介电层之间的界面上方。本申请的上述技术方案通过在介电层和焊盘之间的界面上方设置金属层,至少可以避免介电层与焊盘之间的界面处分层问题。
The utility model relates to a packaging structure, which includes a circuit layer. The circuit layer includes a dielectric layer and a pad, the pad is embedded in the dielectric layer, and the pad is exposed from the top surface of the dielectric layer, and the top surface of the pad is aligned with the top surface of the dielectric layer. The package structure also includes a metal layer disposed over the interface between the pad and the dielectric layer. The above technical solution of the present application can at least avoid the problem of delamination at the interface between the dielectric layer and the pad by disposing the metal layer above the interface between the dielectric layer and the pad.
Description
技术领域technical field
本实用新型涉及半导体技术领域,更具体地,涉及一种封装结构。The utility model relates to the technical field of semiconductors, in particular to a packaging structure.
背景技术Background technique
参考图1A至图1D所示,现行芯片后装(chip last)制程可以包括以下步骤:参考图1A所示,在重分布层(RDL,Redistribution Layer)载体10上形成扇出(Fan-out)重分布层20;参考图1B所示,在重分布层20上连接电子器件32并使用模塑料36模制电子器件32,并且在模塑料36和电子器件32上方设置载体40;参考图1C所示,去除图1B中的重分布层载体10,暴露重分布层20的介电层22和焊盘24;参考图1D所示,将图1C所示的结构倒置,再在重分布层20的暴露的焊盘24上形成焊球50。Referring to FIG. 1A to FIG. 1D, the current chip last process may include the following steps: Referring to FIG. 1A, fan-out (Fan-out) is formed on a redistribution layer (RDL, Redistribution Layer)
在上述现行芯片后装制程中,在去除图1B中连接焊盘24的重分布层载体10之后,因焊盘24的用以连接焊球50的接合面与介电层22的表面接近齐平且彼此不覆盖(见图1D),因此可能面临以下两个问题:In the above-mentioned current chip post-assembly process, after removing the
(1)如图1E所示,介电层22的表面和焊盘24的接合面齐平,容易因热应力使介电层22与焊盘24之间的界面处有产生分层55的风险。(1) As shown in FIG. 1E , the surface of the
(2)如图1F所示,焊盘24的接合面为非碗形结构,落球(ball drop)后的回流过程中,焊球50会有滑动风险,造成焊球50未连接在焊盘24上,或可能造成焊球50桥接(ballbridge)。现有的焊球形成良率预估只有80%,可靠度风险较高。(2) As shown in FIG. 1F , the bonding surface of the
如图2所示,上述问题虽然可以利用另外一层介电层62覆盖重分布层20的介电层22与焊盘24之间的界面来解决如图1E所示的分层问题,并且可以通过在介电层22上开孔暴露焊盘24形成碗形结构来解决如图1F所示的焊球滑动风险,但是将使介电层62覆盖部分焊盘24,而影响电性效能。As shown in FIG. 2, although the above problem can be solved by using another layer of
实用新型内容Utility model content
针对相关技术中的上述问题,本实用新型提出一种封装结构,至少可以解决焊盘与介电层之间界面处的分层问题。In view of the above problems in the related art, the utility model proposes a packaging structure, which can at least solve the delamination problem at the interface between the pad and the dielectric layer.
根据本实用新型的实施例,提供了一种封装结构。封装结构包括线路层。线路层包括介电层和焊盘,焊盘内埋于介电层内,并且焊盘由介电层的顶表面暴露,焊盘的上表面与介电层的顶表面对齐。封装结构还包括金属层,金属层设置在焊盘与介电层之间的界面上方。According to an embodiment of the present invention, a packaging structure is provided. The encapsulation structure includes a wiring layer. The circuit layer includes a dielectric layer and a pad, the pad is embedded in the dielectric layer, and the pad is exposed from the top surface of the dielectric layer, and the top surface of the pad is aligned with the top surface of the dielectric layer. The package structure also includes a metal layer disposed over the interface between the pad and the dielectric layer.
在一些实施例中,封装结构还包括电连接件,金属层具有暴露焊盘的开口,电连接件穿过开口连接到焊盘,使得电连接件位于焊盘上方。In some embodiments, the package structure further includes an electrical connector, the metal layer has an opening exposing the pad, and the electrical connector is connected to the pad through the opening so that the electrical connector is located above the pad.
在一些实施例中,金属层为环形结构,并暴露焊盘的上表面的一部分。In some embodiments, the metal layer is a ring structure and exposes a portion of the upper surface of the pad.
在一些实施例中,封装结构还包括电连接件,电连接件接触金属层及焊盘的上表面的一部分。In some embodiments, the package structure further includes an electrical connector contacting the metal layer and a portion of the upper surface of the pad.
在一些实施例中,封装结构还包括晶种层,晶种层位于界面与金属层之间。In some embodiments, the package structure further includes a seed layer located between the interface and the metal layer.
在一些实施例中,金属层的下表面的一部分接触介电层的顶表面,金属层的下表面的另一部分接触焊盘的上表面。In some embodiments, a portion of the lower surface of the metal layer contacts the top surface of the dielectric layer and another portion of the lower surface of the metal layer contacts the upper surface of the pad.
在一些实施例中,焊盘的上表面为第一上表面,焊盘还具有低于第一上表面的第二上表面,金属层从第一上表面延伸到第二上表面上。In some embodiments, the upper surface of the pad is a first upper surface, the pad further has a second upper surface lower than the first upper surface, and the metal layer extends from the first upper surface to the second upper surface.
在一些实施例中,第一上表面围绕第二上表面,金属层暴露焊盘的第二上表面的一部分。In some embodiments, the first upper surface surrounds the second upper surface, and the metal layer exposes a portion of the second upper surface of the pad.
在一些实施例中,封装结构还包括电连接件,电连接件接触金属层及焊盘的第二上表面的一部分。In some embodiments, the package structure further includes an electrical connector contacting the metal layer and a portion of the second upper surface of the bonding pad.
在一些实施例中,电连接件通过金属层与介电层的顶表面隔开。In some embodiments, the electrical connections are separated from the top surface of the dielectric layer by the metal layer.
本申请的上述封装结构,通过在介电层和焊盘之间的界面上方设置金属层,可以避免介电层与焊盘之间界面处的分层问题;可以将电连接件限位在金属层和焊盘上,因此降低了电连接件相对于焊盘的位置偏移,可以解决焊盘的上表面与介电层的顶表面齐平时的滑动风险。另外,与现有通过使用介电层覆盖部分焊盘来解决分层问题和滑动风险会影响电性效能的方式相比,本申请的封装结构可以避免对电性效能的不利影响。The above-mentioned packaging structure of the present application can avoid the delamination problem at the interface between the dielectric layer and the pad by arranging the metal layer above the interface between the dielectric layer and the pad; the electrical connector can be limited to the metal layer layer and pad, thus reducing the positional offset of the electrical connector relative to the pad, which can solve the risk of slippage when the upper surface of the pad is flush with the top surface of the dielectric layer. In addition, compared with the existing method of using a dielectric layer to cover part of the pads to solve the delamination problem and the risk of sliding that will affect the electrical performance, the packaging structure of the present application can avoid adverse effects on the electrical performance.
附图说明Description of drawings
当结合附图进行阅读时,从以下详细描述可最佳理解本实用新型的各个方面。应当注意,根据工业中的标准实践,各个部件并非按比例绘制。事实上,为了清楚讨论,各个部件的尺寸可以任意增大或减小。Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
图1A至图1D现有技术中形成一种封装结构的多个阶段的截面示意图。1A to 1D are schematic cross-sectional views of various stages of forming a packaging structure in the prior art.
图1E和图1F分别是现有技术中产生的分层风险和焊球滑动风险的结构示意图。FIG. 1E and FIG. 1F are structural schematic diagrams of delamination risk and solder ball sliding risk generated in the prior art, respectively.
图2是现有技术中另一种封装结构的截面示意图。FIG. 2 is a schematic cross-sectional view of another package structure in the prior art.
图3A是根据本申请的一个实施例的封装结构的截面示意图。FIG. 3A is a schematic cross-sectional view of a package structure according to an embodiment of the present application.
图3B是图3A所示的金属层的俯视示意图。FIG. 3B is a schematic top view of the metal layer shown in FIG. 3A .
图4是根据本申请的另一实施例的封装结构的截面示意图。FIG. 4 is a schematic cross-sectional view of a package structure according to another embodiment of the present application.
图5是根据本申请的另一实施例的封装结构的截面示意图。FIG. 5 is a schematic cross-sectional view of a package structure according to another embodiment of the present application.
图6A至图6E是根据本申请的实施例形成封装结构的多个阶段的截面示意图。6A to 6E are schematic cross-sectional views of various stages of forming a package structure according to an embodiment of the present application.
具体实施例specific embodiment
下列公开提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面将描述元件和布置的特定实例以简化本实用新型。当然这些仅仅是实例并不旨在限定本实用新型。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括在第一部件和第二部件之间形成额外的部件使得第一部件和第二部件可以不直接接触的实施例。而且,本实用新型在各个实例中可重复参考数字和/或字母。这种重复仅是为了简明和清楚,其自身并不表示所论述的各个实施例和/或配置之间的关系。The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to limit the utility model. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are in direct contact, or may include forming an additional component between the first component and the second component An embodiment such that the first part and the second part may not be in direct contact. Also, the present invention may repeat reference numerals and/or letters in various instances. This repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.
根据本申请的实施例提供了一种封装结构。图3A是根据本申请的一个实施例的封装结构100的截面示意图。参考图3A所示,封装结构100包括线路层120。在一些实施例中,线路层120是重分布层。线路层120可以包括介电层121和内埋于介电层121内的焊盘126。线路层120还可以包括位于介电层121下方另外的介电层122、123、124。图3A中示出了线路层120总共包括四个堆叠设置的介电层121、122、123、124,但是也可以包括其他数量的介电层。介电层121是线路层120的介电层121、122、123、124中最上一层的介电层。Embodiments according to the present application provide a packaging structure. FIG. 3A is a schematic cross-sectional view of a
焊盘126的上表面126u由介电层121的顶表面121t暴露。焊盘126的上表面126u与介电层121的顶表面121t对齐,即共面。焊盘126与介电层121之间具有界面125。封装结构100还包括金属层130,金属层130设置在焊盘126与介电层121之间的界面125上方。通过在介电层121和焊盘126之间的界面125上方设置金属层130,可以避免介电层121与焊盘126之间界面125处的分层问题。由于避免了分层问题,所以焊盘126的全部侧面可均与介电层121接触以形成界面125。The
金属层130从介电层121的顶表面121t跨过界面125延伸到焊盘126的上表面126u上。这样,金属层130的下表面130b的一部分130b1接触介电层121的顶表面121t,金属层130的下表面130b的另一部分130b2接触焊盘126的上表面126u。封装结构100还包括连接焊盘126的电连接件150。电连接件150位于焊盘126和金属层130上。在一些实施例中,电连接件150可以是焊球等用以电性连接的部件。电连接件150不与介电层121接触,电连接件150通过金属层130与介电层121的顶表面121t隔开。
金属层130可以由任何适用的金属材料形成。可以和电连接件150形成共晶的材料均可用于形成金属层130。在一些实施例中,金属层130的材料可以是铜,即金属层130为铜层。在另一些实施例中,金属层130的材料可以包括镍和金,在这样的实施例中,金属层130包括由化学镍金(ENIG)制程形成的镍层和镍层上的金层。在一些实施例中,金属层130与焊盘126可以由相同的材料形成,例如金属层130和焊盘126的材料可以都是铜。在另一些实施例中,金属层130与焊盘126可以由不同的材料形成。
图3B是图3A所示的金属层130的俯视示意图。为了简明,图3B所示的俯视图对应于金属层130和焊盘126上未形成电连接件150(见图3A)时的俯视图。参考图3B所示,金属层130为环形结构。结合图3A和图3B所示,环形结构的金属层130可以具有暴露焊盘126的开口132,开口132暴露焊盘126的上表面126u的一部分。电连接件150接触金属层130及焊盘126的上表面126u由金属层130暴露的一部分。电连接件150穿过由金属层130限定的开口132连接到焊盘126,使得电连接件150位于焊盘126上方。FIG. 3B is a schematic top view of the
根据本申请的实施例,金属层130配置为降低电连接件150的位置偏移。由于金属层130突出于焊盘126的上表面126u和介电层121的顶表面121t,因此金属层130与焊盘126可以构造成边缘高中央低的碗形结构。由于金属层130与焊盘126形成了边缘高中央低的碗形结构,当将电连接件150形成在焊盘126上时,可以将电连接件150限位在金属层130和焊盘126处,因此可以解决焊盘126的上表面126u与介电层的顶表面121t齐平时的滑动风险,降低了电连接件150相对于焊盘126的位置偏移,在不增加线路层120厚度的情况下提升了制程良率、增加了结构可靠度,焊球形成良率可以高于99.9%,可靠度的检测失败率可以达到接近0%。另外,与图2所示的通过使用介电层62覆盖部分焊盘24来解决分层问题和滑动风险会影响电性效能的方式相比,本申请的实施例通过设置覆盖部分焊盘126且可导电的金属层130,可以避免对电性效能的不利影响。According to an embodiment of the present application, the
此外,线路层120的与电连接件150相对的一侧可以连接电子器件110。电子器件110可以例如是芯片等。电子器件110由模塑料115包封。电子器件110连接至由线路层120中的最下一层介电层124暴露的焊盘129。In addition, the side of the
图4是根据本申请的另一实施例的封装结构100’的截面示意图。参考图4所示,焊盘126和介电层121之间的界面125与金属层130之间可以设置有晶种层127。晶种层127的侧面可以与金属层130的对应侧面垂直对齐。Fig. 4 is a schematic cross-sectional view of a package structure 100' according to another embodiment of the present application. Referring to FIG. 4 , a
图5是根据本申请的另一实施例的封装结构200的截面示意图。在图5所示的封装结构200中,焊盘126的上表面126u包括第一上表面126u1和低于第一上表面126u1的第二上表面126u2。第一上表面126u1对应于焊盘126的边缘区域中,第二上表面126u2对应于焊盘126的中央区域。第一上表面126u1围绕第二上表面126u2。金属层230覆盖焊盘126的第一上表面126u1。金属层230暴露焊盘126的第二上表面126u2的一部分。电连接件150接触金属层230及由金属层230暴露的焊盘126的第二上表面126u2的一部分。FIG. 5 is a schematic cross-sectional view of a
金属层230从第一上表面126u1延伸到第二上表面126u2上。可以通过去除焊盘126的一部分而在焊盘126上形成凹槽,从而限定焊盘126的第一上表面126u1和第二上表面126u2。金属层230从介电层121的顶表面121t延伸跨过介电层121和焊盘126之间的界面125,再延伸经过焊盘126的第一上表面126u1,然后向下延伸到焊盘126的第二上表面126u2上。电连接件150不与介电层121接触,电连接件150通过金属层230与介电层121的顶表面121t隔开。The
图5所示的金属层230的形状可以增加金属层230与焊盘126的接触面积,可将介电层121与焊盘126扣合在一起,进一步避免介电层121与焊盘126发生分层,另外图5所示的金属层230的形状也能增加金属层230与电连接件150的接触面积,确保电连接件150的固定效果。The shape of the
图5所示的封装结构200的其他方面可以与以上参考图3A和图4所描述的类似,此处不再赘述。Other aspects of the
图6A至图6E是根据本申请的实施例形成封装结构的多个阶段的截面示意图。首先参考图6A所示,提供线路层载体610以及形成在线路层载体610上的线路层120。在本实施例中,线路层120可以包括依次形成的四个介电层121、122、123、124。在此阶段,与线路层载体610接触的介电层121中内埋有焊盘126,焊盘126由介电层121暴露且与线路层载体610接触。线路层120的与线路层载体610相对一侧的介电层124中设置有焊盘129,焊盘129由介电层124暴露。6A to 6E are schematic cross-sectional views of various stages of forming a package structure according to an embodiment of the present application. Referring first to FIG. 6A , a
参考图6B所示,例如利用SMT(Surface Mounted Technology,表面组装技术)制程将电子器件110连接在线路层120的焊盘129上。使用模塑料115模制电子器件110。可以通过研磨制程使模塑料115与电子器件110的表面齐平。然后,在模塑料115和电子器件110上方附接载体620。Referring to FIG. 6B , for example, the
参考图6C所示,去除图6B中的线路层载体610,暴露线路层120的介电层121和焊盘126。Referring to FIG. 6C , the
参考图6D所示,将图6C所示的结构倒置。此时,介电层121的顶表面121t和焊盘126的上表面126u齐平。介电层121与焊盘126之间具有界面125。接着形成设置在界面125上方的金属层130。金属层130可以类似于以上参考图3A至图3B所描述的金属层130。在一些实施例中,如参考图4所描述的,可以在形成金属层130之前形成首先晶种层127、再在晶种层127上形成金属层130。Referring to FIG. 6D, the structure shown in FIG. 6C is inverted. At this time, the
参考图6E所示,在金属层130上和焊盘126上形成焊球150。由于在界面125上方设置了金属层130,在形成焊球150时可以将电连接件150限位在焊盘126上,降低了电连接件150相对于焊盘126的位置偏移,可以解决焊盘126的上表面126u与介电层121的顶表面121t齐平时的滑动风险。在一些实施例中,在形成焊球150之后,可以去除载体620,而得到如图3A所示的封装结构100。Referring to FIG. 6E ,
在图6E中形成的焊盘126的上表面160u是平坦表面。在另一实施例中,可以在图6C所示的阶段之后,去除焊盘126的一部分而在焊盘126的上表面处形成凹槽,然后再形成延伸至凹槽中的金属层230而得到如图5所示的封装结构200。The upper surface 160u of the
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本公开的各个方面。本领域技术人员应该理解,可以很容易地使用本实用新型作为基础来设计或更改其他的处理和结构以用于达到与本实用新型所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本实用新型的精神和范围,并且在不背离本实用新型的精神和范围的情况下,可以进行多种变化、替换以及改变。The foregoing summarizes features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and/or realize the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions and changes can be made without departing from the spirit and scope of the present invention.
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