CN219304699U

CN219304699U - Spread spectrum clock generating circuit and DCDC switching power supply circuit

Info

Publication number: CN219304699U
Application number: CN202222551507.9U
Authority: CN
Inventors: 黄钧
Original assignee: Beijing Ziguang Xinneng Technology Co Ltd
Current assignee: Beijing Ziguang Xinneng Technology Co Ltd
Priority date: 2022-09-26
Filing date: 2022-09-26
Publication date: 2023-07-04
Anticipated expiration: 2032-09-26

Abstract

The application relates to the technical field of circuits and discloses a spread spectrum clock generation circuit, which comprises a pseudo-random code generation circuit and a power supply circuit, wherein the pseudo-random code generation circuit is used for generating pseudo-random codes; the pseudo-random bias current circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code; and the clock output circuit is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current. In this way, the spread spectrum clock generating circuit generates the pseudo-random clock, the pseudo-random clock is used as the clock signal of the DCDC switching power supply circuit, and the switching frequency of the DCDC switching power supply circuit can be converted from one frequency to another frequency in a pseudo-random mode, so that the energy output by the DCDC switching power supply circuit is spread into a frequency range, and the energy output by the DCDC switching power supply circuit is dispersed so as to reduce the electromagnetic interference of the DCDC switching power supply circuit. The application also discloses a DCDC switching power supply circuit.

Description

Spread spectrum clock generating circuit and DCDC switching power supply circuit

Technical Field

The present application relates to the field of circuit technology, for example, to a spread spectrum clock generating circuit and a DCDC switching power supply circuit.

Background

At present, a DCDC (Direct Current Direct Current, direct current) switching power supply circuit has the advantages of small size, high efficiency and high current. DCDC switching power supply circuits are therefore widely used in power supply systems to provide stable dc power to the circuitry. However, DCDC switching power supply circuits have a disadvantage in that electromagnetic interference (EMI) is generated at the switching frequency. Wherein electromagnetic interference includes conducted interference or radiated interference. In the case where the DCDC switching power supply circuit and the peripheral circuit are in the same power supply, the DCDC switching power supply circuit and the peripheral circuit thereof may be damaged by electromagnetic interference, thereby causing degradation or even failure of the circuit.

Most DCDC switching power supply circuits exhibit frequency dependent ripple, with lower switching frequencies providing more ripple and higher switching frequencies providing less ripple. Thus, if the clock of the DCDC switching power supply circuit is frequency modulated, the ripple of the DCDC switching power supply circuit will exhibit amplitude modulation. In the related art, the clock signal of the DCDC switching power supply circuit is generally a periodic signal, for example: sine waves or triangular waves. However, using a periodic signal as a clock signal, the DCDC switching power supply circuit will exhibit periodic ripple modulation such that the energy output by the DCDC switching power supply circuit is concentrated at a frequency at which the energy peaks. The DCDC switching power supply circuit is thus very strongly electromagnetically disturbed. Therefore, how to provide a reasonable clock signal for the DCDC switching power supply circuit so as to reduce electromagnetic interference of the DCDC switching power supply circuit is needed to be solved.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a spread spectrum clock generation circuit and a DCDC switching power supply circuit, so as to reduce electromagnetic interference of the DCDC switching power supply circuit.

In some embodiments, the spread spectrum clock generating circuit comprises: a pseudo-random code generating circuit for generating a pseudo-random code; the pseudo-random bias current circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code; and the clock output circuit is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current.

In some embodiments, the pseudo-random code generating circuit comprises: the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the first nor gate, the second nor gate, the exclusive-or gate, the first nand gate and the second nand gate; the power supply end of the first trigger, the power supply end of the second trigger, the power supply end of the third trigger, the power supply end of the fourth trigger, the power supply end of the fifth trigger and the power supply end of the sixth trigger are connected with each other; the power supply grounding end of the first trigger, the power supply grounding end of the second trigger, the power supply grounding end of the third trigger, the power supply grounding end of the fourth trigger, the power supply grounding end of the fifth trigger and the power supply grounding end of the sixth trigger are connected with each other; the D end of the first trigger is connected with the output end of the first NOR gate, and the Q end of the first trigger is connected with the D end of the second trigger and the first pseudo-random code output port; the Q end of the second trigger is connected with the D end of the third trigger and the second pseudo-random code output port; the Q end of the third trigger is connected with the D end of the fourth trigger and the third pseudo-random code output port; the Q end of the fourth trigger is connected with the D end of the fifth trigger and the fourth pseudo-random code output port; the Q end of the fifth trigger is connected with the D end of the sixth trigger and the first input end of the exclusive-OR gate; the Q end of the sixth trigger is connected with the second input end of the exclusive-OR gate; the output end of the exclusive-OR gate is connected with the first input end of the first NOR gate; the second input end of the first NOR gate is connected with the output end of the second NOR gate; the first input end of the second NOR gate is connected with the output end of the first NAND gate, and the second input end of the second NOR gate is connected with the output end of the second NAND gate; the first input end of the first NAND gate is connected with the first pseudo-random code output port; the first pseudo-random code output port is connected with the pseudo-random bias current circuit, and the second input end of the first NAND gate is connected with the second pseudo-random code output port; the second pseudo-random code output port is connected with the pseudo-random bias current circuit, and the third input end of the first NAND gate is connected with the third pseudo-random code output port; the third pseudo-random code output port is connected with a pseudo-random bias current circuit; the first input end of the second NAND gate is connected with a fourth pseudo-random code output port; the fourth pseudo-random code output port is connected with a pseudo-random bias current circuit; the second input end of the second NAND gate is connected with the Q end of the fifth trigger and the D end of the sixth trigger, and the third input end of the second NAND gate is connected with the Q end of the sixth trigger.

In some embodiments, the pseudo random bias current circuit includes: the pseudo-random current generation circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code; a current selection circuit connecting the pseudo-random current generation circuit and the clock output circuit; the current selection circuit receives a spread spectrum enabling signal and is used for outputting fixed current or pseudo random current to the clock output circuit according to the spread spectrum enabling signal.

In some embodiments, the pseudo-random current generating circuit comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube; the grid electrode of the first PMOS tube is connected with the spread spectrum frequency modulation enabling port, the source electrode of the first PMOS tube is connected with the first bias current port, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the second NMOS tube is connected with the grid electrode of the twelfth NMOS tube and the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the thirteenth NMOS tube and the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is connected with the ground, the source electrode of the thirteenth NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the tenth NMOS tube and the source electrode of the twelfth NMOS tube; the grid electrode of the thirteenth NMOS tube is connected with the spread spectrum frequency modulation enabling port; the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the grid electrode of the eleventh NMOS tube; the drain electrode of the third NMOS tube is connected with a current output port; the grid electrode of the second PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the second PMOS tube is connected with the current output port, and the drain electrode of the second PMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the third PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the third PMOS tube is connected with the current output port, and the drain electrode of the third PMOS tube is connected with the drain electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube; the grid electrode of the eighth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the fourth PMOS tube is connected with the current output port, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the grid electrode of the ninth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the ninth NMOS tube is connected with the drain electrode of the tenth NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the fifth PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the fifth PMOS tube is connected with the current output port, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the drain electrode of the twelfth NMOS tube; the current output port is connected with the current selection circuit.

In some embodiments, the current selection circuit includes: a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and an inverter; the grid electrode of the fourteenth NMOS tube is connected with the spread spectrum frequency modulation enabling port, the drain electrode of the fourteenth NMOS tube is connected with the pseudo-random current generating circuit and the source electrode of the sixth PMOS tube, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube, the source electrode of the fifteenth NMOS tube, the drain electrode of the eighth PMOS tube and the grid electrode of the eighth PMOS tube; the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifteenth NMOS tube and the output port of the inverter; an input port of the inverter is connected with a spread spectrum frequency modulation enabling port; the drain electrode of the fifteenth NMOS tube is connected with the second bias current port and the source electrode of the seventh PMOS tube; the grid electrode of the seventh PMOS tube is connected with a spread spectrum frequency modulation enabling port; the source electrode of the eighth PMOS tube is connected with the source electrode of the ninth PMOS tube; the grid electrode of the ninth PMOS tube is connected with the grid electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the pseudo-random bias current port; the pseudo-random bias current port is connected with the clock output circuit.

In some embodiments, the clock output circuit comprises: the capacitor charge-discharge circuit is connected with the pseudo-random bias current circuit, the comparator and the reset logic circuit; the capacitor charge-discharge circuit is used for providing a first comparison voltage for the comparator according to the pseudo-random current; the capacitor charge-discharge circuit is used for providing a second comparison voltage for the comparator according to the switch signal provided by the reset logic circuit; the comparator is connected with the reset logic circuit and is used for outputting a pseudo-random clock according to the first comparison voltage and the second comparison voltage and providing the pseudo-random clock for the reset logic circuit; and the reset logic circuit is used for providing a switching signal for the capacitor charging and discharging circuit according to the pseudo-random clock.

In some embodiments, the capacitive charge-discharge circuit comprises: a first resistor, a first capacitor and a switch; one end of the first resistor is grounded, and the other end of the first resistor is connected with the pseudo-random bias current circuit and the first input port of the comparator; one end of the first capacitor is connected with the second input port of the comparator and one end of the switch, and is connected with the third bias current port; the other end of the first capacitor is connected with the ground and the other end of the switch; the switch is used for switching on and off according to a switch signal of the reset logic circuit.

In some embodiments, the DCDC switching power supply circuit includes the spread spectrum clock generating circuit described above.

In some embodiments, the DCDC switching power supply circuit includes: a DCDC voltage stabilizer circuit connected with the spread spectrum clock generating circuit; and the spread spectrum clock generating circuit is used for generating a pseudo random clock as a clock signal of the DCDC voltage stabilizer circuit.

In some embodiments, the DCDC switching power supply circuit further comprises: the second capacitor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the inductor; one end of the inductor is connected with the DCDC voltage stabilizer circuit, and the other end of the inductor is connected with one end of the second capacitor, one end of the third resistor, one end of the fourth resistor and the output voltage port; the other end of the second capacitor is connected with one end of the second resistor; the other end of the second resistor and the other end of the third resistor are grounded; the other end of the fourth resistor is connected with one end of the fifth resistor and the DCDC voltage stabilizer circuit; the other end of the fifth resistor is grounded.

The spread spectrum clock generation circuit and the DCDC switching power supply circuit provided by the embodiment of the disclosure can realize the following technical effects: and the pseudo random code generation circuit is used for generating pseudo random codes. And the pseudo-random bias current circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code. And the clock output circuit is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current. In this way, the spread spectrum clock generating circuit generates the pseudo-random clock, the pseudo-random clock is used as the clock signal of the DCDC switching power supply circuit, and the switching frequency of the DCDC switching power supply circuit can be converted from one frequency to another frequency in a pseudo-random mode, so that the energy output by the DCDC switching power supply circuit is spread into a frequency range, and the energy output by the DCDC switching power supply circuit is dispersed so as to reduce the electromagnetic interference of the DCDC switching power supply circuit.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a spread spectrum clock generating circuit provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a pseudo-random code generating circuit according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram of a pseudo-random code provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pseudo-random current generating circuit provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a current selection circuit provided in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a clock output circuit provided in an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a DCDC switching power supply circuit according to an embodiment of the present disclosure.

Reference numerals:

1: a pseudo-random code generation circuit; 2: a pseudo-random bias current circuit; 3: a clock output circuit; 4: a first trigger; 5: a second trigger; 6: a third trigger; 7: a fourth trigger; 8: a fifth trigger; 9: a sixth trigger; 10: a first nor gate; 11: a second nor gate; 12: an exclusive or gate; 13: a first NAND gate; 14: a second NAND gate; 15: a first pseudo-random code output port; 16: a second pseudo-random code output port; 17: a third pseudo-random code output port; 18: a fourth pseudo-random code output port; 19: a fifth pseudo-random code output port; 20: a sixth pseudo-random code output port; 21: a first PMOS tube; 22: a second PMOS tube; 23: a third PMOS tube; 24: a fourth PMOS tube; 25: a fifth PMOS tube; 26: a first NMOS tube; 27: a second NMOS tube; 28: a third NMOS tube; 29: a fourth NMOS tube; 30: a fifth NMOS tube; 31: a sixth NMOS tube; 32: a seventh NMOS tube; 33: an eighth NMOS tube; 34: a ninth NMOS transistor; 35: a tenth NMOS tube; 36: an eleventh NMOS transistor; 37: a twelfth NMOS transistor; 38: a thirteenth NMOS transistor; 39: a spread spectrum frequency modulation enabling port; 40: a first bias current port; 41: a current output port; 42: a sixth PMOS tube; 43: a seventh PMOS transistor; 44: an eighth PMOS tube; 45: a ninth PMOS transistor; 46: a fourteenth NMOS transistor; 47: a fifteenth NMOS transistor; 48: an inverter; 49: a second bias current port; 50: a pseudo-random bias current port; 51: a comparator; 52: resetting the logic circuit; 53: a first resistor; 54: a first capacitor; 55: a switch; 56: a third bias current port; 57: a bias voltage generating circuit; 58: a control circuit; 59: a peak current comparator; 60: a transconductance amplifier; 61: a reference voltage generating circuit; 62: a gate driving circuit; 63: a zero-crossing current comparator; 64: a spread spectrum clock generating circuit; 65: a second capacitor; 66: a second resistor; 67: a third resistor; 68: a fourth resistor; 69: a fifth resistor; 70: an inductance; 71: a third capacitor; 72: a sixth resistor; 73: the DCDC circuit enables the control port; 74: a working mode selection port; 75: an input voltage port; 76: a tenth PMOS tube; 77: a sixteenth NMOS transistor; 78: a current source; 79: an external port; 80: a voltage feedback port; 81: a ground port; 82: an output voltage port.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are used primarily to better describe embodiments of the present disclosure and embodiments thereof and are not intended to limit the indicated device, element, or component to a particular orientation or to be constructed and operated in a particular orientation. Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the embodiments of the present disclosure will be understood by those of ordinary skill in the art in view of the specific circumstances.

In addition, the terms "disposed," "connected," "secured" and "affixed" are to be construed broadly. For example, "connected" may be in a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

As shown in conjunction with fig. 1, an embodiment of the present disclosure provides a spread spectrum clock generating circuit including a pseudo random code generating circuit 1, a pseudo random bias current circuit 2, and a clock output circuit 3. A pseudo-random code generating circuit 1 for generating a pseudo-random code. And the pseudo-random bias current circuit 2 is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code. And the clock output circuit 3 is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current.

The spread spectrum clock generating circuit provided by the embodiment of the disclosure is used for generating pseudo-random codes through the pseudo-random code generating circuit. And the pseudo-random bias current circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code. And the clock output circuit is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current. In this way, the spread spectrum clock generating circuit generates the pseudo-random clock, the pseudo-random clock is used as the clock signal of the DCDC switching power supply circuit, and the switching frequency of the DCDC switching power supply circuit can be converted from one frequency to another frequency in a pseudo-random mode, so that the energy output by the DCDC switching power supply circuit is spread into a frequency range, and the energy output by the DCDC switching power supply circuit is dispersed so as to reduce the electromagnetic interference of the DCDC switching power supply circuit.

Further, as shown in conjunction with fig. 2, the pseudo random code generating circuit includes: a first flip-flop 4, a second flip-flop 5, a third flip-flop 6, a fourth flip-flop 7, a fifth flip-flop 8, a sixth flip-flop 9, a first nor gate 10, a second nor gate 11, an exclusive-or gate 12, a first nand gate 13, and a second nand gate 14; the power supply end (VDD) of the first trigger 4, the power supply end of the second trigger 5, the power supply end of the third trigger 6, the power supply end of the fourth trigger 7, the power supply end of the fifth trigger 8 and the power supply end of the sixth trigger 9 are connected with each other; the power supply Ground (GND) of the first trigger 4, the power supply ground of the second trigger 5, the power supply ground of the third trigger 6, the power supply ground of the fourth trigger 7, the power supply ground of the fifth trigger 8 and the power supply ground of the sixth trigger 9 are connected to each other; the D end of the first trigger 4 is connected with the output end of the first NOR gate 10, and the Q end of the first trigger 4 is connected with the D end of the second trigger 5 and the first pseudo-random code output port 15; the Q end of the second trigger 5 is connected with the D end of the third trigger 6 and the second pseudo-random code output port 16; the Q end of the third trigger 6 is connected with the D end of the fourth trigger 7 and the third pseudo-random code output port 17; the Q end of the fourth trigger 7 is connected with the D end of the fifth trigger 8 and the fourth pseudo-random code output port 18; the Q end of the fifth trigger 8 is connected with the D end of the sixth trigger 9 and the first input end of the exclusive-OR gate 12; the Q end of the sixth trigger 9 is connected with the second input end of the exclusive-OR gate 12; the output end of the exclusive-or gate 12 is connected with the first input end of the first nor gate 10; the second input end of the first NOR gate 10 is connected with the output end of the second NOR gate 11; the first input end of the second nor gate 11 is connected with the output end of the first nor gate 13, and the second input end of the second nor gate 11 is connected with the output end of the second nor gate 14; a first input end of the first NAND gate 13 is connected with a first pseudo-random code output port 15; the first pseudo-random code output port 15 is connected with a pseudo-random bias current circuit, and the second input end of the first NAND gate 13 is connected with the second pseudo-random code output port 16; the second pseudo-random code output port 16 is connected with a pseudo-random bias current circuit, and the third input end of the first NAND gate 13 is connected with the third pseudo-random code output port 17; the third pseudo-random code output port 17 is connected with a pseudo-random bias current circuit; a first input of the second nand gate 14 is connected to a fourth pseudorandom code output port 18; the fourth pseudo-random code output port 18 is connected with a pseudo-random bias current circuit; a second input of the second nand gate 14 is connected to a fifth pseudorandom code output port 19 and a third input of the second nand gate 14 is connected to a sixth pseudorandom code output port 20. The power supply end of the first trigger 4 is also connected with a power supply, and the power ground end of the first trigger 4 is also connected with ground. The intersection point of the connection lines of the Q end of the fifth flip-flop 8, the D end of the sixth flip-flop 9 and the first input end of the exclusive-or gate 12 is taken as a fifth pseudo-random code output port 19. An intersection of the connection line of the Q terminal of the sixth flip-flop 9 and the second input terminal of the xor gate 12 is taken as a sixth pseudo random code output port 20. The C <1> port of the first flip-flop 4, the C <1> port of the second flip-flop 5, the C <1> port of the third flip-flop 6, the C <1> port of the fourth flip-flop 7, the C <1> port of the fifth flip-flop 8, and the C <1> port of the sixth flip-flop 9 are all configured to receive a preset clock signal CLK. The C <0> port of the first flip-flop 4, the C <0> port of the second flip-flop 5, the C <0> port of the third flip-flop 6, the C <0> port of the fourth flip-flop 7, the C <0> port of the fifth flip-flop 8, and the C <0> port of the sixth flip-flop 9 are all for receiving the inverted signal CLKB of the preset clock signal. The QN ports of each flip-flop are not connected to other ports. The first pseudo-random code output port 15 outputs a first pseudo-random code. The second pseudo-random code output port 16 outputs a second pseudo-random code. The third pseudo-random code output port 17 outputs a third pseudo-random code. The fourth pseudo-random code output port 18 outputs a fourth pseudo-random code. The fifth pseudo-random code output port 19 outputs a fifth pseudo-random code, and the sixth pseudo-random code output port 20 outputs a sixth pseudo-random code. In some embodiments, a timing diagram of each of the pseudo random codes generated by the pseudo random code generating circuit described above is shown in fig. 3. In fig. 3, the abscissa is time, the abscissa is in milliseconds, the ordinate is voltage, and the ordinate is volt. For example: the sixth pseudorandom code is at 0.5 milliseconds at 0 volts.

Optionally, the pseudo random bias current circuit comprises: the pseudo-random current generation circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code; a current selection circuit connected with the pseudo-random current generation circuit and the clock output circuit; the current selection circuit receives the spread spectrum enabling signal and is used for outputting fixed current or pseudo random current to the clock output circuit according to the spread spectrum enabling signal. In some embodiments, the current selection circuit is coupled to a spread spectrum frequency modulation enable port, the spread spectrum frequency modulation enable port providing a spread spectrum enable signal.

Further, as shown in fig. 4, the pseudo-random current generating circuit includes: a first PMOS (positive channel Metal Oxide Semiconductor, P-type Metal Oxide Semiconductor field effect transistor) 21, a second PMOS 22, a third PMOS 23, a fourth PMOS 24, a fifth PMOS 25, a first NMOS (N-Metal-Oxide-Semiconductor) 26, a second NMOS 27, a third NMOS 28, a fourth NMOS 29, a fifth NMOS 30, a sixth NMOS 31, a seventh NMOS 32, an eighth NMOS 33, a ninth NMOS 34, a tenth NMOS 35, an eleventh NMOS 36, a twelfth NMOS 37, a thirteenth NMOS 38. The grid electrode of the first PMOS tube 21 is connected with the spread spectrum frequency modulation enabling port 39, and the source electrode of the first PMOS tube 21 is connected with the first bias current end A port 40, the drain of the first PMOS tube 21 is connected with the drain of the second NMOS tube 27; the grid electrode of the second NMOS tube 27 is connected with the grid electrode of the eleventh NMOS tube 36, and the source electrode of the second NMOS tube 27 is connected with the grid electrode of the twelfth NMOS tube 37 and the drain electrode of the first NMOS tube 26; the grid electrode of the first NMOS tube 26 is connected with the grid electrode of the twelfth NMOS tube 37, the grid electrode of the fourth NMOS tube 29, the drain electrode of the thirteenth NMOS tube 38 and the drain electrode of the first NMOS tube 26, and the source electrode of the first NMOS tube 26 is connected with the ground, the source electrode of the thirteenth NMOS tube 38, the source electrode of the fourth NMOS tube 29, the source electrode of the sixth NMOS tube 31, the source electrode of the eighth NMOS tube 33, the source electrode of the tenth NMOS tube 35 and the source electrode of the twelfth NMOS tube 37; the gate of thirteenth NMOS transistor 38 is connected to spread spectrum frequency modulation enable port 39; the drain electrode of the fourth NMOS tube 29 is connected with the source electrode of the third NMOS tube 28; the gate of the third NMOS tube 28 is connected to the gate of the eleventh NMOS tube 36; the drain electrode of the third NMOS tube 28 is connected with a current output port 41; the grid electrode of the second PMOS tube 22 is connected with the pseudo-random code generating circuit, the source electrode of the second PMOS tube 22 is connected with the current output port 41, and the drain electrode of the second PMOS tube 22 is connected with the drain electrode of the fifth NMOS tube 30; the grid electrode of the fifth NMOS tube 30 is connected with the grid electrode of the eleventh NMOS tube 36, and the source electrode of the fifth NMOS tube 30 is connected with the drain electrode of the sixth NMOS tube 31; the grid electrode of the sixth NMOS tube 31 is connected with the grid electrode of the twelfth NMOS tube 37; the grid electrode of the third PMOS tube 23 is connected with the pseudo-random code generating circuit, the source electrode of the third PMOS tube 23 is connected with the current output port 41, and the drain electrode of the third PMOS tube 23 is connected with the drain electrode of the seventh NMOS tube 32; the grid electrode of the seventh NMOS tube 32 is connected with the grid electrode of the eleventh NMOS tube 36, and the source electrode of the seventh NMOS tube 32 is connected with the drain electrode of the eighth NMOS tube 33; the grid electrode of the eighth NMOS tube 33 is connected with the grid electrode of the twelfth NMOS tube 37; the grid electrode of the fourth PMOS tube 24 is connected with the pseudo-random code generating circuit, the source electrode of the fourth PMOS tube 24 is connected with the current output port 41, and the drain electrode of the fourth PMOS tube 24 is connected with the drain electrode of the ninth NMOS tube 34; the grid electrode of the ninth NMOS tube 34 is connected with the grid electrode of the eleventh NMOS tube 36, and the source electrode of the ninth NMOS tube 34 is connected with the drain electrode of the tenth NMOS tube 35; the grid electrode of the tenth NMOS tube 35 is connected with the grid electrode of the twelfth NMOS tube 37; the grid electrode of the fifth PMOS tube 25 is connected with the pseudo-random code generating circuit, the source electrode of the fifth PMOS tube 25 is connected with the current output port 41, and the drain electrode of the fifth PMOS tube 25 is connected with the drain electrode of the eleventh NMOS tube 36; the source electrode of the eleventh NMOS tube 36 is connected with the twelfth NMOS tube A drain electrode of 37; the current output port 41 is connected to a current selection circuit. Wherein, the grid electrode of the second PMOS tube 22 is connected with the first pseudo-random code output port 15 of the pseudo-random code generating circuit; the grid electrode of the third PMOS tube 23 is connected with the second pseudo-random code output port 16 of the pseudo-random code generating circuit; the grid electrode of the fourth PMOS tube 24 is connected with the third pseudo-random code output port 17 of the pseudo-random code generation circuit; the grid electrode of the fifth PMOS tube 25 is connected with the fourth pseudo-random code output port 18 of the pseudo-random code generating circuit. The first bias current port is for providing a first bias current. The first bias current port is connected with a first bias current generating circuit, and the first bias current generating circuit outputs a first bias current through the first bias current port. Thus, a current mirror formed by the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube is mirrored to the I0 branch, and the I0 branch is in a normally-on state. The first pseudo-random code controls the on-off state of the second PMOS tube, so as to control the on-off state of the I1 branch. The second pseudo-random code controls the on-off state of the third PMOS tube, so as to control the on-off state of the I2 branch. The third pseudo-random code controls the on or off state of the fourth PMOS tube, thereby controlling the on and off of the I3 branch. And the fourth pseudo-random code controls the on-off state of the fifth PMOS tube, thereby controlling the on-off state of the I4 branch circuit. When the first pseudo-random code is at a high level, the second PMOS tube is conducted, and the I1 branch circuit has current. When the first pseudo-random code is at a low level, the second PMOS tube is turned off, and the I1 branch does not have current. When the second pseudo-random code is at a high level, the third PMOS tube is conducted, and the I2 branch circuit has current. When the second pseudo-random code is at a low level, the third PMOS tube is turned off, and the I2 branch has no current. When the third pseudo-random code is at a high level, the fourth PMOS tube is conducted, and the I3 branch circuit has current. When the third pseudo-random code is at a low level, the fourth PMOS tube is turned off, and the I3 branch circuit has no current. When the fourth pseudo-random code is at a high level, the fifth PMOS tube is conducted, and the I4 branch circuit has current. When the fourth pseudo-random code is at a low level, the fifth PMOS tube is turned off, and the I4 branch has no current. Taking the current value of the I0 branch as I _I0 The current value of the I1 branch is taken as I _I1 The current value of the I2 branch is taken as I _I2 The current value of the I3 branch is taken as I _I3 Current value of I4 branchAs I _I4 . The PMOS tube is controlled according to the first pseudo-random code, the second pseudo-random code, the third pseudo-random code and the fourth pseudo-random code, so that the current value output by the current output port is I _I0 、I _I0 +I _I1 、I _I0 +I _I1 +I _I2 、I _I0 +I _I1 +I _I2 +I _I3 And I _I0 +I _I1 +I _I2 +I _I3 +I _I4 And switched between, thereby forming a pseudo-random current.

Further, as shown in fig. 5, the current selection circuit includes: a sixth PMOS transistor 42, a seventh PMOS transistor 43, an eighth PMOS transistor 44, a ninth PMOS transistor 45, a fourteenth NMOS transistor 46, a fifteenth NMOS transistor 47, and an inverter 48. The grid electrode of the fourteenth NMOS tube 46 is connected with the spread spectrum frequency modulation enabling port 39, the drain electrode of the fourteenth NMOS tube 46 is connected with the pseudo-random current generating circuit and the source electrode of the sixth PMOS tube 42, and the source electrode of the fourteenth NMOS tube 46 is connected with the drain electrode of the sixth PMOS tube 42, the drain electrode of the seventh PMOS tube 43, the source electrode of the fifteenth NMOS tube 47, the drain electrode of the eighth PMOS tube 44 and the grid electrode of the eighth PMOS tube 44; the grid electrode of the sixth PMOS tube 42 is connected with the grid electrode of the fifteenth NMOS tube 47 and the output port of the inverter 48; an input port of the inverter 48 is connected to the spread spectrum frequency modulation enable port 39; the drain electrode of the fifteenth NMOS tube 47 is connected with the second bias current port 49 and the source electrode of the seventh PMOS tube 43; the gate of the seventh PMOS transistor 43 is connected to the spread spectrum frequency modulation enable port 39; the source electrode of the eighth PMOS tube 44 is connected with the source electrode of the ninth PMOS tube 45; the grid electrode of the ninth PMOS tube 45 is connected with the grid electrode of the eighth PMOS tube 44, and the drain electrode of the ninth PMOS tube 45 is connected with the pseudo-random bias current port 50; the pseudo-random bias current port 50 is connected to a clock output circuit. The source of the eighth PMOS transistor 44 is also connected to a power supply. The second bias current port is for providing a second bias current. The second bias current port is connected with a second bias current generating circuit, and the second bias current generating circuit outputs a second bias current through the second bias current port. The drain of the fourteenth NMOS transistor 46 is connected to the current output port 41 of the pseudo-random current generating circuit. A fixed or pseudo-random current is provided to the clock output circuit through the pseudo-random bias current port. Thus, when the spread spectrum modulation function is turned off, the spread spectrum enable signal input from the spread spectrum modulation enable port is high. And the transmission gate connecting the second bias current port and the I5 branch is conducted, and the current of the I5 branch is equal to the current output by the second bias current port. The current of the I5 branch is mirrored to the drain electrode of the ninth PMOS tube through a current mirror formed by the eighth PMOS tube and the ninth PMOS tube, so that the current output by the drain electrode of the ninth PMOS tube is equal to the current output by the second bias current port. At this time, the current value output by the drain electrode of the ninth PMOS transistor is a fixed current value. When the spread spectrum modulation function is turned on, the spread spectrum enable signal input from the spread spectrum modulation enable port is low. The transmission gate connecting the current output port and the I5 branch is conducted, and the current of the I5 branch is equal to the current output by the current output port. The current of the I5 branch is mirrored to the drain electrode of the ninth PMOS tube through a current mirror formed by the eighth PMOS tube and the ninth PMOS tube, so that the current output by the drain electrode of the ninth PMOS tube is equal to the current output by the current output port. At this time, the current value output by the drain electrode of the ninth PMOS transistor is a pseudo-random current value.

Optionally, the clock output circuit includes: the capacitor charge-discharge circuit is connected with the pseudo-random bias current circuit, the comparator and the reset logic circuit; the capacitor charge-discharge circuit is used for providing a first comparison voltage for the comparator according to the pseudo-random current; the capacitor charge-discharge circuit is used for providing a second comparison voltage for the comparator according to the switching signal provided by the reset logic circuit; the comparator is connected with the reset logic circuit, and is used for outputting a pseudo-random clock according to the first comparison voltage and the second comparison voltage and providing the pseudo-random clock for the reset logic circuit; and the reset logic circuit is used for providing a switching signal for the capacitor charging and discharging circuit according to the pseudo-random clock.

Further, as shown in fig. 6, the capacitor charging and discharging circuit includes: a first resistor 53, a first capacitor 54 and a switch 55. One end of the first resistor 53 is grounded, and the other end of the first resistor 53 is connected with the pseudo-random bias current circuit and the first input port of the comparator 51; one end of the first capacitor 54 is connected to the second input port of the comparator 51, one end of the switch 55 and the third bias current port 56; the other end of the first capacitor 54 is connected to ground and the other end of the switch 55; the switch 55 is used for switching on and off according to a switching signal of the reset logic circuit 52. Wherein the other end of the first resistor 53 is connected to the pseudo-random bias current port 50 of the pseudo-random bias current circuit. The third bias current port is for providing a third bias current. The third bias current port is connected with a third bias current generating circuit, and the third bias current generating circuit outputs a third bias current through the third bias current port. The first input port of the comparator is a negative input end of the comparator, and the second input port of the comparator is a positive input end of the comparator. Thus, the current flowing from the drain of the ninth NMOS transistor, i.e., the current flowing from the pseudo-random bias current port, will generate the voltage V2 on the first resistor, and V2 is used as the second comparison voltage of the comparator. The bias current generated by the third bias current port charges the first capacitor, so that the voltage V1 of the first capacitor is continuously changed, and V1 is used as the first comparison voltage of the comparator. In the case where the voltage V2 is equal to the voltage V1, the output terminal of the comparator outputs a high level. The high level of the output end of the comparator is provided for the reset logic circuit, the reset logic circuit controls the switch to be conducted, the capacitor is discharged at the moment, and the voltage V1 is continuously reduced. In the case where the voltage V1 is smaller than the voltage V2, the output terminal of the comparator outputs a low level. The low level at the output end of the comparator is provided for the reset logic circuit, the reset logic circuit controls the switch to be opened, the capacitor is charged at the moment, and the voltage V1 is continuously increased. The current flowing out of the pseudo-random bias current port is continuously changed, so that the voltage V2 is also continuously changed, and the comparison threshold value of V1 and V2 is also randomly changed, so that the clock frequency formed by the high level or the low level output by the output end of the comparator is a pseudo-random clock in the cyclic charge and discharge process of the capacitor.

The embodiment of the disclosure provides a DCDC switching power supply circuit, which comprises the spread spectrum clock generation circuit.

By adopting the DCDC switching power supply circuit provided by the embodiment of the disclosure, the pseudo-random clock is generated by the spread spectrum clock generating circuit. The pseudo-random clock is used as a clock signal of the DCDC switching power supply circuit, and the switching frequency of the DCDC switching power supply circuit can be converted from one frequency to another frequency in a pseudo-random mode, so that the energy output by the DCDC switching power supply circuit is expanded into a frequency range, and the energy output by the DCDC switching power supply circuit is dispersed, so that the electromagnetic interference of the DCDC switching power supply circuit is reduced.

Optionally, the DCDC switching power supply circuit includes: a DCDC voltage stabilizer circuit connected with the spread spectrum clock generating circuit; and the spread spectrum clock generating circuit is used for generating a pseudo random clock as a clock signal of the DCDC voltage stabilizer circuit.

Optionally, the DCDC switching power supply circuit further comprises: the second capacitor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the inductor; one end of the inductor is connected with the DCDC voltage stabilizer circuit, and the other end of the inductor is connected with one end of the second capacitor, one end of the third resistor, one end of the fourth resistor and the output voltage port; the other end of the second capacitor is connected with one end of the second resistor; the other end of the second resistor and the other end of the third resistor are grounded; the other end of the fourth resistor is connected with one end of the fifth resistor and the DCDC voltage stabilizer circuit; the other end of the fifth resistor is grounded. One end of the inductor is connected with the drain electrode of a tenth PMOS tube of the DCDC voltage stabilizer circuit through an external port. The other end of the fourth resistor is connected with a second input port of the transconductance amplifier of the DCDC voltage stabilizer circuit through a voltage feedback port.

In some embodiments, fig. 7 is a schematic diagram of a DCDC switching power supply circuit, as shown in connection with fig. 7: the control circuit 58 is connected to the DCDC circuit enable control port 73, the operation mode selection port 74, and the bias voltage generating circuit 57. The bias voltage generating circuit 57 is connected to the input voltage port 75, the first input port of the peak current comparator 59, and the source of the tenth PMOS transistor 76. The gate of the tenth PMOS transistor 76 is connected to the gate driving circuit 62, and the drain of the tenth PMOS transistor 76 is connected to the drain of the sixteenth NMOS transistor 77 and the external port 79. The gate drive circuit 62 is connected to the output port of the peak current comparator 59, the second input port of the peak current comparator 59, the spread spectrum clock generating circuit 64, the output port of the zero crossing current comparator 63, and the gate of the sixteenth NMOS transistor 77. The spread spectrum clock generating circuit 64 is connected to the spread spectrum frequency modulation enable port 39. A second input port of peak current comparator 59 is connected to an output port of transconductance amplifier 60 and to one end of sixth resistor 72. A first input port of the transconductance amplifier 60 is connected to a reference voltage generating circuit 61, and the reference voltage generating circuit 61 is grounded. A second input port of the transconductance amplifier 60 is connected to a voltage feedback port 80. The other end of the sixth resistor 72 is connected to one end of the third capacitor 71, and the other end of the third capacitor 71 is grounded. The source of the sixteenth NMOS tube 77 is connected to the input port of the current source 78, and the output port of the current source 78 is connected to the negative input port of the zero-crossing current comparator 63, the ground port 81, and the ground, and the positive input port of the zero-crossing current comparator is grounded. The external port 79 is connected to one end of the inductor 70, and the other end of the inductor 70 is connected to one end of the second capacitor 65, one end of the third resistor 67, one end of the fourth resistor 68 and the output voltage port 82; the other end of the second capacitor 65 is connected with one end of a second resistor 66; the other end of the second resistor 66 and the other end of the third resistor 67 are grounded; the other end of the fourth resistor 68 is connected to one end of the fifth resistor 69 and the voltage feedback port 80; the other end of the fifth resistor 69 is grounded. The gate driving circuit is connected with the output end of the comparator of the spread spectrum clock generating circuit. The first input port of the transconductance amplifier is an anode input port, and the second input port of the transconductance amplifier is a cathode input port. The first input port of the peak current comparator is a positive electrode port, and the second input port of the peak current comparator is a negative electrode port. The bias voltage generating circuit is used for generating bias voltage. The grid driving circuit is used for driving the switching tube tenth PMOS tube and the sixteenth NMOS tube to be turned on and off. The control circuit is used for controlling the working mode of the switching power supply. The reference voltage generation circuit is used for generating a reference voltage.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may include structural and other modifications. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A spread spectrum clock generating circuit, comprising:

a pseudo-random code generating circuit for generating a pseudo-random code;

the pseudo-random bias current circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code;

and the clock output circuit is connected with the pseudo-random bias current circuit and is used for generating a pseudo-random clock according to the pseudo-random current.

2. The spread spectrum clock generating circuit as recited in claim 1, wherein the pseudo random code generating circuit comprises: the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the first nor gate, the second nor gate, the exclusive-or gate, the first nand gate and the second nand gate; the power supply end of the first trigger, the power supply end of the second trigger, the power supply end of the third trigger, the power supply end of the fourth trigger, the power supply end of the fifth trigger and the power supply end of the sixth trigger are connected with each other; the power supply grounding end of the first trigger, the power supply grounding end of the second trigger, the power supply grounding end of the third trigger, the power supply grounding end of the fourth trigger, the power supply grounding end of the fifth trigger and the power supply grounding end of the sixth trigger are connected with each other; the D end of the first trigger is connected with the output end of the first NOR gate, and the Q end of the first trigger is connected with the D end of the second trigger and the first pseudo-random code output port; the Q end of the second trigger is connected with the D end of the third trigger and the second pseudo-random code output port; the Q end of the third trigger is connected with the D end of the fourth trigger and the third pseudo-random code output port; the Q end of the fourth trigger is connected with the D end of the fifth trigger and the fourth pseudo-random code output port; the Q end of the fifth trigger is connected with the D end of the sixth trigger and the first input end of the exclusive-OR gate; the Q end of the sixth trigger is connected with the second input end of the exclusive-OR gate; the output end of the exclusive-OR gate is connected with the first input end of the first NOR gate; the second input end of the first NOR gate is connected with the output end of the second NOR gate; the first input end of the second NOR gate is connected with the output end of the first NAND gate, and the second input end of the second NOR gate is connected with the output end of the second NAND gate; the first input end of the first NAND gate is connected with the first pseudo-random code output port; the first pseudo-random code output port is connected with the pseudo-random bias current circuit, and the second input end of the first NAND gate is connected with the second pseudo-random code output port; the second pseudo-random code output port is connected with the pseudo-random bias current circuit, and the third input end of the first NAND gate is connected with the third pseudo-random code output port; the third pseudo-random code output port is connected with a pseudo-random bias current circuit; the first input end of the second NAND gate is connected with a fourth pseudo-random code output port; the fourth pseudo-random code output port is connected with a pseudo-random bias current circuit; the second input end of the second NAND gate is connected with the Q end of the fifth trigger and the D end of the sixth trigger, and the third input end of the second NAND gate is connected with the Q end of the sixth trigger.

3. The spread spectrum clock generating circuit as recited in claim 1, wherein the pseudo random bias current circuit comprises:

the pseudo-random current generation circuit is connected with the pseudo-random code generation circuit and is used for generating pseudo-random current according to the pseudo-random code;

a current selection circuit connecting the pseudo-random current generation circuit and the clock output circuit; the current selection circuit receives a spread spectrum enabling signal and is used for outputting fixed current or pseudo random current to the clock output circuit according to the spread spectrum enabling signal.

4. A spread spectrum clock generating circuit as recited in claim 3, wherein the pseudo random current generating circuit comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube; the grid electrode of the first PMOS tube is connected with the spread spectrum frequency modulation enabling port, the source electrode of the first PMOS tube is connected with the first bias current port, and the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the second NMOS tube is connected with the grid electrode of the twelfth NMOS tube and the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the grid electrode of the fourth NMOS tube, the drain electrode of the thirteenth NMOS tube and the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is connected with the ground, the source electrode of the thirteenth NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the tenth NMOS tube and the source electrode of the twelfth NMOS tube; the grid electrode of the thirteenth NMOS tube is connected with the spread spectrum frequency modulation enabling port; the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with the grid electrode of the eleventh NMOS tube; the drain electrode of the third NMOS tube is connected with a current output port; the grid electrode of the second PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the second PMOS tube is connected with the current output port, and the drain electrode of the second PMOS tube is connected with the drain electrode of the fifth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the sixth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the third PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the third PMOS tube is connected with the current output port, and the drain electrode of the third PMOS tube is connected with the drain electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube; the grid electrode of the eighth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the fourth PMOS tube is connected with the current output port, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the grid electrode of the ninth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, and the source electrode of the ninth NMOS tube is connected with the drain electrode of the tenth NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the twelfth NMOS tube; the grid electrode of the fifth PMOS tube is connected with the pseudo-random code generating circuit, the source electrode of the fifth PMOS tube is connected with the current output port, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the eleventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the drain electrode of the twelfth NMOS tube; the current output port is connected with the current selection circuit.

5. A spread spectrum clock generating circuit as recited in claim 3, wherein the current selection circuit comprises: a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and an inverter; the grid electrode of the fourteenth NMOS tube is connected with the spread spectrum frequency modulation enabling port, the drain electrode of the fourteenth NMOS tube is connected with the pseudo-random current generating circuit and the source electrode of the sixth PMOS tube, and the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube, the source electrode of the fifteenth NMOS tube, the drain electrode of the eighth PMOS tube and the grid electrode of the eighth PMOS tube; the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifteenth NMOS tube and the output port of the inverter; an input port of the inverter is connected with a spread spectrum frequency modulation enabling port; the drain electrode of the fifteenth NMOS tube is connected with the second bias current port and the source electrode of the seventh PMOS tube; the grid electrode of the seventh PMOS tube is connected with a spread spectrum frequency modulation enabling port; the source electrode of the eighth PMOS tube is connected with the source electrode of the ninth PMOS tube; the grid electrode of the ninth PMOS tube is connected with the grid electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the pseudo-random bias current port; the pseudo-random bias current port is connected with the clock output circuit.

6. The spread spectrum clock generating circuit as recited in claim 1, wherein the clock output circuit comprises:

the capacitor charge-discharge circuit is connected with the pseudo-random bias current circuit, the comparator and the reset logic circuit; the capacitor charge-discharge circuit is used for providing a first comparison voltage for the comparator according to the pseudo-random current; the capacitor charge-discharge circuit is used for providing a second comparison voltage for the comparator according to the switch signal provided by the reset logic circuit;

the comparator is connected with the reset logic circuit and is used for outputting a pseudo-random clock according to the first comparison voltage and the second comparison voltage and providing the pseudo-random clock for the reset logic circuit;

and the reset logic circuit is used for providing a switching signal for the capacitor charging and discharging circuit according to the pseudo-random clock.

7. The spread spectrum clock generating circuit as recited in claim 6, wherein the capacitor charge-discharge circuit comprises: a first resistor, a first capacitor and a switch; one end of the first resistor is grounded, and the other end of the first resistor is connected with the pseudo-random bias current circuit and the first input port of the comparator; one end of the first capacitor is connected with the second input port of the comparator and one end of the switch, and is connected with the third bias current port; the other end of the first capacitor is connected with the ground and the other end of the switch; the switch is used for switching on and off according to a switch signal of the reset logic circuit.

8. A DCDC switching power supply circuit, comprising a spread spectrum clock generating circuit as claimed in any one of claims 1 to 7.

9. The DCDC switching power supply circuit of claim 8, wherein the DCDC switching power supply circuit comprises:

a DCDC voltage stabilizer circuit connected with the spread spectrum clock generating circuit;

and the spread spectrum clock generating circuit is used for generating a pseudo random clock as a clock signal of the DCDC voltage stabilizer circuit.

10. The DCDC switching power supply circuit of claim 9, further comprising: the second capacitor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the inductor; one end of the inductor is connected with the DCDC voltage stabilizer circuit, and the other end of the inductor is connected with one end of the second capacitor, one end of the third resistor, one end of the fourth resistor and the output voltage port; the other end of the second capacitor is connected with one end of the second resistor; the other end of the second resistor and the other end of the third resistor are grounded; the other end of the fourth resistor is connected with one end of the fifth resistor and the DCDC voltage stabilizer circuit; the other end of the fifth resistor is grounded.