CN101719762B - Spread-spectrum clock signal generator for digital current modulation - Google Patents

Abstract

The invention relates to a spread-spectrum clock signal generator for digital current modulation, which belongs to the technical field of electronics. In the invention, a digital modulation current generation circuit comprising a state machine, a switching group and micro current sources is added on the basis of a common clock signal generator, and a binary signal Di generated by the state machine is utilized to control the opening and the closing of a switch Ki; when the switch Ki is opened, current Ii generated by an ith micro current source is superposed into modulation output current IDVC; and the modulation output current IDVC and the charge/discharge bias current Imain of an oscillation capacitor C0 in the common clock signal generator are superposed together to form the charge/discharge current Isum of the oscillation capacitor C0. The invention generates a spread-spectrum clock signal by changing the magnitude of the charge/discharge current of the oscillation capacitor in the clock signal generator and avoids using a filtering component which is difficult to integrate under a precondition of achieving favorable EMI performance, thereby lowering the area of a chip; meanwhile, the invention has lower power consumption and favorable robustness.

Description

A Digital Current Modulated Spread Spectrum Clock Signal Generator

technical field

The invention belongs to the field of electronic technology, and relates to clock signal generation technology, frequency modulation technology and anti-electromagnetic interference technology, in particular to a spread spectrum clock generator realized by digital modulation current modulation.

Background technique

The continuous improvement of integration is a core development direction of microelectronics technology, and with the continuous improvement of chip integration, more and more control circuits and power processing devices are integrated in one chip, and the chip operating frequency is getting higher and higher. Make the problem of electromagnetic interference more and more serious. For this reason, the International Radio Interference Professional Committee (CISPR) International Standardization Organization established in the International Electrotechnical Commission (IEC), as well as the United States Federal Communications Commission (FCC) and other agencies with government functions, have successively formulated various electromagnetic compatibility (EMC) standards, Test methods and related laws. How to improve the anti-interference ability of highly integrated chips and at the same time reduce the interference of integrated chips to the external environment is an urgent problem to be solved.

In recent years, a variety of schemes to suppress circuit electromagnetic interference (EMI) have been proposed, such as adding coupling capacitors, slope control, reducing package inductance, spread spectrum technology, and so on. Among them, the spread spectrum technology omits the filter circuit, and the circuit structure is simple and effective, so it is widely used. By modulating the switching frequency, it disperses the energy concentrated on the switching frequency and its harmonics to the discrete sidebands around them, thereby reducing the amplitude of electromagnetic interference at each frequency point, reaching a level lower than the electromagnetic interference standard limit value.

The clock signal generator is a basic circuit commonly used in electronic technology, and its application is very extensive. In various existing integrated circuits, more and more clock signal generators are integrated together, which makes the EMI performance of the clock signal generator itself must comply with the EMC standard. Under such technical requirements, various spread spectrum clock signal generators emerged as the times require.

Traditional spread-spectrum clock signal generators are usually generated by phase-locked loop circuits. There are usually three implementations in the prior art: the first is to introduce a ΣΔ modulator into phase-locked loops (PLLs); the second is to digitize the output of a multi-phase phase-locked loop or use a delay-locked loop ) to generate the clock; the third is to directly modulate with a voltage-controlled oscillator (VCO) in the PLLs. The first two structures are more complex, the third structure is simple and has no ΣΔ noise, but when the input frequency is relatively low or the required bandwidth is relatively small, a large filter device is required in the loop filter, which will take up a lot area, making total integration difficult.

Contents of the invention

The present invention provides a spread spectrum clock signal generator with digital current modulation. The spread spectrum clock signal generator uses digital variable current modulation technology to directly change the charging/discharging current of the oscillating capacitor in the clock signal generator. The clock signal generating circuit outputs the frequency of the clock signal, thereby generating a spread spectrum clock signal. Under the premise of good EMI performance, the present invention avoids the use of difficult-to-integrate filter devices, thereby reducing the area of the chip; and adopts digital technology to generate spread spectrum clock signals, which means that the present invention has lower power consumption and Good robustness.

Technical scheme of the present invention is as follows:

A digital current modulated spread spectrum clock signal generator, as shown in Figure 1, includes a clock signal generator and a digital modulated current generating circuit. The digital modulation current generation circuit is composed of a state machine that generates M-bit binary signals, a switch group consisting of M switches, and M microcurrent sources; in the digital modulation current generation circuit, the binary signal generated by the state machine is used D _i (i=1, 2, 3, ..., M) _is used to control the opening and closing of the switch K _i (i = 1, 2, 3, ..., M) in the switch group. The _current I _i produced by the i micro-current sources is superimposed on the modulated output current I _DVC produced by the entire digital modulation current generating circuit through the switch K _i ; The bias current I _main charged and discharged by the oscillation capacitor C ₀ in the clock signal generator is superimposed together to form the charge and discharge current I _sum of the oscillation capacitor C ₀ .

若状态机产生的二进制信号D_i对开关K_i而言为低电平开启，高电平关闭，则数字化调制电流产生电路产生的调制输出电流

其中

与D_i是互补的关系。If the binary signal D _i generated by the state machine is turned on at a high level and turned off at a low level for the switch K _i , then the modulated output current generated by the digitized modulation current generating circuit

If the binary signal D _i generated by the state machine is turned on at a low level and turned off at a high level for the switch K _i , then the modulated output current generated by the digitized modulation current generating circuit

in

It is a complementary relationship with D _i .

The modulated output current I _DVC generated by the digital modulated current generation circuit is a variable current that varies discretely with the state machine output signal D ₁ D ₂ ... D _i ... D _M , and it is the same as the oscillation capacitor C ₀ in the ordinary clock signal generator The charging and discharging bias current I _main is superimposed to determine the charging and discharging current of the oscillation capacitor C ₀ . If I _sum =I _DVC +I _main is defined, then the relationship between the clock frequency generated by the entire spread spectrum clock signal generator and the charging and discharging current of the oscillation capacitor C ₀ can be expressed as f=ρ(I _sum ), when I _sum is at a certain When the range changes, the clock frequency generated by the entire spread spectrum clock signal generator also changes within a certain range, thereby realizing spread spectrum, and the peak value of the spectrum at its high harmonics is reduced, and electromagnetic interference is suppressed. In a charging and discharging cycle, the state machine output signals D ₁ D ₂ ... D _i ... D _M correspond to a fixed state, and the modulated output current I _DVC generated by the digital modulation current generating circuit is also constant. If the binary signal D _i generated by the state machine is turned on at a low level and turned off at a high level for the switch K _i as an example, then the output current I _DVC of the digital modulation current generation circuit and the waveform of the charging _and discharging voltage of the oscillating capacitor The relationship between graph changes is shown in Figure 2.

It should be noted:

1. The current I _DVC of each micro-current source in the digital modulation current generation circuit can be the same or different.

2. The current I _i of the micro-current source should be much smaller than the bias current I _main charged and discharged by the oscillating capacitor C ₀ in the ordinary clock signal generator. In practical applications, I _main should be higher than I _i by more than two orders of magnitude.

3. The number M of micro-current sources in the digital modulation current generation circuit (corresponding to the number of switches in the switch group and the number of bits of the binary signal generated by the state machine) should not be too small or too large. If the value of M is too small, the spread spectrum effect of current modulation is not very obvious, which is not enough to ensure the EMI performance of the entire spread spectrum clock signal generator; if the value of M reaches a certain value, the spread spectrum effect of current modulation will reach a certain level. Limit, if the value of M is increased, the spread spectrum effect of current modulation will not increase, but will increase the chip area and device cost of the entire spread spectrum clock signal generator. In practical applications, the value range of M should be between 3 and 10.

4. As long as the state machine can generate a series of binary values (high and low levels), the control of the switch can be realized. In the present invention, the state machine can be realized by a random signal generator, or by a regularly changing binary signal generating circuit (such as a counter), or even by software programming.

The digital current modulated spread spectrum clock signal generator provided by the present invention changes the output clock signal frequency of the clock signal generating circuit by directly changing the charging/discharging current of the oscillating capacitor in the clock signal generator, thereby generating the spread spectrum clock signal. On the premise of good EMI performance, the present invention avoids the use of difficult-to-integrate filter devices, thereby reducing the area of the chip; and adopts digital technology to generate spread-spectrum clock signals, so that the present invention has lower power consumption and good robustness.

Description of drawings

Fig. 1 is a structural schematic diagram of a digital current modulated spread spectrum clock signal generator provided by the present invention.

Figure 2 is a waveform diagram of the digitized modulation current I _DVC and the charging and discharging voltage of the oscillation capacitor C ₀ .

Fig. 3 is a schematic circuit diagram of a specific digital current modulation spread spectrum clock signal generator provided by the present invention.

Figure 4 is a comparison of the output spectrum of the clock signal generator with a digital modulation current generation circuit (spread spectrum circuit) and without a clock signal generator with a spread spectrum circuit.

Detailed ways

A specific digital current modulated spread spectrum clock signal generator, as shown in Figure 3, consists of a clock signal generator and a digital modulated current generating circuit.

The clock signal generator includes:

An oscillating capacitor C ₀ bias current I _main current source for charging and discharging: the current source is composed of five PMOS transistors MP11~MP15 and two NMOS transistors MN3~MN4 through mirroring to generate bias current I _main in a certain proportion; PMOS transistor MP11 , The source of MP12, MP13 and MP14 is connected to the power supply voltage Vcc; the drain of MP14 is connected to the drain of MN4, and the gate of MP14 is connected to the signal X1 of the external circuit; the drain of MP13 is connected to the source of MP15 The gate of the MP13 tube is connected to the gate of the MP12 tube; the drain of the MP15 tube is connected to the drain of the MP12 tube and the drain of the MN3 tube; the gate of the MP15 tube is externally connected to the protection circuit signal Y1; the MN3 tube and the MN4 tube The grid of the tube is connected and connected to the drain of the MN4 tube, the source of the MN3 tube and the MN4 tube is grounded Vss; the gates of the MP11 tube, MP12 tube and MP13 tube are interconnected and connected to the drain of the MP12 tube, and the drain of the MP11 tube is output The bias current I _main for charging and discharging the oscillation capacitor C ₀ .

When the signal X1 is low level, the current reference current IMN4 is generated, thereby generating a mirror current through MN3 in a certain proportion; when the signal Y1 is high level, MP15 is cut off, and all the current flows through MP12; when the signal Y1 is low level , MP15 is turned on, MP13 divides a large part of the current flowing through MP12, and the circuit enters the protection state. Because the gate voltages of MP12 and MP11 are the same, MP11 generates the bias current I _main for charging the capacitor through mirroring.

A PMOS differential input pair: the differential input pair is composed of a pair of PMOS transistors MP1 and MP2; the sources of MP1 and MP2 are connected to the drain of MP11.

An inverter INV1: the gate of the MP2 transistor is connected to the gate of the MP1 transistor through the inverter INV1.

A current sink: the current sink is composed of NMOS transistors MN1 and MN2; the drains of MN1 and MN2 are respectively connected to the drains of MP1 and MP2, and the gates of MN1 and MN2 are interconnected and connected to the drain of MN1 pole, and the sources of MN1 and MN2 are grounded to Vss. By adjusting the width-to-length ratio of the tubes MN1 and MN2, the magnitude of the charge and discharge current of the capacitor _C0 can be controlled, which is used to determine the ratio of the time constant of the charge and discharge of the capacitor to achieve precise control of the duty cycle of the output waveform.

A comparison circuit: the comparison circuit is composed of two comparators COM_1 and COM_2; Vref1 and Vref2 are its comparison reference voltages, which come from an external reference circuit, and both are greater than 0V; EN1 and EN2 are the enable terminals of the comparators COM_1 and COM_2 respectively , are active low; one input terminal of the comparator COM_1 and COM_2 is input to Vref1 and Vref2 respectively, and the other input terminal is interconnected; the output terminals of the comparator COM_1 and COM_2 are interconnected and connected to the input terminal of the inverter INV and Gate of MP2 tube.

One oscillating capacitor C0: one plate of the oscillating capacitor C0 is grounded to Vss, and the other plate is connected to the interconnection input terminals of the comparators COM_1 and COM_2 and the gates of the MN1 and MN2 tubes.

The digital modulation current generating circuit includes: a state machine for generating 4-bit binary signals, a switch group consisting of 4 switches and 4 micro-current sources.

The four micro-current sources are composed of four PMOS tubes MP7-MP10; the sources of MP7 tubes, MP8 tubes, MP9 tubes and MP10 tubes are connected to the power supply voltage Vcc; the gates of MP7 tubes, MP8 tubes, MP9 tubes and MP10 tubes The gates of MP11, MP12 and MP13 are interconnected and connected; the drains of MP7, MP8, MP9 and MP10 respectively output currents I ₁ , I ₂ , I ₃ and I ₄ . The current sources I ₁ , I ₂ , I ₃ and I ₄ are obtained by mirroring the reference current.

The switch group formed by the four switches is composed of four PMOS tubes MP3-MP6; the source of MP3 tube is connected to the drain of MP7 tube, the source of MP4 tube is connected to the drain of MP8 tube, and the source of MP5 tube is connected to MP9 The drain of the tube, the source of the MP6 tube is connected to the drain of the MP10 tube; the drains of the MP3 tube, MP4 tube, MP5 tube and MP6 tube are interconnected and connected to the sources of the MP1 tube and the MP2 tube.

The state machine for generating 4-bit binary signals is a 4-bit counter whose output signals D ₁ , D ₂ , D ₃ and D ₄ are respectively connected to the gates of MP3, MP4, MP5 and MP6. The output terminals of the comparators COM_1 and COM_2 are connected to the clock input terminals of the 4-bit counter through the inverter INV2, and the constant signal output of the spread spectrum clock signal generator that utilizes the entire digitized current modulation provides the clock input signal for the counter, which is beneficial to reduce The cost of the spread spectrum clock signal generator for the entire digitization current modulation.

The working principle of the spread spectrum clock signal generator for digitized current modulation is as follows:

In an ordinary clock signal generator, Vref1 and Vref2 come from an external circuit reference circuit to provide a reference voltage for this circuit, which is composed of a two-stage comparator and a differential pair.

The differential pair consists of MP1, MP2, MN1, and MN2, and IN1 and IN2 are two opposite signals. When IN1 is at low level, MP1 is turned on, MP2, MN1, and MN2 are all turned off, and the capacitor is charged; when IN1 is at high level, MP2 is turned on, MN1 and MN2 are also turned on, MP1 is turned off, and the capacitor is discharged.

When the capacitor is charged, IN1 is at low level and IN2 is at high level. At this time, the comparator COM_1 works, and the comparator COM_2 is cut off. When the output voltage VCO of the differential pair is less than Vref1, IN1 is at low level and IN2 is at high level, until the output voltage VCO of the differential pair is greater than Vref1, IN1 becomes high level, IN2 becomes low level, and the capacitor stops charging. Start discharging. When the capacitor is discharged, IN1 is at a high level and IN2 is at a low level, at this time the comparator COM_1 is cut off, and the comparator COM_2 is working. When the output voltage VCO of the differential pair is greater than Vref2, IN1 is at high level and IN2 is at low level, until the output voltage VCO of the differential pair is less than Vref2, IN1 becomes low level, IN2 becomes high level, and the capacitor stops discharging. Start charging.

The clock signal generator repeats the charging and discharging work in this way, so as to output a relatively constant oscillation signal (clock signal). During the working period of the clock signal generator, the states of D ₁ , D ₂ , D ₃ and D ₄ will change with the output state of the state machine. When D ₁ , D ₂ , D ₃ and D ₄ are all at low level, the four branches controlled by them are all turned on, the charging and discharging current is the largest, and the clock frequency generated by the clock signal generator is the highest; when D ₁ , D ₂ , D ₃ and D ₄ are all at high level, the M branches controlled by them are all turned off, the charging and discharging current is the smallest, and the clock frequency generated by the clock signal generator is the lowest; when D ₁ , D ₂ , D ₃ and D ₄ When part is high level and part is low level, the MP3~MP6 tubes are alternately turned on, and the charge and discharge current of the capacitor is between the maximum charge and discharge current and the minimum charge and discharge current. At this time, the clock frequency generated by the clock signal generator is at the highest The range varies between the clock frequency and the lowest clock frequency. Since the micro current sources I ₁ , I ₂ , I ₃ and I ₄ are much smaller than the main current source I _main , the frequency of the clock signal generator only changes within a small range, resulting in frequency jitter effect (that is, spread spectrum output) , so as to realize the spread spectrum clock signal of digital current modulation. At the same time, the spectrum at the original high-order harmonic will be extended to a frequency band, so the spectrum amplitude is reduced and the EMI performance is improved.

The present invention adopts the 0.5μm BCD process of a standard foundry line, and applies it to a flyback switching power supply. The area occupied by the entire clock generator is 0.561mm2, and the area occupied by the spread spectrum circuit is 0.032mm2. The power consumption is 1.68mW. The invention only adds a state machine, several current switches and several current branches to the ordinary clock generation circuit to realize the digital spread spectrum clock. It does not need some programming expertise, and the structure is simple and easy to operate. .

Figure 4 is a comparison diagram of the output waveform spectrum with and without the spread spectrum circuit. Comparing the peak values of the output waveform spectrum in the two figures, it can be seen that the EMI peak value is reduced by about 12dB after adding the spread spectrum circuit. According to the principle of energy conservation, the total energy before and after frequency spreading does not change, so when the frequency spreads, the EMI peak value naturally decreases.

Claims (3)

1. the spread-spectrum clock signal generator of a digitlization current-modulation comprises an ordinary clock signal generator, it is characterized in that, comprises that also a digitlization modulated current produces circuit; Switches set and 4 micro-current sources that said Digital Modulation current generating circuit is made up of a state machine that produces 4 binary signals, 4 switches are formed; In said Digital Modulation current generating circuit, the binary signal D that utilizes state machine to produce _iCome the K switch in the control switch group _iOpening and closing, work as K switch _iDuring unlatching, i the electric current I that micro-current source produces _iPass through K switch _iThe modulation output current I that the whole Digital Modulation current generating circuit that is added to produces _DVCIn the middle of; And the modulation output current I that said Digital Modulation current generating circuit produces _DVCWith oscillating capacitance C in the said ordinary clock signal generator ₀The bias current I that discharges and recharges _MainBe superimposed and constitute oscillating capacitance C ₀Charging and discharging currents I _SumI=1 wherein, 2,3,4;

Said 4 micro-current sources are made up of four PMOS pipe MP7～MP10; The source electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe connects power source voltage Vcc; The gate interconnection that MP7 manages, MP8 manages, MP9 manages and MP10 manages also connects the grid that MP11 manages, MP12 manages and MP13 manages; The drain electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe is output current I respectively ₁, I ₂, I ₃And I ₄

The switches set that said 4 switches are formed is made up of four PMOS pipe MP3～MP6; The source electrode of MP3 pipe connects the drain electrode of MP7 pipe, and the source electrode of MP4 pipe connects the drain electrode of MP8 pipe, and the source electrode of MP5 pipe connects the drain electrode of MP9 pipe, and the source electrode of MP6 pipe connects the drain electrode of MP10 pipe; The drain electrode interconnection of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe also connects the MP1 pipe and the source electrode of MP2 pipe;

The state machine of 4 binary signals of said generation is one 4 digit counter, the binary signal D that utilizes state machine to produce ₁, D ₂, D ₃And D ₄Connect the grid of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe respectively; The output of comparator C OM_1 and COM_2 links to each other with the input end of clock of 4 digit counters through inverter INV2;

Said ordinary clock signal generator comprises:

An oscillating capacitance C ₀The bias current I that discharges and recharges _MainCurrent source: this current source produces bias current I by five PMOS pipe MP11～MP15 and two NMOS pipe MN3～MN4 through mirror image by a certain percentage _MainThe source electrode of PMOS pipe MP11, MP12, MP13 and MP14 connects power source voltage Vcc; The drain electrode of pipe MP14 pipe connects the drain electrode of MN4 pipe, and the grid of pipe MP14 pipe connects the signal X1 of external circuit; The drain electrode of MP13 pipe connects the source electrode of MP15 pipe; The drain electrode of MP15 pipe links to each other with the drain electrode of MP12 pipe and the drain electrode of MN3 pipe; The external protective circuit signal of the grid Y1 of MP15 pipe; The grid of MN3 pipe and MN4 pipe links to each other and connects the drain electrode that MN4 manages, the source ground Vss of MN3 pipe and MN4 pipe; The gate interconnection of MP11 pipe, MP12 pipe and MP13 pipe also connects the drain electrode that MP12 manages, the drain electrode output oscillating capacitance C of MP11 pipe ₀The bias current I that discharges and recharges _Main

A PMOS difference input is right: this difference input is to being made up of a pair of PMOS pipe MP1 and MP2; The source electrode of MP1 pipe and MP2 pipe connects the drain electrode of MP11 pipe;

The grid of a reverser INV1:MP2 pipe connects the grid of MP1 pipe through reverser INV1;

An electric current is heavy: this electric current is heavy to be made up of NMOS pipe MN1 and MN2; The drain electrode that MN1 pipe and MN2 manage connects the drain electrode of MP1 pipe and MP2 pipe respectively, and the gate interconnection of MN1 pipe and MN2 pipe also connects the drain electrode that MN1 manages, the source ground Vss of MN1 pipe and MN2 pipe;

A comparison circuit: this comparison circuit is made up of two comparator C OM_1 and COM_2; V _Ref1And V _Ref2Be its benchmark voltage, from external reference circuit, and all greater than 0V; EN1 and EN2 are respectively the Enable Pins of comparator C OM_1 and COM_2, and it is effective to be all low level; The input of comparator C OM_1 and COM_2 is imported V respectively _Ref1And V _Ref2, another input interconnection; The output interconnection of comparator C OM_1 and COM_2 also connects the input of reverser INV1 and the grid of MP2 pipe;

An oscillating capacitance C ₀: oscillating capacitance C ₀A pole plate ground connection Vss, the grid that interconnection input and the MN1 pipe that another pole plate meets comparator C OM_1 and COM_2 and MN2 manage.

2. the spread-spectrum clock signal generator of digitlization current-modulation according to claim 1 is characterized in that, if the binary signal D that state machine produces _iTo K switch _iOpen for high level, low level is closed, then the modulation output current of Digital Modulation current generating circuit generation

If the binary signal D that state machine produces _iTo K switch _iOpen for low level, high level is closed, then the modulation output current of Digital Modulation current generating circuit generation

Wherein

With D _iIt is complementary relationship.

3. the spread-spectrum clock signal generator of digitlization current-modulation according to claim 1 is characterized in that, oscillating capacitance C in the said ordinary clock signal generator ₀The bias current I that discharges and recharges _MainExceed the electric current I of each micro-current source in the Digital Modulation current generating circuit _iMore than two one magnitude.

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