CN101719762B - Spread-spectrum clock signal generator for digital current modulation - Google Patents

Spread-spectrum clock signal generator for digital current modulation Download PDF

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CN101719762B
CN101719762B CN2009102162404A CN200910216240A CN101719762B CN 101719762 B CN101719762 B CN 101719762B CN 2009102162404 A CN2009102162404 A CN 2009102162404A CN 200910216240 A CN200910216240 A CN 200910216240A CN 101719762 B CN101719762 B CN 101719762B
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pipe
current
drain electrode
clock signal
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CN101719762A (en
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张波
郭海燕
李肇基
李泽宏
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University of Electronic Science and Technology of China
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Abstract

The invention relates to a spread-spectrum clock signal generator for digital current modulation, which belongs to the technical field of electronics. In the invention, a digital modulation current generation circuit comprising a state machine, a switching group and micro current sources is added on the basis of a common clock signal generator, and a binary signal Di generated by the state machine is utilized to control the opening and the closing of a switch Ki; when the switch Ki is opened, current Ii generated by an ith micro current source is superposed into modulation output current IDVC; and the modulation output current IDVC and the charge/discharge bias current Imain of an oscillation capacitor C0 in the common clock signal generator are superposed together to form the charge/discharge current Isum of the oscillation capacitor C0. The invention generates a spread-spectrum clock signal by changing the magnitude of the charge/discharge current of the oscillation capacitor in the clock signal generator and avoids using a filtering component which is difficult to integrate under a precondition of achieving favorable EMI performance, thereby lowering the area of a chip; meanwhile, the invention has lower power consumption and favorable robustness.

Description

A kind of spread-spectrum clock signal generator of digitlization current-modulation
Technical field
The invention belongs to electronic technology field, relate to clock signal generating technique, frequency modulating technology and anti-electromagnetic interference technology, the frequency-spreading clock generator that particularly adopts Digital Modulation current-modulation mode to realize.
Background technology
Improving constantly of integrated level is a core developing direction of microelectric technique; And improving constantly along with chip integration; Increasing control circuit and Power Processing device are integrated in the chip, and working frequency of chip is increasingly high, make that electromagnetic interference problem is more and more serious.International wireless electrical interference Professional Committee (CISPR) International Standards Organization that for this reason sets up in the International Electrotechnical Commission (IEC); And FCC (FCC) etc. has the mechanism of government function, successively works up various electromagnetic compatibilities (EMC) standard, method of testing and relevant law.How to promote the antijamming capability of high integrated chip, reducing integrated chip simultaneously is a urgent problem to the interference of external environment condition.
Have the scheme of multiple inhibition circuit electromagnetic interference (EMI) to be suggested in recent years, for example add coupling capacitance, slope control reduces package inductance, spread spectrum or the like.Wherein spread spectrum has omitted filter circuit, and circuit structure simply effectively is widely used.It is distributed to the energy that concentrates on switching frequency and the harmonic wave thereof on their discrete sidebands on every side through the method for modulation switch frequency, reduces the electromagnetic interference amplitude on each frequency thus, reaches the limit value that is lower than the electromagnetic interference standard code.
Clock signal generator is a tandem circuit commonly used in the electronic technology, and it is used very extensively.In the existing various integrated circuit, increasing clock signal generator is integrated, this just makes the EMI performance of clock signal generator itself must meet the EMC standard.Under such technical need, various spread-spectrum clock signal generators arise at the historic moment.
Traditional spread-spectrum clock signal generator is normally produced by phase-locked loop circuit.Three kinds of implementations are arranged usually: first kind, a ∑ Delta modulator is introduced phase-locked loop (PLLs) in the prior art; Second kind of output to heterogeneous phase-locked loop is carried out digitized processing or is produced clock with delay lock loop (DLL); The third is with directly modulation of voltage-controlled oscillator (VCO) in PLLs.Preceding two kinds of structure more complicated, the third is simple in structure and do not have a ∑ Δ noise, but when incoming frequency when relatively lower or desired bandwidth ratio is less, the big filtering device of needs in loop filtering, this will take very large tracts of land, make fully integrated difficulty.
Summary of the invention
The present invention provides a kind of spread-spectrum clock signal generator of digitlization current-modulation; This spread-spectrum clock signal generator utilizes digitlization variable current modulation technique; Size through the charge/discharge current of oscillating capacitance in the direct change clock signal generator changes clock signal generating circuit clock signal frequency, thereby produces frequency-spreading clock signal.The present invention has avoided the use of and has been difficult to integrated filtering device under the prerequisite with good EMI performance, thereby has reduced area of chip; And adopt digital technology to produce frequency-spreading clock signal, mean that the present invention has lower power consumption and good robustness.
Technical scheme of the present invention is following:
A kind of spread-spectrum clock signal generator of digitlization current-modulation, as shown in Figure 1, comprise that a clock signal generator and a digitlization modulated current produce circuit.Said Digital Modulation current generating circuit is made up of the state machine of a generation M position binary signal, switches set and M micro-current source that a M switch is formed; In said Digital Modulation current generating circuit, the binary signal D that utilizes state machine to produce i(i=1,2,3 ..., M) come K switch in the control switch group i(i=1,2,3 ..., K switch is worked as in opening and closing M) iDuring unlatching, i the electric current I that micro-current source produces iPass through K switch iThe modulation output current I that the whole Digital Modulation current generating circuit that is added to produces DVCIn the middle of; And the modulation output current I that said Digital Modulation current generating circuit produces DVCWith oscillating capacitance C in the said ordinary clock signal generator 0The bias current I that discharges and recharges MainBe superimposed and constitute oscillating capacitance C 0Charging and discharging currents I Sum
If the binary signal D that state machine produces iTo K switch iOpen for high level, low level is closed, then the modulation output current of Digital Modulation current generating circuit generation
Figure GSB00000504318400021
If the binary signal D that state machine produces iTo K switch iOpen for low level, high level is closed, then the modulation output current of Digital Modulation current generating circuit generation
Figure GSB00000504318400022
Wherein
Figure GSB00000504318400023
With D iIt is complementary relationship.
The modulation output current I that the Digital Modulation current generating circuit produces DVCBe one with state machine output signal D 1D 2D iD MChange and the variable current of Discrete Change oscillating capacitance C in it and the ordinary clock signal generator 0The bias current I that discharges and recharges MainBe superimposed and determined oscillating capacitance C 0Charging and discharging currents.If definition I Sum=I DVC+ I Main, clock frequency and oscillating capacitance C that then whole spread-spectrum clock signal generator produces 0The relation of charging and discharging currents can be expressed as f=ρ (I Sum), work as I SumWhen changing within the specific limits, the clock frequency that whole spread-spectrum clock signal generator produces also changes within the specific limits, thereby realizes spread spectrum, and the peak value of its high order harmonic component place frequency spectrum is minimized, and electromagnetic interference has obtained inhibition.Discharge and recharge in the cycle state machine output signal D at one 1D 2D iD MCorresponding stationary state, the modulation output current I that the Digital Modulation current generating circuit produces DVCAlso be constant.If binary signal D with the state machine generation iTo K switch iFor low level is opened, high level is closed and is example, then digital modulated current produces circuit output current I DVCFill C with oscillating capacitance 0The oscillogram variation relation of discharge voltage is as shown in Figure 2.
Need to prove:
1, the electric current I of each micro-current source in the Digital Modulation current generating circuit DVCCan be identical, also can be different.
2, the electric current I of micro-current source iShould be far smaller than oscillating capacitance C in the ordinary clock signal generator 0The bias current I that discharges and recharges Main, in the practical application, I MainShould exceed I iMore than two one magnitude.
3, the number M of micro-current source in the Digital Modulation current generating circuit (figure place of the binary signal that produces corresponding to the switch number and the state machine of switches set) should be not too small, and is unsuitable excessive yet.If the M value is too little, then the spread spectrum effect of current-modulation is not clearly, is not enough to guarantee the EMI performance of whole spread-spectrum clock signal generator; If after the M value arrived certain numerical value, the spread spectrum effect of current-modulation can reach certain limit, if increase the value of M again, the spread spectrum effect of current-modulation can not increase yet, and can increase the chip area and the device cost of whole spread-spectrum clock signal generator on the contrary.In the practical application, the span of M should be between 3～10.
4, state machine is as long as can produce the control that a series of binary numeral (high-low level) just can be realized switch.In the present invention, state machine can adopt the random signal generator to realize, the binary signal that also can adopt rule to change produces circuit (like counter) and realizes, even can adopt software programming to realize.
The spread-spectrum clock signal generator of digitlization current-modulation provided by the invention changes clock signal generating circuit clock signal frequency through the size of the charge/discharge current of oscillating capacitance in the direct change clock signal generator, thereby produces frequency-spreading clock signal.The present invention has avoided the use of and has been difficult to integrated filtering device under the prerequisite with good EMI performance, thereby has reduced area of chip; And adopt digital technology to produce frequency-spreading clock signal, make the present invention have lower power consumption and good robustness.
Description of drawings
Fig. 1 is the structure principle chart of the spread-spectrum clock signal generator of digitlization current-modulation provided by the invention.
Fig. 2 is the Digital Modulation electric current I DVCWith oscillating capacitance C 0The oscillogram that charge and discharge are pressed.
Fig. 3 is the circuit theory diagrams of the spread-spectrum clock signal generator of a kind of concrete digitlization current-modulation provided by the invention.
Fig. 4 is the output spectrum comparison that has added the clock signal generator of Digital Modulation current generating circuit (spectrum spreading circuit) and do not added the clock signal generator of spectrum spreading circuit.
Embodiment
A kind of spread-spectrum clock signal generator of concrete digitlization current-modulation, as shown in Figure 3, produce circuit by a clock signal generator and a digitlization modulated current and constitute.
Said clock signal generator comprises:
An oscillating capacitance C 0The bias current I that discharges and recharges MainCurrent source: this current source produces bias current I by five PMOS pipe MP11～MP15 and two NMOS pipe MN3～MN4 through mirror image by a certain percentage MainThe source electrode of PMOS pipe MP11, MP12, MP13 and MP14 connects power source voltage Vcc; The drain electrode of pipe MP14 pipe connects the drain electrode of MN4 pipe, and the grid of pipe MP14 pipe connects the signal X1 of external circuit; The drain electrode of MP13 pipe connects the source electrode of MP15 pipe, and the grid of MP13 pipe links to each other with the grid of MP12 pipe; The drain electrode of MP15 pipe links to each other with the drain electrode of MP12 pipe and the drain electrode of MN3 pipe; The external protective circuit signal of the grid Y1 of MP15 pipe; The grid of MN3 pipe and MN4 pipe links to each other and connects the drain electrode that MN4 manages, the source ground Vss of MN3 pipe and MN4 pipe; The gate interconnection of MP11 pipe, MP12 pipe and MP13 pipe also connects the drain electrode that MP12 manages, the drain electrode output oscillating capacitance C of MP11 pipe 0The bias current I that discharges and recharges Main
When signal X1 is low level, produce current reference electric current I MN4, produce image current thus by a certain percentage and pass through MN3; When signal Y1 was high level, MP15 ended, and electric current all flows through MP12; When signal Y1 is low level, the MP15 conducting, MP13 divides a big chunk of walking to flow through MP12 electric current, and circuit advances people's guard mode.Because the grid voltage of MP12 and MP11 is identical, so MP11 produces the bias current I of electric capacity charging through mirror image Main
A PMOS difference input is right: this difference input is to being made up of a pair of PMOS pipe MP1 and MP2; The source electrode of MP1 pipe and MP2 pipe connects the drain electrode of MP11 pipe.
The grid of a reverser INV1:MP2 pipe connects the grid of MP1 pipe through reverser INV1.
An electric current is heavy: this electric current is heavy to be made up of NMOS pipe MN1 and MN2; The drain electrode that MN1 pipe and MN2 manage connects the drain terminal of MP1 pipe and MP2 pipe respectively, and the gate interconnection of MN1 pipe and MN2 pipe also connects the drain electrode that MN1 manages, the source ground Vss of MN1 pipe and MN2 pipe.Through the breadth length ratio of adjustment pipe MN1 and MN2, can control capacitance C 0The size of charge and discharge electric current is used for confirming the time constant ratio of electric capacity charge and discharge, to reach the duty ratio of accurate control output waveform.
A comparison circuit: this comparison circuit is made up of two comparator C OM_1 and COM_2; Vref1 and Vref2 are its benchmark voltage, from external reference circuit, and all greater than 0V; EN1 and EN2 are respectively the Enable Pins of comparator C OM_1 and COM_2, and it is effective to be all low level; The input of comparator C OM_1 and COM_2 is imported Vref1 and Vref2 respectively, another input interconnection; The output interconnection of comparator C OM_1 and COM_2 also connects the input of reverser INV and the grid of MP2 pipe.
An oscillating capacitance C0: the pole plate ground connection Vss of oscillating capacitance C0, another pole plate connects the interconnection input of comparator C OM_1 and COM_2 and the grid of MN1 pipe and MN2 pipe.
Said Digital Modulation current generating circuit comprises: one produces the state machine of 4 binary signals, 4 switches set and 4 micro-current sources that switch is formed.
Said 4 micro-current sources are made up of four PMOS pipe MP7～MP10; The source electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe connects power source voltage Vcc; The gate interconnection that MP7 manages, MP8 manages, MP9 manages and MP10 manages also connects the grid that MP11 manages, MP12 manages and MP13 manages; The drain electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe is output current I respectively 1, I 2, I 3And I 4Current source I 1, I 2, I 3And I 4All get through the mirror image reference current.
The switches set that said 4 switches are formed is made up of four PMOS pipe MP3～MP6; The source electrode of MP3 pipe connects the drain electrode of MP7 pipe, and the source electrode of MP4 pipe connects the drain electrode of MP8 pipe, and the source electrode of MP5 pipe connects the drain electrode of MP9 pipe, and the source electrode of MP6 pipe connects the drain electrode of MP10 pipe; The drain electrode interconnection of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe also connects the MP1 pipe and the source electrode of MP2 pipe.
The state machine of 4 binary signals of said generation is one 4 digit counter, its output signal D 1, D 2, D 3And D 4Connect the grid of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe respectively.The output of comparator C OM_1 and COM_2 links to each other with the input end of clock of 4 digit counters through inverter INV2; Utilize the signal all the time of the spread-spectrum clock signal generator of whole digitlization current-modulation to be output as counter clock input signal is provided, help reducing the cost of the spread-spectrum clock signal generator of whole digitlization current-modulation like this.
The operation principle of the spread-spectrum clock signal generator of above-mentioned digitlization current-modulation is:
In the ordinary clock signal generator, Vref1 and Vref2 provide reference voltage from the external circuit reference circuit for this circuit, are made up of two stage comparator and differential pair two parts.
Differential pair is made up of MP1, MP2, MN1, MN2, and IN1 and IN2 are two opposite signals.When IN1 is low level, the MP1 conducting, MP2, MN1, MN2 end, the electric capacity charging; When IN1 is high level, MP2 conducting MN1, also conducting of MN2, MP1 ends, capacitor discharge.
IN1 is a low level when electric capacity charges, and IN2 is a high level, comparator C OM_1 work at this moment, and comparator C OM_2 ends.The output voltage V CO of differential pair is during less than Vref1, and IN1 is a low level, and IN2 is a high level, and greater than Vref1, IN1 becomes high level up to the output voltage V CO of differential pair, and IN2 becomes low level, and electric capacity stops charging, begins discharge.When capacitor discharge, IN1 is a high level, and IN2 is a low level, and at this moment comparator C OM_1 ends, comparator C OM_2 work.The output voltage V CO of differential pair is during greater than Vref2, and IN1 is a high level, and IN2 is a low level, and less than Vref2, IN1 becomes low level up to the output voltage V CO of differential pair, and IN2 becomes high level, and electric capacity stops discharge, begins charging.
The clock signal generator work that discharges and recharges of repetition that comes to this, thus a comparatively constant oscillator signal (clock signal) exported.At clock signal generator duration of work, D 1, D 2, D 3And D 4State can change along with the variation of state machine output state.Work as D 1, D 2, D 3And D 4When all being low level, 4 whole conductings of branch road of their control, charging and discharging currents is maximum, and the clock frequency that clock signal generator produces is the highest; Work as D 1, D 2, D 3And D 4When all being high level, M the branch road of their control all turn-offs, and charging and discharging currents is minimum, and the clock frequency that clock signal generator produces is minimum; Work as D 1, D 2, D 3And D 4Part is a high level; When part is low level; MP3～staggered the conducting of MP6 pipe; The charging and discharging currents of electric capacity is between maximum charging and discharging currents and the minimum charging and discharging currents, changes in the scope of clock frequency between maximum clock frequency and minimum clock frequency that this moment, clock signal generator produced.Because micro-current source I 1, I 2, I 3And I 4Than master current source I MainLittle a lot, the frequency of clock signal generator just changes in a very little scope, produces frequency jitter effect (being spread spectrum output), thereby realizes the frequency-spreading clock signal of digitlization current-modulation.Simultaneously, the frequency spectrum at former high order harmonic component place will expand to a frequency band, thereby the spectrum amplitude reduction, and the EMI performance is improved.
The present invention adopts 0.5 μ m BCD technology of certain standard foundry line, and is applied to an inverse-excitation type switch power-supply, and the shared area of whole clock generator is 0.561mm2, and wherein the shared area of spectrum spreading circuit is 0.032mm2.Power consumption is that 1.68mW. the present invention only produces at ordinary clock and added state machine and several current switch and several current branch in the circuit and just realized the digitlization spread spectrum clock, does not need the professional knowledge of some programmings, easy operating simple in structure.
Fig. 4 is for having added spectrum spreading circuit and not added spectrum spreading circuit output waveform frequency spectrum comparison diagram.Relatively the output waveform spectrum peak can be known among two figure, has added the EMI peak value behind the spectrum spreading circuit and has fallen 12dB is probably arranged.According to principle of conservation of energy, the gross energy before and after the spread spectrum does not become, so after the frequency expansion was opened, the EMI peak value had just reduced naturally.

Claims (3)

1. the spread-spectrum clock signal generator of a digitlization current-modulation comprises an ordinary clock signal generator, it is characterized in that, comprises that also a digitlization modulated current produces circuit; Switches set and 4 micro-current sources that said Digital Modulation current generating circuit is made up of a state machine that produces 4 binary signals, 4 switches are formed; In said Digital Modulation current generating circuit, the binary signal D that utilizes state machine to produce iCome the K switch in the control switch group iOpening and closing, work as K switch iDuring unlatching, i the electric current I that micro-current source produces iPass through K switch iThe modulation output current I that the whole Digital Modulation current generating circuit that is added to produces DVCIn the middle of; And the modulation output current I that said Digital Modulation current generating circuit produces DVCWith oscillating capacitance C in the said ordinary clock signal generator 0The bias current I that discharges and recharges MainBe superimposed and constitute oscillating capacitance C 0Charging and discharging currents I SumI=1 wherein, 2,3,4;
Said 4 micro-current sources are made up of four PMOS pipe MP7～MP10; The source electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe connects power source voltage Vcc; The gate interconnection that MP7 manages, MP8 manages, MP9 manages and MP10 manages also connects the grid that MP11 manages, MP12 manages and MP13 manages; The drain electrode of MP7 pipe, MP8 pipe, MP9 pipe and MP10 pipe is output current I respectively 1, I 2, I 3And I 4
The switches set that said 4 switches are formed is made up of four PMOS pipe MP3～MP6; The source electrode of MP3 pipe connects the drain electrode of MP7 pipe, and the source electrode of MP4 pipe connects the drain electrode of MP8 pipe, and the source electrode of MP5 pipe connects the drain electrode of MP9 pipe, and the source electrode of MP6 pipe connects the drain electrode of MP10 pipe; The drain electrode interconnection of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe also connects the MP1 pipe and the source electrode of MP2 pipe;
The state machine of 4 binary signals of said generation is one 4 digit counter, the binary signal D that utilizes state machine to produce 1, D 2, D 3And D 4Connect the grid of MP3 pipe, MP4 pipe, MP5 pipe and MP6 pipe respectively; The output of comparator C OM_1 and COM_2 links to each other with the input end of clock of 4 digit counters through inverter INV2;
Said ordinary clock signal generator comprises:
An oscillating capacitance C 0The bias current I that discharges and recharges MainCurrent source: this current source produces bias current I by five PMOS pipe MP11～MP15 and two NMOS pipe MN3～MN4 through mirror image by a certain percentage MainThe source electrode of PMOS pipe MP11, MP12, MP13 and MP14 connects power source voltage Vcc; The drain electrode of pipe MP14 pipe connects the drain electrode of MN4 pipe, and the grid of pipe MP14 pipe connects the signal X1 of external circuit; The drain electrode of MP13 pipe connects the source electrode of MP15 pipe; The drain electrode of MP15 pipe links to each other with the drain electrode of MP12 pipe and the drain electrode of MN3 pipe; The external protective circuit signal of the grid Y1 of MP15 pipe; The grid of MN3 pipe and MN4 pipe links to each other and connects the drain electrode that MN4 manages, the source ground Vss of MN3 pipe and MN4 pipe; The gate interconnection of MP11 pipe, MP12 pipe and MP13 pipe also connects the drain electrode that MP12 manages, the drain electrode output oscillating capacitance C of MP11 pipe 0The bias current I that discharges and recharges Main
A PMOS difference input is right: this difference input is to being made up of a pair of PMOS pipe MP1 and MP2; The source electrode of MP1 pipe and MP2 pipe connects the drain electrode of MP11 pipe;
The grid of a reverser INV1:MP2 pipe connects the grid of MP1 pipe through reverser INV1;
An electric current is heavy: this electric current is heavy to be made up of NMOS pipe MN1 and MN2; The drain electrode that MN1 pipe and MN2 manage connects the drain electrode of MP1 pipe and MP2 pipe respectively, and the gate interconnection of MN1 pipe and MN2 pipe also connects the drain electrode that MN1 manages, the source ground Vss of MN1 pipe and MN2 pipe;
A comparison circuit: this comparison circuit is made up of two comparator C OM_1 and COM_2; V Ref1And V Ref2Be its benchmark voltage, from external reference circuit, and all greater than 0V; EN1 and EN2 are respectively the Enable Pins of comparator C OM_1 and COM_2, and it is effective to be all low level; The input of comparator C OM_1 and COM_2 is imported V respectively Ref1And V Ref2, another input interconnection; The output interconnection of comparator C OM_1 and COM_2 also connects the input of reverser INV1 and the grid of MP2 pipe;
An oscillating capacitance C 0: oscillating capacitance C 0A pole plate ground connection Vss, the grid that interconnection input and the MN1 pipe that another pole plate meets comparator C OM_1 and COM_2 and MN2 manage.
2. the spread-spectrum clock signal generator of digitlization current-modulation according to claim 1 is characterized in that, if the binary signal D that state machine produces iTo K switch iOpen for high level, low level is closed, then the modulation output current of Digital Modulation current generating circuit generation
Figure FSB00000647588600021
If the binary signal D that state machine produces iTo K switch iOpen for low level, high level is closed, then the modulation output current of Digital Modulation current generating circuit generation
Figure FSB00000647588600022
Wherein
Figure FSB00000647588600023
With D iIt is complementary relationship.
3. the spread-spectrum clock signal generator of digitlization current-modulation according to claim 1 is characterized in that, oscillating capacitance C in the said ordinary clock signal generator 0The bias current I that discharges and recharges MainExceed the electric current I of each micro-current source in the Digital Modulation current generating circuit iMore than two one magnitude.
CN2009102162404A 2009-11-18 2009-11-18 Spread-spectrum clock signal generator for digital current modulation Expired - Fee Related CN101719762B (en)

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US9923566B1 (en) * 2016-08-30 2018-03-20 Stmicroelectronics International N.V. Spread spectrum clock generator
CN107591680B (en) * 2017-09-26 2024-03-29 南京美辰微电子有限公司 Discrete laser driver tail current source
CN112615622B (en) * 2020-12-26 2023-03-24 上海艾为电子技术股份有限公司 Spread spectrum clock generator and electronic equipment
CN112994445B (en) * 2021-04-25 2021-07-27 四川蕊源集成电路科技有限公司 Apparatus and method for reducing electromagnetic interference of DC-DC power supply

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CN1567989A (en) * 2003-06-13 2005-01-19 奇景光电股份有限公司 Apparatus for reducing electromagnetic wave interference and method thereof
CN101079632A (en) * 2007-06-15 2007-11-28 智原科技股份有限公司 Low-jitter spread spectrum clocking generator
JP2008227613A (en) * 2007-03-08 2008-09-25 Kawasaki Microelectronics Kk Spread spectrum clock generator

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Publication number Priority date Publication date Assignee Title
CN1567989A (en) * 2003-06-13 2005-01-19 奇景光电股份有限公司 Apparatus for reducing electromagnetic wave interference and method thereof
JP2008227613A (en) * 2007-03-08 2008-09-25 Kawasaki Microelectronics Kk Spread spectrum clock generator
CN101079632A (en) * 2007-06-15 2007-11-28 智原科技股份有限公司 Low-jitter spread spectrum clocking generator

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