CN219267655U

CN219267655U - Array substrate capable of reducing parasitic capacitance coupling influence

Info

Publication number: CN219267655U
Application number: CN202320116235.1U
Authority: CN
Inventors: 毛清平
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2023-01-28
Filing date: 2023-01-28
Publication date: 2023-06-27
Anticipated expiration: 2033-01-28

Abstract

The utility model relates to the technical field of displays, and provides an array substrate for reducing the influence of parasitic capacitance coupling, which comprises: a glass substrate; a first metal layer forming a gate electrode, a first CK signal wiring and a third CK signal wiring which are distributed at intervals; a gate insulating layer plated on the upper surfaces of the glass substrate and the first metal layer; a pixel electrode; an active layer; the second metal layer forms source electrodes, drain electrodes and first signal connecting lines which are distributed at intervals; a passivation layer plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode; the conducting layer is plated on the upper surface of the passivation layer; and the shading metal layer is plated on the upper surface of the passivation layer. The utility model has the advantages that: the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, and the parasitic capacitance coupling effect is reduced, so that the feed through voltage is reduced.

Description

Array substrate capable of reducing parasitic capacitance coupling influence

Technical Field

The utility model relates to the technical field of displays, in particular to an array substrate capable of reducing the influence of parasitic capacitance coupling.

Background

In the case of a TFT-LCD display, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is generally called the parasitic capacitance C _gd . The grid electrode of the TFT device is connected with the grid lines which are transversely distributed and used for controlling the on-off of the TFT device; the source electrode of the TFT device is connected with the data lines which are longitudinally distributed and used for writing the data voltage to be displayed into the TFT device; when the TFT is turned on, the source electrode is conducted with the drain electrode, the data voltage enters the drain electrode and reaches the liquid crystal capacitor Cst from the pixel electrode, and the light transmittance of the liquid crystal is adjusted; when the TFT is turned off, the source and drain are turned off, and the data voltage of the source cannot enter the drain. The data voltage of the source electrode changes in positive and negative polarities periodically, and is a deflection voltage for making the liquid crystal generate positive and negative polarities.

Referring to fig. 1 and 2, at the instant of TFT off, the gate voltage V _g V from high level _high V instantaneously dropping to low level _low Due to parasitic capacitance C _gd The presence of (C) will be V _g The transient change of (a) is coupled to the drain electrode, the drain voltage is reduced due to the influence of parasitic capacitance coupling (coupling influence), and the voltage difference generated between the pixel electrode and the drain electrode can cause the jump of the voltage of the pixel electrode due to the fact that the TFT device is turned off at the moment, and the jump variable DeltaV is called a feedback voltage. In the waveform diagram of FIG. 2, V _g Is the gate voltage, V _d Is the drain voltage in an ideal state,

is the center point of the actually supplied common electrode voltage, i.e. the actually supplied positive and negative deflection voltages, V _p (t) is the actual pixel electrode voltage, V _com Is the common electrode voltage in the ideal state of keeping the same voltage at both ends of the liquid crystal in the positive and negative polarity state, V _offset Is the deviation of the ideal common electrode voltage from the actual common electrode voltage, T _f Is the switching period of the TFT device, V _lc ＞V _com Is the region where the pixel electrode voltage is greater than the common electrode voltage in the current ideal state, V _lc ＜V _com Is an image ofThe pixel electrode voltage is smaller than the region of the common electrode voltage in the current ideal state.

As shown in FIG. 2, the existence of the feed through voltage results in an ideal state of the common electrode V _com The point position deviates from the center position of the actually provided positive and negative deflection voltages, namely the common electrode voltage in an ideal state changes, but the actually provided positive and negative deflection voltages are unchanged, so that voltages at two ends of liquid crystal in the positive and negative states are different, the deflection angles of the liquid crystal in the positive and negative states are different, the light quantity of the array substrate is different, and the picture of the liquid crystal display is flickering. Reducing the Feedthrough voltage is a problem that should be solved at present.

Disclosure of Invention

The utility model aims to solve the technical problem of providing an array substrate for reducing the influence of parasitic capacitance coupling, and by arranging a conductive layer above a drain electrode, the potential of the conductive layer is opposite to that of a grid electrode, and the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, so that the influence of parasitic capacitance coupling is reduced, and the feedback voltage is reduced.

The utility model is realized in the following way:

an array substrate for reducing parasitic capacitance coupling effects, comprising:

a glass substrate;

a first metal layer plated on the upper surface of the glass substrate to form grid electrodes, a first CK signal wiring and a third CK signal wiring which are distributed at intervals, wherein the potential of the first CK signal wiring is opposite to that of the third CK signal wiring;

the gate insulating layer is plated on the upper surfaces of the glass substrate and the first metal layer, a first hole, a second hole and a third hole are formed in the gate insulating layer, the gate is exposed out of the first hole, the first CK signal wire is exposed out of the second hole, and the third CK signal wire is exposed out of the third hole;

the pixel electrode is plated on the upper surface of the gate insulating layer and is also positioned at the side of the grid electrode;

the first electrode block is plated on the first hole and is also connected with the grid electrode;

the second electrode block is plated on the second hole and is also connected with the first CK signal wiring;

the third electrode block is plated on the third hole and is also connected with the third CK signal wiring;

the first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;

the active layer is plated on the upper surface of the grid insulation layer and is also positioned right above the grid;

the second metal layer is plated on the upper surface of the gate insulating layer, source electrodes, drain electrodes and first signal connecting wires which are distributed at intervals are formed, the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the drain electrodes are also connected with the pixel electrodes, the right end of the first signal connecting wire is connected with the first electrode block, and the left end of the first signal connecting wire is connected with the second electrode block;

the passivation layer is plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode, a fourth hole is formed in the passivation layer, and the third electrode block is exposed out of the fourth hole;

the conducting layer is plated on the upper surface of the passivation layer and is also positioned right above the drain electrode, the upper surface of the passivation layer is also plated with a second signal connecting wire, the conducting layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire passes through the fourth hole and is connected with the third electrode block;

the shading metal layer is plated on the upper surface of the passivation layer and is also positioned right above the channel of the active layer, and the shading metal layer, the conducting layer and the second signal connecting line are arranged at intervals;

the shading metal layer, the conducting layer and the second signal connecting wire are made of the same material as the first metal layer.

Further, the method further comprises the following steps:

the second metal layer also forms TP wirings which are distributed at intervals;

the outer insulating layer is plated on the upper surfaces of the conducting layer, the shading metal layer and the passivation layer, a fifth hole is formed in the outer insulating layer, the fifth hole penetrates through the passivation layer, and the TP wiring is exposed out of the fifth hole;

and the public electrode is plated on the upper surface of the outer insulating layer and also penetrates through the fifth hole to be connected with the TP wiring.

Further, the first metal layer, the second metal layer, the conductive layer, the second signal connection line and the shading metal layer are all of a Ti/AL/Ti three-layer structure or an MO/AL/MO three-layer structure.

Further, the gate insulating layer is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer is of SiO ₂ The outer insulating layer is made of SiOx, siNO or SiNx.

Further, the active layer is made of an IGZO material, and the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are made of an ITO material.

Further, the first metal layer further forms second CK signal wires and fourth CK signal wires which are distributed at intervals, and the potential of the second CK signal wires is opposite to that of the fourth CK signal wires;

the first CK signal wire is connected with the grid electrode of the array substrate of the first row, the second CK signal wire is connected with the grid electrode of the array substrate of the second row, the third CK signal wire is connected with the conductive layer of the array substrate of the first row, and the fourth CK signal wire is connected with the conductive layer of the array substrate of the second row.

Further, the signal timing phase of the first CK signal trace is one quarter cycle earlier than the signal timing phase of the second CK signal trace, and the signal timing phase of the third CK signal trace is one quarter cycle earlier than the signal timing phase of the fourth CK signal trace.

The utility model has the advantages that: 1. a conductive layer is arranged above the drain electrode, a complementary capacitor is formed between the conductive layer and the drain electrode, a signal of the grid electrode is provided by a first CK signal wiring, a signal of the conductive layer is provided by a third CK signal wiring, the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are mutually counteracted, the voltage difference generated between the pixel electrode and the drain electrode is reduced, the parasitic capacitance coupling influence is reduced, the feed through voltage is reduced, and the picture flicker of the liquid crystal display is reduced; when the supplementary capacitance and the parasitic capacitance are equal in size, the feedback voltage is eliminated, and the picture display stability of the liquid crystal display is improved. 2. The conductive layer is arranged at a position close to the contact of the drain electrode and the active layer, and the field intensity of the position is larger, so that the Schottky barrier formed by the contact of the active layer semiconductor and the metal line of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current can be increased. 3. The ITO has good conductivity and light transmittance, and the materials of the pixel electrode, the first electrode block, the second electrode block and the third electrode block are ITO, so that the pixel electrode, the first electrode block, the second electrode block and the third electrode block can be formed into films in the same process, thereby simplifying the substrate structure and improving the productivity. 4. The first hole, the second hole and the third hole are formed in the gate insulating layer in advance, and then the first electrode block, the second electrode block and the third electrode block are respectively filled, so that the influence of subsequent process etching on the metal of the first metal layer is avoided. 5. The conducting layer does not cover the channel of the active layer, but a floating shading metal layer is plated right above the channel of the active layer, so that the shading effect can be achieved, and the stability of the TFT device is improved.

Drawings

The utility model will be further described with reference to examples of embodiments with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of parasitic capacitance existing between a gate and a drain of a TFT device in the background art.

FIG. 2 is a schematic diagram of a common electrode V in an ideal state due to the presence of a feed through voltage in the background art _com Schematic diagram of point location deviation.

Fig. 3 is a schematic design diagram of an array substrate for reducing the influence of parasitic capacitance coupling according to the present utility model.

Fig. 4 is a circuit schematic diagram of a first row of TFT devices of the array substrate of fig. 3.

Fig. 5 is a circuit schematic of a second row of TFT devices of the array substrate of fig. 3.

FIG. 6 is a timing diagram of a first CK signal trace, a second CK signal trace, a third CK signal trace, and a fourth CK signal trace in the present utility model.

Fig. 7 is a schematic top view of an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

FIG. 8 is a flow chart of a manufacturing process of an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 9 is a second flowchart of the fabrication of the array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 10 is a third flowchart of the fabrication of the array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 11 is a flowchart of manufacturing an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 12 is a flowchart of manufacturing an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 13 is a flowchart sixth of the fabrication of the array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 14 is a flow chart seventh for manufacturing the array substrate for reducing the influence of parasitic capacitance coupling.

Fig. 15 is a flowchart eight of manufacturing an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 16 is a flowchart of manufacturing an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Fig. 17 is a flowchart of manufacturing an array substrate for reducing the effect of parasitic capacitance coupling according to the present utility model.

Reference numerals:

a glass substrate 1; a pixel display area 11;

a gate electrode 2;

a first CK signal wiring 31; a second CK signal trace 32; a third CK signal wiring 33; a fourth CK signal trace 34;

a gate insulating layer 4; a first hole 41; a second hole 42; a third hole 43;

a pixel electrode 5; a first electrode block 51; a second electrode block 52; a third electrode block 53;

an active layer 6;

a source electrode 7;

a drain electrode 8;

a first signal connection line 91; right end 911 of the first signal connection line; the left end 912 of the first signal connection line; a second signal connection line 92;

a passivation layer 10; a fourth hole 101;

a conductive layer 20;

a light shielding metal layer 30;

TP trace 40;

an outer insulating layer 50; fifth hole 501;

and a common electrode 60.

Detailed Description

The array substrate capable of reducing the influence of the parasitic capacitance is provided, the defect that the liquid crystal display screen flickers due to the existence of the feed through voltage caused by the influence of the parasitic capacitance in the background technology is overcome, and the technical effects of reducing the influence of the parasitic capacitance, reducing the feed through voltage and stabilizing the liquid crystal display screen are achieved.

The technical scheme in the embodiment of the utility model aims to solve the defects, and the general idea is as follows:

the main improvement of the utility model is that after the passivation layer is plated, a conductive layer is plated on the upper part of the drain electrode, and the conductive layer and the drain electrode form a complementary capacitor C _{Supplement and supplement} Then the potential of the conductive layer is opposite to the potential of the grid electrode of the TFT array substrate at any time. Parasitic capacitance C exists between drain and gate _gd Thus the coupling effect of the grid electrode and the drain electrode is counteracted with the coupling effect of the conductive layer and the drain electrode, namely the parasitic capacitance coupling effect is reduced, thereby reducing the pixel electrode and the drain electrodeThe voltage difference generated between the drain electrodes can reduce the jump of the voltage of the pixel electrode, thereby achieving the purpose of reducing the feed through voltage. The signal of the grid electrode is provided by a first CK signal wiring, the signal of the conductive layer is provided by a third CK signal wiring, and when the capacitor C is supplemented _{Supplement and supplement} And parasitic capacitance C _gd When the magnitudes of the signals are uniform, the feedback voltage caused by the signal change of the grid electrode can be eliminated. The capacitance C can be supplemented by regulating the positive area and the film distance between the conductive layer and the drain electrode _{Supplement and supplement} And parasitic capacitance C _gd Is uniform in size.

The conducting layer does not cover the channel of the active layer, but a floating shading metal layer is plated right above the channel of the active layer, the periphery of the floating shading metal layer, namely the shading metal layer, is spaced, and is not contacted with the conducting layer and the second signal connecting wire around, the shading metal layer plays a shading role, and the stability of the TFT device is improved.

In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.

Referring to fig. 1 to 17, a preferred embodiment of the present utility model.

a glass substrate 1;

a first metal layer plated on the upper surface of the glass substrate 1, forming a gate electrode 2, a first CK signal wire 31 and a third CK signal wire 33 which are distributed at intervals, wherein the potential of the first CK signal wire 31 is opposite to that of the third CK signal wire 33;

a gate insulating layer 4 plated on the upper surfaces of the glass substrate 1 and the first metal layer, wherein a first hole 41, a second hole 42 and a third hole 43 are formed in the gate insulating layer 4, the gate electrode 2 is exposed in the first hole 41, the first CK signal trace 31 is exposed in the second hole 42, and the third CK signal trace 33 is exposed in the third hole 43;

a pixel electrode 5 plated on the upper surface of the gate insulating layer 4 and located at the side of the gate electrode 2;

a first electrode block 51 plated on the first hole 41 and connected to the gate electrode 2;

a second electrode block 52 plated on the second hole 42 and connected to the first CK signal trace 31;

a third electrode block 53 plated on the third hole 43 and connected to the third CK signal trace 33;

the first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5;

the active layer 6 is plated on the upper surface of the insulating layer of the grid electrode 2 and is also positioned right above the grid electrode 2;

a second metal layer plated on the upper surface of the gate insulating layer 4 to form source electrodes 7, drain electrodes 8 and first signal connection lines 91 which are distributed at intervals, wherein the source electrodes 7 are connected with the left end of the active layer 6, the drain electrodes 8 are connected with the right end of the active layer 6, the drain electrodes 8 are also connected with the pixel electrodes 5, the right ends 911 of the first signal connection lines are connected with the first electrode blocks 51, and the left ends 912 of the first signal connection lines are connected with the second electrode blocks 52;

a passivation layer 10 plated on the upper surfaces of the gate insulating layer 4, the active layer 6, the second metal layer, and the pixel electrode 5, wherein a fourth hole 101 is formed in the passivation layer 10, and the third electrode block 53 is exposed from the fourth hole 101;

the conductive layer 20 is plated on the upper surface of the passivation layer 10 and is also positioned right above the drain electrode 8, the upper surface of the passivation layer 10 is also plated with a second signal connecting wire 92, the conductive layer 20 is connected with the right end of the second signal connecting wire 92, and the left end of the second signal connecting wire 92 passes through the fourth hole 101 to be connected with the third electrode block 53;

a light shielding metal layer 30 plated on the upper surface of the passivation layer 10 and located right above the channel of the active layer 6, wherein the light shielding metal layer 30 is spaced from the conductive layer 20 and the second signal connection line 92;

the light shielding metal layer 30 and the conductive layer 20 are made of the same material as the first metal layer.

In the utility model, the conductive layer 20 is arranged above the drain electrode 8, a complementary capacitance is formed between the conductive layer 20 and the drain electrode 8, the signal of the grid electrode 2 is provided by the first CK signal wiring 31, the signal of the conductive layer 20 is provided by the third CK signal wiring 33, the potential of the conductive layer 20 is opposite to that of the grid electrode 2, the coupling effect of the grid electrode 2 on the drain electrode 8 and the coupling effect of the conductive layer 20 on the drain electrode 8 are mutually counteracted, the parasitic capacitance coupling effect is reduced, the voltage difference generated between the pixel electrode 5 and the drain electrode 8 is reduced, the feed through voltage is reduced, and the picture flicker of the liquid crystal display is reduced; when the supplementary capacitance and the parasitic capacitance are equal in size, the feedback voltage is eliminated, and the picture display stability of the liquid crystal display is improved; effectively prevent V of the common electrode 60 in an ideal state _com The point position deviates from the center position of the actually provided positive and negative deflection voltages; the voltage values at two ends of the liquid crystal in the positive and negative polarity states are kept the same, and the deflection angles of the liquid crystal in the positive and negative polarities are the same, so that the light quantity of the array substrate is the same, and the picture of the liquid crystal display is stable.

The conductive layer 20 is disposed near the position where the drain electrode 8 contacts the active layer 6, and the field strength of the position is larger, so that the schottky barrier formed by the contact of the semiconductor of the active layer 6 and the metal line of the drain electrode 8 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

By pre-opening the first hole 41, the second hole 42 and the third hole 43 in the gate insulating layer 4 and then filling the first electrode block 51, the second electrode block 52 and the third electrode block 53 respectively, the influence of the subsequent process etching on the metal of the first metal layer is avoided. The first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5, so that the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed into films in the same process, the substrate structure is simplified, the productivity is improved, and the cost is reduced. When the passivation layer 10 etches the fourth hole 101, the third electrode block 53 is exposed from the fourth hole 101, and thus the third CK signal trace 33 is not etched, and the outermost metal of the third CK signal trace 33 located in the first metal layer is prevented from being damaged.

The conductive layer 20 does not cover the channel of the active layer 6, but a floating light shielding metal layer 30 is plated right above the channel of the active layer 6, and the floating light shielding metal layer, namely, the periphery of the light shielding metal layer is spaced and is not contacted with the surrounding conductive layer 20 and the second signal connection line 92, and the light shielding metal layer 30 plays a role in shielding light, so that the stability of the TFT device is improved.

Further comprises: the second metal layer also forms TP traces 40 that are spaced apart;

an outer insulating layer 50 plated on the upper surfaces of the conductive layer 20, the light shielding metal layer 30 and the passivation layer 10, wherein a fifth hole 501 is formed in the outer insulating layer 50, the fifth hole 501 penetrates through the passivation layer 10, and the TP trace 40 is exposed out of the fifth hole 501;

and a common electrode 60 plated on the upper surface of the outer insulation layer 50, wherein the common electrode 60 is further connected to the TP wiring 40 through the fifth hole 501. One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 5, and the other end is connected to the common electrode 60. The full name of TP wiring is Touch Panel Senser Line; the TP trace provides a voltage signal to the common electrode.

The first metal layer, the second metal layer, the conductive layer 20, the second signal connection line 92, and the light shielding metal layer 30 are all Ti/AL/Ti three-layer structures or MO/AL/MO three-layer structures.

The gate insulating layer 4 is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer 10 is of SiO ₂ The outer insulating layer 50 is made of SiOx, siNO, or SiNx.

The active layer 6 is made of IGZO, and the pixel electrode 5, the first electrode block 51, the second electrode block 52, the third electrode block 53 and the common electrode 60 are made of ITO. The ITO has good conductivity and light transmittance, and the materials of the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are ITO, so that the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed into films in the same process, thereby simplifying the substrate structure and improving the productivity.

The first metal layer further forms a second CK signal trace 32 and a fourth CK signal trace 34 that are distributed at intervals, and the potential of the second CK signal trace 32 is opposite to that of the fourth CK signal trace 34;

the first CK signal wire (CK 1) is connected with the grid electrode of the array substrate of the first row, the second CK signal wire (CK 2) is connected with the grid electrode of the array substrate of the second row, the third CK signal wire (CK 3) is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal wire (CK 4) is connected with the conductive layer of the array substrate of the fourth row.

For the first row of the array substrate, a first hole 41 is formed in the position of the grid electrode 2 of the first row, a second hole 42 is formed in the position of the first CK signal wire 31, a third hole 43 is formed in the position of the third CK signal wire 33, and the first row of the array substrate is provided with a first signal connecting wire 91 and a second signal connecting wire 92; for the second row of the array substrate, the first hole 41 is formed at the position of the second row gate 2, the second hole 42 is formed at the position of the second CK signal trace 32, the third hole 43 is formed at the position of the fourth CK signal trace 34, and the second row of the array substrate also has the first signal connection line 91 and the second signal connection line 92.

The signal timing phase of the first CK signal trace 31 is one quarter cycle earlier than the signal timing phase of the second CK signal trace 32, and the signal timing phase of the third CK signal trace 33 is one quarter cycle earlier than the signal timing phase of the fourth CK signal trace 34. When the first CK signal wiring 31 drives the gate electrode 2 of the first row TFT device to a high potential, the source electrode 7 and the drain electrode 8 of the first row TFT device are turned on, a data voltage signal is written to the pixel electrode 5, after a quarter period of time, the second CK signal wiring 32 drives the gate electrode 2 of the second row TFT device to a high potential, the source electrode 7 and the drain electrode 8 of the second row TFT device are turned on, and a data voltage signal is written to the pixel electrode 5. When the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, and when the first CK signal wiring 31 is at a low potential, the third CK signal wiring 33 is at a high potential; the potential of the second CK signal wiring 32 is the same as that of the fourth CK signal wiring 34. The array substrate causes the display screen to be sequentially lighted from top to bottom or bottom to top of the pixels of one row under the control of the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34. For example, when the first CK signal trace is 10V, the third CK signal trace is-15V; when the first CK signal trace is-15V, the third CK signal trace is 10V.

And a driving IC connected to the first, second, third, and fourth CK signal wirings 31, 32, 33, and 34. The driving ICs are used to give different timing signals to the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34.

The utility model reduces the working principle of the array substrate of parasitic capacitance coupling influence:

in this embodiment, the design of the single-side level 4CK is taken as an example (note that the circuit design of the present utility model is not limited to the single-side level 4CK, but may be double-side level), the timing chart is shown in fig. 5, and fig. 4 is a circuit diagram of all pixels in the first row in fig. 3. In short, the display of the picture is realized by sequentially lighting pixels of a row from top to bottom or from bottom to top. The pixel needs to be lightened, the grid electrode 2 corresponding to the pixel TFT device in the row is at a high potential, then the TFT device is turned on, and a data signal can be written into the pixel electrode 5, so that the liquid crystal is controlled to twist, and the pixel is lightened. Taking the first row of pixels as an example, when the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, the high potential of the first CK signal wiring 31 is transferred to the first row of gates 2, the TFT devices of the first row are turned on, the pixel electrode 5 is signal-written, and the low potential of the third CK signal wiring 33 is transferred to the conductive layer 20 of the first row; when the first CK signal trace 31 is switched to low, the third CK signal trace 33 is switched to high, the gate 2 is switched from high to low, and the parasitic capacitance formed by the gate 2 and the drain 8 will have a coupling effect, so as to pull down the voltage of the drain 8, but since the third CK signal trace 33 is switched from low to high, i.e. the conductive layer 20 of the first row is switched from low to high, the complementary capacitance formed by the conductive layer 20 and the drain 8 will have a coupling effect, so as to pull up the drain voltage, so that the drain voltage will not change due to the jump of the gate, that is, the voltage of the pixel electrode will not change. Note that here the design requires that the C-complement is equal in magnitude to Cgd, the purpose of this design being such that there are two feedthru voltages one by one and two in magnitude at the drain 8. Similarly, the TFT devices of each row can avoid the Feedthrough voltage caused by the production jump of the gate 2.

At the microscopic level, it is the migration of charges between the drain electrode 8 and the pixel electrode 5 that causes a change in the amount of charges stored on the pixel electrode 5 and thus a change in voltage. After the pixel electrode 5 is charged, the electric potential between the drain electrode 8 and the pixel electrode 5 is equal, and no electron transfer occurs between them, but since the voltage of the gate electrode 2 is switched from a high potential to a low potential at this moment, the change is coupled to the drain electrode 8 through the parasitic capacitance formed by the gate electrode 2 and the drain electrode 8, and a voltage difference is generated between the drain electrode 8 and the pixel electrode 5, so that the electric charge transfer occurs between the drain electrode 8 and the pixel electrode 5, and the pixel electrode 5 is changed. The utility model solves the problem by adding a conductive layer 20, the conductive layer 20 and the drain electrode 8 form a complementary capacitor C for supplementing, and then the first CK signal wiring 31 and the third CK signal wiring 33 respectively give opposite potential signals to the grid electrode 2 and the conductive layer 20, so that the coupling effect of parasitic capacitance and complementary capacitance is counteracted, and the working performance of the device is improved.

A manufacturing method of an array substrate for reducing parasitic capacitance coupling influence comprises the following steps:

s1, referring to FIG. 8, a first metal layer is plated on the upper surface of a glass substrate 1 to form a grid electrode 2, a first CK signal wire 31, a second CK signal wire 32, a third CK signal wire 33 and a fourth CK signal wire 34 which are distributed at intervals, wherein the potential of the first CK signal wire is opposite to that of the third CK signal wire, and the potential of the second CK signal wire 32 is opposite to that of the fourth CK signal wire 34;

the gate 2 is used for turning on and off the TFT device, the first CK signal trace 311 is used for transmitting a first row gate 2 signal, the second CK signal trace 32 is used for transmitting a second row gate signal, the third CK signal trace 33 is used for transmitting a first row conductive layer 20 signal, and the fourth CK signal trace 34 is used for transmitting a second row conductive layer signal; the material of the first metal layer may be selected from MO/AL/MO stack, ti/AL/Ti stack, AL/MO stack (MO as top layer), AL/Ti stack (Ti as top layer), etc., and PVD is performed. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, by using the small expansion coefficient of MO or Ti, the deformation of AL in a high-temperature process can be restrained, and the oxidation of AL can be prevented.

S2, referring to FIG. 9, plating a gate insulating layer 4 on the upper surfaces of the glass substrate 1 and the first metal layer;

the insulating layer of the gate electrode 2 is used as an insulating medium and is also a capacitance medium between the gate electrode 2 and the active layer 6, and the material is formed by using SiOx single layer or SiNx/SiOx double layer in a CVD mode. Considering that the requirements of TFT devices at present are fast reaction and low power consumption, and these are all achieved by shrinking TFT devices, and in order to achieve miniaturization of the devices, a suitable high-K material (such as HfO 2) needs to be selected for the gate insulating layer 4, but considering that the interface of HfO2 has more defects, if the interface is directly contacted with the active layer 6 or the gate 2 metal, the stability of the devices may be affected, so that SiOx or SiNx with a relatively good interface may be considered (SiNx can only be used as a contact film layer with the gate metal layer, if as a contact surface with IGZO, H remained in the SiNx film layer during film forming may destroy IGZO characteristics) serving as a contact surface, such as SiOx/HfO2/SiOx three-layer structure needs to be relatively larger in thickness of the SiOx three-layer structure in order to ensure that the advantage of representing the high-K material is guaranteed.

S3, referring to FIG. 10, a first hole 41, a second hole 42 and a third hole 43 are formed in the gate insulating layer 4, the gate 2 is exposed out of the first hole 41, the first CK signal wire 31 is exposed out of the second hole 42, and the third CK signal wire 33 is exposed out of the third hole 43;

for the first row of the array substrate, a first hole is formed in the position of the grid electrode of the first row, a second hole 42 is formed in the position of the first CK signal wire 31, and a third hole 43 is formed in the position of the third CK signal wire 33; for the second row of the array substrate, a first hole is formed at the position of the second row gate, a second hole 42 is formed at the position of the second CK signal trace 32, and a third hole 43 is formed at the position of the fourth CK signal trace 34. The first hole 41, the second hole 42 and the third hole 43 are located outside the pixel display area 11.

The dry etching digs out the first hole 41, the second hole 42 and the third hole 43, the first hole 41 and the second hole 42 function to provide a junction of the first CK signal trace 31 (or the second CK signal trace 32), the first signal connection line 91 and the gate 2, and the third hole 43 functions to provide a junction of the third CK signal trace 33 (or the fourth CK signal trace 34) and the second signal connection line 92.

S4, referring to FIG. 11, plating a pixel electrode 5 on the upper surface of the gate insulating layer 4, wherein the pixel electrode 5 is also positioned at the side of the gate electrode 2;

plating a first electrode block 51, a second electrode block 52 and a third electrode block 53 on the first hole 41, the second hole 42 and the third hole 43 respectively, wherein the first electrode block 51 is connected with the grid 2, the second electrode block 52 is connected with the first CK signal wire 31, and the third electrode block 53 is connected with the third CK signal wire 33;

the materials of the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are all selected to be ITO, mainly because ITO has good conductivity and light transmittance, PVD film formation and acid wet etching. By pre-opening the first hole 41, the second hole 42 and the third hole 43 in the gate insulating layer 4 and then filling the first electrode block 51, the second electrode block 52 and the third electrode block 53 respectively, the influence of the subsequent process etching on the metal of the first metal layer is avoided.

S5, referring to FIG. 12, plating an active layer 6 on the upper surface of the gate insulating layer 4, wherein the active layer 6 is positioned right above the grid electrode 2; the active layer 6 is in the plane of the pixel display area 11.

The material of the active layer 6 is selected from metal oxide semiconductors such as IGZO, and PVD is performed by wet etching.

S6, referring to FIG. 13, a second metal layer is plated on the upper surface of the gate insulating layer 4 to form source electrodes 7 and drain electrodes 8 which are distributed at intervals and a first signal connection line 91, wherein the source electrodes 7 are connected with the left end of the active layer 6, the drain electrodes 8 are connected with the right end of the active layer 6, the drain electrodes 8 are also connected with the pixel electrodes 5, the right ends 911 of the first signal connection line are connected with the first electrode block 51, and the left ends 912 of the first signal connection line are connected with the second electrode block 52; the source electrode 7 and the drain electrode 8 are both in the plane of the pixel display area 11.

The material of the second metal layer can be selected from MO/AL/MO three-layer structure, ti/AL/Ti three-layer structure, PVD film forming and acid liquid wet etching. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, the expansion coefficient of the outer metal MO or Ti is smaller, so that the deformation of the AL in a high-temperature process can be restrained, and the oxidation of the AL can be prevented.

S7, referring to FIG. 14, plating a passivation layer 10 on the upper surfaces of the gate insulating layer 4, the active layer 6, the second metal layer and the pixel electrode 5;

etching a fourth hole 101 in the passivation layer 10, wherein the third electrode block 53 is exposed out of the fourth hole 101; the fourth hole is outside the pixel display area.

The material of the passivation layer 10 is selected to be SiO ₂ CVD film formation, dry etching digs out the fourth dig hole 101. The fourth hole 101 serves to provide a junction between the third CK signal trace 33 and the conductive layer 20. Since the gate insulating layer 4 under the position of the fourth hole 101 has been dug into the third hole 43 in step S3 and is covered with ITO having excellent conductivity, etching is stopped after the third electrode block 53 is exposed when the fourth hole 101 is dug out, so that the third CK signal wiring 33 is not etched, the internal metal line (AL) exposed to the air due to the absence of the outer protective metal (MO or Ti) of the third CK signal wiring 33 is prevented from being oxidized, the contact resistance is increased, and the likeThe questions are given.

S8, referring to FIG. 15, plating a conductive layer 20 and a second signal connection line 92 and plating a shading metal layer 30 on the upper surface of the passivation layer 10, wherein the conductive layer 20 is further located right above the drain electrode 8, the conductive layer is connected with the right end of the second signal connection line 92, the left end of the second signal connection line 92 passes through the fourth hole 101 and is connected with the third electrode block 53, the shading metal layer 30 is further located right above the channel of the active layer 6, and the shading metal layer 30 is spaced from the conductive layer 20 and the second signal connection line 92;

The materials of the conductive layer 20 and the light shielding metal layer 30 may be MO/AL/MO three-layer structure, ti/AL/Ti three-layer structure, AL/MO double-layer structure (MO as top layer), AL/Ti double-layer structure (Ti as top layer), or the like, and PVD film formation is performed. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, by using the small expansion coefficient of MO or Ti, the deformation of AL in a high-temperature process can be restrained, and the oxidation of AL can be prevented. The conductive layer 20 is required to be designed right above the drain electrode 8, so that a capacitance structure, namely a complementary capacitance, is formed with the drain electrode 8, and the capacitance of the complementary capacitance is consistent with the capacitance of parasitic capacitance formed by the gate electrode 2 and the drain electrode 8, and the positive area and the film layer distance of the conductive layer 20 can be regulated and controlled to be equal. The light shielding metal layer 30 is arranged right above the channel of the active layer 6, floats, is not contacted with the conductive layer 20 and the second signal connection line 92, can play a role of light shielding, and improves the stability of the TFT device.

As shown in fig. 7, the conductive layer 20 and the second signal connection line 9292 do not cover the channel to the active layer 6; the voltage signals of the conductive layer 20 and the second signal connection line 9292 are prevented from interfering with the channel of the active layer 6, and the operation stability of the active layer is ensured.

Further comprises: in S6, the second metal layer further forms TP traces 40 distributed at intervals;

s9, referring to FIG. 16, plating an outer insulating layer 50 on the upper surfaces of the conductive layer 20, the light shielding metal layer 30 and the passivation layer 10, wherein a fifth hole 501 is etched in the outer insulating layer 50, the fifth hole 501 penetrates through the passivation layer 10, and the TP wire 40 is exposed out of the fifth hole;

the material of the outer insulating layer 50 may be SiOx, siNO, siNx or the like, and is formed by CVD. A fifth hole 501 is obtained by dry etching through the insulating layer and the passivation layer 10 until the TP trace 40 is exposed, the fifth hole 501 being provided for the purpose of providing a connection of the common electrode 60 and the TP trace 40.

S10, referring to fig. 17, a common electrode 60 is plated on the upper surface of the outer insulating layer 50, and the common electrode 60 is further connected to the TP trace 40 through the fifth hole 501.

The material of the common electrode 60 is selected to be ITO mainly because ITO has good conductivity and light transmittance, PVD film formation, acid wet etching.

While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the utility model, and that equivalent modifications and variations of the utility model in light of the spirit of the utility model will be covered by the claims of the present utility model.

Claims

1. An array substrate for reducing the effect of parasitic capacitance coupling, comprising:

a glass substrate;

2. The array substrate for reducing the effect of parasitic capacitance coupling of claim 1, further comprising:

3. The array substrate for reducing the effect of parasitic capacitance coupling of claim 2, wherein the first metal layer, the second metal layer, the conductive layer, the second signal connection line, and the light shielding metal layer are all Ti/AL/Ti three-layer structure or MO/AL/MO three-layer structure.

4. The array substrate for reducing parasitic capacitance coupling effect according to claim 2, wherein the gate insulating layer is a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer is SiO ₂ The outer insulating layer is made of SiOx, siNO or SiNx.

5. The array substrate for reducing the influence of parasitic capacitance coupling as claimed in claim 2, wherein the active layer is IGZO material, and the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO material.

6. The array substrate for reducing the influence of parasitic capacitance coupling according to claim 1, wherein the first metal layer further forms second and fourth CK signal wirings which are spaced apart, and the potential of the second CK signal wiring is opposite to the potential of the fourth CK signal wiring;

7. The array substrate of claim 6, wherein the signal timing phase of the first CK signal trace is one-quarter cycle earlier than the signal timing phase of the second CK signal trace, and the signal timing phase of the third CK signal trace is one-quarter cycle earlier than the signal timing phase of the fourth CK signal trace.