CN116153942A - Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof - Google Patents
Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof Download PDFInfo
- Publication number
- CN116153942A CN116153942A CN202310082142.6A CN202310082142A CN116153942A CN 116153942 A CN116153942 A CN 116153942A CN 202310082142 A CN202310082142 A CN 202310082142A CN 116153942 A CN116153942 A CN 116153942A
- Authority
- CN
- China
- Prior art keywords
- electrode
- signal
- layer
- hole
- electrode block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000002184 metal Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 238000002161 passivation Methods 0.000 claims abstract description 40
- 239000011521 glass Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 273
- 239000000463 material Substances 0.000 claims description 23
- 238000007747 plating Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910004205 SiNX Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- 230000001808 coupling effect Effects 0.000 abstract description 13
- 230000008901 benefit Effects 0.000 abstract description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 21
- 230000003071 parasitic effect Effects 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 239000013589 supplement Substances 0.000 description 10
- 230000008859 change Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000000295 complement effect Effects 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000000153 supplemental effect Effects 0.000 description 2
- 101001077374 Oryza sativa subsp. japonica UMP-CMP kinase 3 Proteins 0.000 description 1
- 101001077376 Oryza sativa subsp. japonica UMP-CMP kinase 4 Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention relates to the technical field of displays, and provides an array substrate for maintaining the potential level of a pixel electrode, which comprises the following components: a glass substrate; a first metal layer plated on the upper surface of the glass substrate to form a grid electrode, a first CK signal wiring and a third CK signal wiring which are distributed at intervals; a gate insulating layer plated on upper surfaces of the glass substrate and the first metal layer; a pixel electrode plated on an upper surface of the gate insulating layer; a first electrode block; a second electrode block; a third electrode block; an active layer plated on an upper surface of the gate insulating layer; the second metal layer is plated on the upper surface of the gate insulating layer, and source electrodes, drain electrodes and first signal connecting lines which are distributed at intervals are formed; and the conducting layer is plated on the upper surface of the passivation layer. The invention has the advantages that: the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, and the feedback voltage is reduced.
Description
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate for maintaining the potential level of a pixel electrode and a manufacturing method thereof.
Background
In the case of a TFT-LCD display, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is generally called the parasitic capacitance C gd . The grid electrode of the TFT device is connected with the grid lines which are transversely distributed and used for controlling the on-off of the TFT device; source and longitudinal distribution of TFT deviceThe data line is connected and used for writing data voltage to be displayed into the TFT device; when the TFT is turned on, the source electrode is conducted with the drain electrode, the data voltage enters the drain electrode and reaches the liquid crystal capacitor Cst from the pixel electrode, and the light transmittance of the liquid crystal is adjusted; when the TFT is turned off, the source and drain are turned off, and the data voltage of the source cannot enter the drain. The data voltage of the source electrode changes in positive and negative polarities periodically, and is a deflection voltage for making the liquid crystal generate positive and negative polarities.
Referring to fig. 1 and 2, at the instant of TFT off, the gate voltage V g V from high level high V instantaneously dropping to low level low Due to parasitic capacitance C gd The presence of (C) will be V g The transient change of (a) is coupled to the drain electrode, resulting in a drop in the drain voltage, and the voltage difference between the pixel electrode and the drain electrode may cause a jump in the voltage of the pixel electrode, which is referred to as the feedback voltage. In the waveform diagram of FIG. 2, V g Is the gate voltage, V d Is the drain voltage in an ideal state,
is the center point of the actually supplied common electrode voltage, i.e. the actually supplied positive and negative deflection voltages, V p (t) is the actual pixel electrode voltage, V com Is the common electrode voltage in the ideal state of keeping the same voltage at both ends of the liquid crystal in the positive and negative polarity state, V offset Is the deviation of the ideal common electrode voltage from the actually supplied common electrode voltage, tf is the switching period of the TFT device, V lc ＞V com Is the region where the pixel electrode voltage is greater than the common electrode voltage in the current ideal state, V lc ＜V com Is a region where the pixel electrode voltage is less than the common electrode voltage of the current ideal state.
As shown in FIG. 2, the existence of the feed through voltage results in an ideal state of the common electrode V com The point position deviates from the center position of the actually provided positive and negative deflection voltages, i.e. the common electrode voltage in an ideal state changes, but the actually provided positive and negative deflection voltages are unchangedThis causes the voltages at both ends of the liquid crystal in the positive and negative polarities to be different, which causes the deflection angle of the liquid crystal in the positive and negative polarities to be different, so that the light quantity of the array substrate is different, and the flicker of the liquid crystal display screen is caused. Reducing the Feedthrough voltage is a problem that should be solved at present.
Disclosure of Invention
The invention aims to solve the technical problem of providing an array substrate for maintaining the potential level of a pixel electrode and a manufacturing method thereof, wherein a conductive layer is arranged above a drain electrode, the potential of the conductive layer is opposite to that of a grid electrode, and the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, so that the feed through voltage is reduced, and the potential level of the pixel electrode is maintained.
The invention is realized in the following way:
an array substrate for maintaining a potential level of a pixel electrode, comprising:
a glass substrate;
a first metal layer plated on the upper surface of the glass substrate to form grid electrodes, a first CK signal wiring and a third CK signal wiring which are distributed at intervals, wherein the potential of the first CK signal wiring is opposite to that of the third CK signal wiring;
the gate insulating layer is plated on the upper surfaces of the glass substrate and the first metal layer, a first hole, a second hole and a third hole are formed in the gate insulating layer, the gate is exposed out of the first hole, the first CK signal wire is exposed out of the second hole, and the third CK signal wire is exposed out of the third hole;
The pixel electrode is plated on the upper surface of the gate insulating layer and is also positioned at the side of the grid electrode;
the first electrode block is plated on the first hole and is also connected with the grid electrode;
the second electrode block is plated on the second hole and is also connected with the first CK signal wiring;
the third electrode block is plated on the third hole and is also connected with the third CK signal wiring;
the first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;
the active layer is plated on the upper surface of the grid insulation layer and is also positioned right above the grid;
the second metal layer is plated on the upper surface of the gate insulating layer, source electrodes, drain electrodes and first signal connecting wires which are distributed at intervals are formed, the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the drain electrodes are also connected with the pixel electrodes, the right end of the first signal connecting wire is connected with the first electrode block, and the left end of the first signal connecting wire is connected with the second electrode block;
the passivation layer is plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode, a fourth hole is formed in the passivation layer, and the third electrode block is exposed out of the fourth hole;
The conducting layer is plated on the upper surface of the passivation layer and is further positioned right above the drain electrode, a second signal connecting wire is plated on the upper surface of the passivation layer, the conducting layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire penetrates through the fourth hole to be connected with the third electrode block.
Further, the method further comprises the following steps:
the second metal layer also forms TP wirings which are distributed at intervals;
the passivation layer is also provided with a fifth hole, and the TP wiring is exposed out of the fifth hole;
and the public electrode is plated on the upper surface of the passivation layer, and a lead of the public electrode also passes through the fifth hole to be connected with the TP wiring.
Further, the first metal layer and the second metal layer are both of a Ti/AL/Ti three-layer structure or an MO/AL/MO three-layer structure.
Further, the gate insulating layer is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer is of SiO 2 The outer insulating layer is made of SiOx, siNO or SiNx.
Further, the active layer is made of an IGZO material, and the conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are made of an ITO material.
Further, the first metal layer further forms second CK signal wires and fourth CK signal wires which are distributed at intervals, and the potential of the second CK signal wires is opposite to that of the fourth CK signal wires;
the first CK signal wire is connected with the grid electrode of the array substrate of the first row, the second CK signal wire is connected with the grid electrode of the array substrate of the second row, the third CK signal wire is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal wire is connected with the conductive layer of the array substrate of the fourth row.
Further, the signal timing phase of the first CK signal trace is one quarter cycle earlier than the signal timing phase of the second CK signal trace, and the signal timing phase of the third CK signal trace is one quarter cycle earlier than the signal timing phase of the fourth CK signal trace.
A manufacturing method of an array substrate for maintaining the potential level of a pixel electrode comprises the following steps:
s1, plating a first metal layer on the upper surface of a glass substrate to form grid electrodes, first CK signal wires and third CK signal wires which are distributed at intervals, wherein the potential of the first CK signal wires is opposite to that of the third CK signal wires;
S2, plating a gate insulating layer on the upper surfaces of the glass substrate and the first metal layer;
s3, a first hole, a second hole and a third hole are formed in the gate insulating layer, the grid electrode is exposed out of the first hole, the first CK signal wire is exposed out of the second hole, and the third CK signal wire is exposed out of the third hole;
s4, plating a pixel electrode on the upper surface of the gate insulating layer, wherein the pixel electrode is also positioned at the side of the gate electrode;
plating a first electrode block, a second electrode block and a third electrode block on the first hole, the second hole and the third hole respectively, wherein the first electrode block is connected with the grid, the second electrode block is connected with the first CK signal wire, and the third electrode block is connected with the third CK signal wire;
the first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;
s5, plating an active layer on the upper surface of the gate insulating layer, wherein the active layer is positioned right above the gate electrode;
s6, plating a second metal layer on the upper surface of the gate insulating layer to form source electrodes, drain electrodes and first signal connecting lines which are distributed at intervals, wherein the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the drain electrodes are also connected with the pixel electrodes, the right end of the first signal connecting line is connected with the first electrode block, and the left end of the first signal connecting line is connected with the second electrode block;
S7, plating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode;
a fourth hole is formed in the passivation layer, and the third electrode block is exposed out of the fourth hole;
s8, plating a conductive layer and a second signal connecting wire on the upper surface of the passivation layer, wherein the conductive layer is further positioned right above the drain electrode, the conductive layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire penetrates through the fourth hole to be connected with the third electrode block.
Further, the method further comprises the following steps:
in the step S6, the second metal layer further forms TP traces distributed at intervals;
in the step S7, etching a fourth hole and a fifth hole on the passivation layer at the same time, wherein the TP wiring is exposed out of the fifth hole;
in the step S8, a conducting layer, a second signal connecting wire and a common electrode are plated on the upper surface of the passivation layer at the same time, and a lead of the common electrode is connected with the TP wiring through the fifth hole.
Further, the conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO materials.
The invention has the advantages that: 1. a conductive layer is arranged above the drain electrode, a complementary capacitor is formed between the conductive layer and the drain electrode, a signal of the grid electrode is provided by a first CK signal wiring, a signal of the conductive layer is provided by a third CK signal wiring, the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually counteracted, the voltage difference generated between the pixel electrode and the drain electrode is reduced, so that the Feedthrough voltage is reduced, the potential level of the pixel electrode is maintained, and the picture flicker of the liquid crystal display is reduced; when the supplementary capacitance and the parasitic capacitance are equal in size, the feedback voltage is eliminated, and the picture display stability of the liquid crystal display is improved. 2. Under the control of the first CK signal wiring, the second CK signal wiring, the third CK signal wiring and the fourth CK signal wiring, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are turned on and off successively, so that the first row of pixels and the second row of pixels of the display screen are set to brightness successively, and the liquid crystal display screen displays stably row by row. 3. The conductive layer is arranged at a position close to the contact of the drain electrode and the active layer, and the field intensity of the position is larger, so that the Schottky barrier formed by the contact of the active layer semiconductor and the metal line of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current can be increased. 4. The ITO has good conductivity and light transmittance, and the materials of the pixel electrode, the first electrode block, the second electrode block and the third electrode block are ITO, so that the pixel electrode, the first electrode block, the second electrode block and the third electrode block can be formed into films in the same process. 5. The first hole, the second hole and the third hole are formed in the gate insulating layer in advance, and then the first electrode block, the second electrode block and the third electrode block are respectively filled, so that the influence of subsequent process etching on the metal of the first metal layer is avoided.
Drawings
The invention will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of parasitic capacitance existing between a gate and a drain of a TFT device in the background art.
FIG. 2 is a schematic diagram of a common electrode V in an ideal state due to the presence of a feed through voltage in the background art com Schematic diagram of point location deviation.
FIG. 3 is a schematic diagram of an array substrate for maintaining the potential level of a pixel electrode according to the present invention.
Fig. 4 is a circuit schematic diagram of a first row of TFT devices of the array substrate of fig. 3.
Fig. 5 is a circuit schematic of a second row of TFT devices of the array substrate of fig. 3.
FIG. 6 is a timing diagram of a first CK signal trace, a second CK signal trace, a third CK signal trace, and a fourth CK signal trace in the present invention.
FIG. 7 is a schematic top view of an array substrate for maintaining the pixel electrode potential level according to the present invention.
FIG. 8 is a flow chart of a manufacturing process of an array substrate for maintaining the potential level of a pixel electrode according to the present invention.
FIG. 9 is a second flowchart of the fabrication of the array substrate for maintaining the pixel electrode potential level according to the present invention.
FIG. 10 is a flowchart of a manufacturing process of an array substrate for maintaining the pixel electrode potential level according to the present invention.
FIG. 11 is a flowchart of a manufacturing process of an array substrate for maintaining the pixel electrode potential level according to the present invention.
FIG. 12 is a flowchart of a manufacturing process of an array substrate for maintaining the pixel electrode potential level according to the present invention.
FIG. 13 is a flowchart of a manufacturing process of an array substrate for maintaining the pixel electrode potential level according to the present invention.
Fig. 14 is a flow chart of the manufacturing process of the array substrate for maintaining the potential level of the pixel electrode according to the present invention.
FIG. 15 is a flowchart eight of a method for fabricating an array substrate for maintaining the pixel electrode potential level according to the present invention.
Reference numerals:
a glass substrate 1; a pixel display area 11;
a gate electrode 2;
a first CK signal wiring 31; a second CK signal trace 32; a third CK signal wiring 33; a fourth CK signal trace 34;
a gate insulating layer 4; a first hole 41; a second hole 42; a third hole 43;
a pixel electrode 5; a first electrode block 51; a second electrode block 52; a third electrode block 53;
an active layer 6;
a source electrode 7;
a drain electrode 8;
a first signal connection line 91; right end 911 of the first signal connection line; the left end 912 of the first signal connection line; a second signal connection line 92;
a passivation layer 10; a fourth hole 101; fifth hole 102;
a conductive layer 20;
and a common electrode 40.
Detailed Description
The embodiment of the invention solves the problem of flicker of a liquid crystal display picture caused by the existence of a feed through voltage in the background technology by providing the array substrate for maintaining the potential level of the pixel electrode and the manufacturing method thereof, and achieves the technical effects of reducing the feed through voltage, maintaining the potential level of the pixel electrode and stabilizing the liquid crystal display picture.
The technical scheme in the embodiment of the invention aims to solve the defects, and the general idea is as follows:
the main improvement of the invention is that after the passivation layer is plated, a conductive layer is plated on the upper part of the drain electrode, and the conductive layer and the drain electrode form a complementary capacitor C Supplement and supplement Then the potential of the conductive layer is opposite to the potential of the grid electrode of the TFT array substrate at any time. Parasitic capacitance C exists between drain and gate gd So that the coupling effect of the grid electrode and the drain electrode is equal to that of the conductive layerThe coupling effects of the drain electrodes are mutually offset, so that the voltage difference generated between the pixel electrode and the drain electrode is reduced, the voltage jump of the pixel electrode is reduced, and the purpose of reducing the feed through voltage is achieved. The signal of the grid electrode is provided by a first CK signal wiring, the signal of the conductive layer is provided by a third CK signal wiring, and when the capacitor C is supplemented Supplement and supplement And parasitic capacitance C gd When the magnitudes of the signals are uniform, the feedback voltage caused by the signal change of the grid electrode can be eliminated. The capacitance C can be supplemented by regulating the positive area and the film distance between the conductive layer and the drain electrode Supplement and supplement And parasitic capacitance C gd Is uniform in size.
The first hole, the second hole and the third hole are formed in the gate insulating layer in advance, then the first electrode block, the second electrode block and the third electrode block are filled respectively, the influence of subsequent process etching on the metal of the first metal layer is avoided, signals of the first CK signal wiring sequentially pass through the second electrode block, the first signal connecting wire and the first electrode block to reach the grid, and signals of the third CK signal wiring sequentially pass through the third electrode block and the second signal connecting wire to reach the conducting layer.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
Referring to fig. 1 to 15, a preferred embodiment of the present invention.
An array substrate for maintaining a potential level of a pixel electrode, comprising:
a glass substrate 1;
a first metal layer plated on the upper surface of the glass substrate 1, forming a gate electrode 2, a first CK signal wire 31 and a third CK signal wire 33 which are distributed at intervals, wherein the potential of the first CK signal wire 31 is opposite to that of the third CK signal wire 33;
a gate insulating layer 4 plated on the upper surfaces of the glass substrate 1 and the first metal layer, wherein a first hole 41, a second hole 42 and a third hole 43 are formed in the gate insulating layer 4, the gate electrode 2 is exposed in the first hole 41, the first CK signal trace 31 is exposed in the second hole 42, and the third CK signal trace 33 is exposed in the third hole 43;
a pixel electrode 5 plated on the upper surface of the gate insulating layer 4 and located at the side of the gate electrode 2;
a first electrode block 51 plated on the first hole 41 and connected to the gate electrode 2;
a second electrode block 52 plated on the second hole 42 and connected to the first CK signal trace 31;
A third electrode block 53 plated on the third hole 43 and connected to the third CK signal trace 33;
the first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5;
the active layer 6 is plated on the upper surface of the insulating layer of the grid electrode 2 and is also positioned right above the grid electrode 2;
a second metal layer plated on the upper surface of the gate insulating layer 4 to form source electrodes 7, drain electrodes 8 and first signal connection lines 91 which are distributed at intervals, wherein the source electrodes 7 are connected with the left end of the active layer 6, the drain electrodes 8 are connected with the right end of the active layer 6, the drain electrodes 8 are also connected with the pixel electrodes 5, the right ends 911 of the first signal connection lines are connected with the first electrode blocks 51, and the left ends 912 of the first signal connection lines are connected with the second electrode blocks 52;
a passivation layer 10 plated on the upper surfaces of the gate insulating layer 4, the active layer 6, the second metal layer, and the pixel electrode 5, wherein a fourth hole 101 is formed in the passivation layer 10, and the third electrode block 53 is exposed from the fourth hole 101;
the conducting layer 20 is plated on the upper surface of the passivation layer 10 and is further located right above the drain electrode 8, the upper surface of the passivation layer is further plated with a second signal connection line 92, the conducting layer 20 is connected with the right end of the second signal connection line 92, and the left end of the second signal connection line 92 passes through the fourth hole 101 to be connected with the third electrode block 53.
In the present invention, a conductive layer 20 is disposed above the drain electrode 8, a supplemental capacitance is formed between the conductive layer 20 and the drain electrode 8, the signal of the gate electrode 2 is provided by a first CK signal trace 31, and the conductive layer 20The signal is provided by the third CK signal trace 33, the potential of the conductive layer 20 is opposite to that of the gate 2, the coupling effect of the gate 2 to the drain 8 and the coupling effect of the conductive layer 20 to the drain 8 cancel each other, and the voltage difference generated between the pixel electrode 5 and the drain 8 is reduced, so that the Feedthrough voltage is reduced, and the flicker of the picture of the liquid crystal display is reduced; when the supplementary capacitance and the parasitic capacitance are equal in size, the feedback voltage is eliminated, the potential level of the pixel electrode 5 is maintained, and the picture display stability of the liquid crystal display is improved; effectively prevent V of the common electrode 40 in an ideal state com The point position deviates from the center position of the actually provided positive and negative deflection voltages; the voltage values at two ends of the liquid crystal in the positive and negative polarity states are kept the same, and the deflection angles of the liquid crystal in the positive and negative polarities are the same, so that the light quantity of the array substrate is the same, and the picture of the liquid crystal display is stable.
The conductive layer 20 is disposed near the position where the drain electrode 8 contacts the active layer 6, and the field strength of the position is larger, so that the schottky barrier formed by the contact of the semiconductor of the active layer 6 and the metal line of the drain electrode 8 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.
By pre-opening the first hole 41, the second hole 42 and the third hole 43 in the gate insulating layer 4 and then filling the first electrode block 51, the second electrode block 52 and the third electrode block 53 respectively, the influence of the subsequent process etching on the metal of the first metal layer is avoided. The first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5, so that the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed into films in the same process, the substrate structure is simplified, the productivity is improved, and the cost is reduced. When the passivation layer 10 etches the fourth hole 101, the third electrode block 53 is exposed from the fourth hole 101, and thus the third CK signal trace 33 is not etched, and damage to the metal of the outermost layer of the third CK signal trace 33 located in the first metal layer is avoided; the conductive layer 20 is connected to the third electrode block 53 through the fourth hole 101, and the conductive layer 20 and the third electrode block 53 are made of ITO.
Further comprises: the second metal layer also forms TP traces 30 that are spaced apart;
the passivation layer 10 is further provided with a fifth hole 102, and the TP trace is exposed out of the fifth hole 102;
and a common electrode 40 plated on the upper surface of the passivation layer 10, wherein the common electrode 40 is further connected to the TP trace 30 through the fifth hole 102. One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 5, and the other end is connected to the common electrode 40. The full name of TP wiring is Touch Panel Senser Line; the TP trace provides a voltage signal to the common electrode.
The first metal layer and the second metal layer are both of a Ti/AL/Ti three-layer structure or an MO/AL/MO three-layer structure.
The gate insulating layer 4 is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer 10 is of SiO 2 The outer insulating layer is made of SiOx, siNO or SiNx.
The active layer 6 is made of IGZO, and the conductive layer 20, the pixel electrode 5, the first electrode block 51, the second electrode block 52, the third electrode block 53, the second signal connection line 92 and the common electrode 40 are made of ITO. The ITO has good conductivity and light transmittance, and the materials of the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are ITO, so that the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed into films in the same process, and the materials of the conductive layer 20 and the common electrode 40 of the array substrate are ITO, so that the conductive layer 20 and the common electrode 40 can be formed into films in the same process, thereby simplifying the substrate structure and improving the productivity.
The first metal layer further forms a second CK signal trace 32 and a fourth CK signal trace 34 that are distributed at intervals, and the potential of the second CK signal trace 32 is opposite to that of the fourth CK signal trace 34;
The first CK signal wire (CK 1) is connected with the grid electrode of the array substrate of the first row, the second CK signal wire (CK 2) is connected with the grid electrode of the array substrate of the second row, the third CK signal wire (CK 3) is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal wire (CK 4) is connected with the conductive layer of the array substrate of the fourth row.
For the first row of the array substrate, a first hole 41 is formed in the position of the grid electrode 2 of the first row, a second hole 42 is formed in the position of the first CK signal wire 31, a third hole 43 is formed in the position of the third CK signal wire 33, and the first row of the array substrate is provided with a first signal connecting wire 91 and a second signal connecting wire 92; for the second row of the array substrate, the first hole 41 is formed at the position of the second row gate 2, the second hole 42 is formed at the position of the second CK signal trace 32, the third hole 43 is formed at the position of the fourth CK signal trace 34, and the second row of the array substrate also has the first signal connection line 91 and the second signal connection line 92.
The signal timing phase of the first CK signal trace 31 is one quarter cycle earlier than the signal timing phase of the second CK signal trace 32, and the signal timing phase of the third CK signal trace 33 is one quarter cycle earlier than the signal timing phase of the fourth CK signal trace 34. When the first CK signal wiring 31 drives the gate electrode 2 of the first row TFT device to a high potential, the source electrode 7 and the drain electrode 8 of the first row TFT device are turned on, a data voltage signal is written to the pixel electrode 5, after a quarter period of time, the second CK signal wiring 32 drives the gate electrode 2 of the second row TFT device to a high potential, the source electrode 7 and the drain electrode 8 of the second row TFT device are turned on, and a data voltage signal is written to the pixel electrode 5. When the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, and when the first CK signal wiring 31 is at a low potential, the third CK signal wiring 33 is at a high potential; the potential of the second CK signal wiring 32 is the same as that of the fourth CK signal wiring 34. The array substrate causes the display screen to be sequentially lighted from top to bottom or bottom to top of the pixels of one row under the control of the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34. For example, when the first CK signal trace is 10V, the third CK signal trace is-15V; when the first CK signal trace is-15V, the third CK signal trace is 10V.
And a driving IC connected to the first, second, third, and fourth CK signal wirings 31, 32, 33, and 34. The driving ICs are used to give different timing signals to the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34.
The invention maintains the working principle of the array base plate of the potential level of the pixel electrode:
in this embodiment, the design of the single-side level 4CK is taken as an example (note that the circuit design of the present invention is not limited to the single-side level 4CK, but may be double-side level), the timing chart is shown in fig. 5, and fig. 4 is a circuit diagram of all pixels in the first row in fig. 3. In short, the display of the picture is realized by sequentially lighting pixels of a row from top to bottom or from bottom to top. The pixel needs to be lightened, the grid electrode 2 corresponding to the pixel TFT device in the row is at a high potential, then the TFT device is turned on, and a data signal can be written into the pixel electrode 5, so that the liquid crystal is controlled to twist, and the pixel is lightened. Taking the first row of pixels as an example, when the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, the high potential of the first CK signal wiring 31 is transferred to the first row of gates 2, the TFT devices of the first row are turned on, the pixel electrode 5 is signal-written, and the low potential of the third CK signal wiring 33 is transferred to the conductive layer 20 of the first row; when the first CK signal trace 31 is switched to low, the third CK signal trace 33 is switched to high, the gate 2 is switched from high to low, and the parasitic capacitance formed by the gate 2 and the drain 8 will have a coupling effect, so as to pull down the voltage of the drain 8, but since the third CK signal trace 33 is switched from low to high, i.e. the conductive layer 20 of the first row is switched from low to high, the complementary capacitance formed by the conductive layer 20 and the drain 8 will have a coupling effect, so as to pull up the drain voltage, so that the drain voltage will not change due to the jump of the gate, that is, the voltage of the pixel electrode will not change. Note that the design here requires C Supplement and supplement And C gd Equal in magnitude, the purpose of this design is to have an increased and decreased two feedthru voltages at the drain 8 and equal in magnitude. Similarly, each row of TFT devices can avoid production jump due to the grid electrode 2The voltage of feed through caused by the change.
At the microscopic level, it is the migration of charges between the drain electrode 8 and the pixel electrode 5 that causes a change in the amount of charges stored on the pixel electrode 5 and thus a change in voltage. After the pixel electrode 5 is charged, the electric potential between the drain electrode 8 and the pixel electrode 5 is equal, and no electron transfer occurs between them, but since the voltage of the gate electrode 2 is switched from a high potential to a low potential at this moment, the change is coupled to the drain electrode 8 through the parasitic capacitance formed by the gate electrode 2 and the drain electrode 8, and a voltage difference is generated between the drain electrode 8 and the pixel electrode 5, so that the electric charge transfer occurs between the drain electrode 8 and the pixel electrode 5, and the pixel electrode 5 is changed. The invention solves this problem by adding a conductive layer 20, the conductive layer 20 and the drain electrode 8 forming a supplemental capacitance C Supplement and supplement Then, opposite potential signals are respectively given to the grid electrode 2 and the conductive layer 20 through the first CK signal wiring 31 and the third CK signal wiring 33, so that the coupling effect of parasitic capacitance and complementary capacitance is counteracted, and the working performance of the device is improved.
A manufacturing method of an array substrate for maintaining the potential level of a pixel electrode comprises the following steps:
s1, referring to FIG. 8, a first metal layer is plated on the upper surface of a glass substrate 1 to form a grid electrode 2, a first CK signal wire 31, a second CK signal wire 32, a third CK signal wire 33 and a fourth CK signal wire 34 which are distributed at intervals, wherein the potential of the first CK signal wire is opposite to that of the third CK signal wire, and the potential of the second CK signal wire 32 is opposite to that of the fourth CK signal wire 34;
the gate 2 is used for turning on and off the TFT device, the first CK signal wire 31 is used for transmitting a first row gate 2 signal, the second CK signal wire 32 is used for transmitting a second row gate signal, the third CK signal wire 33 is used for transmitting a first row conductive layer 20 signal, and the fourth CK signal wire 34 is used for transmitting a second row conductive layer signal; the material of the first metal layer can be selected from any one of MO/AL/MO three-layer structure, ti/AL/Ti three-layer structure, AL/MO double-layer structure (MO is used as top layer), and AL/Ti double-layer structure (Ti is used as top layer), and PVD film is formed. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, by using the small expansion coefficient of MO or Ti, the deformation of AL in a high-temperature process can be restrained, and the oxidation of AL can be prevented.
S2, referring to FIG. 9, plating a gate insulating layer 4 on the upper surfaces of the glass substrate 1 and the first metal layer;
the insulating layer of the gate electrode 2 is used as an insulating medium and is also a capacitance medium between the gate electrode 2 and the active layer 6, and the material is formed by using SiOx single layer or SiNx/SiOx double layer in a CVD mode. Considering that the requirements of TFT devices at present are fast reaction and low power consumption, and these are all achieved by shrinking TFT devices, and in order to achieve miniaturization of the devices, a suitable high-K material (such as HfO 2) needs to be selected for the gate insulating layer 4, but considering that the interface of HfO2 has more defects, if the interface is directly contacted with the active layer 6 or the gate 2 metal, the stability of the devices may be affected, so that SiOx or SiNx with a relatively good interface may be considered (SiNx can only be used as a contact film layer with the gate metal layer, if as a contact surface with IGZO, H remained in the SiNx film layer during film forming may destroy IGZO characteristics) serving as a contact surface, such as SiOx/HfO2/SiOx three-layer structure needs to be relatively larger in thickness of the SiOx three-layer structure in order to ensure that the advantage of representing the high-K material is guaranteed.
S3, referring to FIG. 10, a first hole 41, a second hole 42 and a third hole 43 are formed in the gate insulating layer 4, the gate 2 is exposed out of the first hole 41, the first CK signal wire 31 is exposed out of the second hole 42, and the third CK signal wire 33 is exposed out of the third hole 43;
For the first row of the array substrate, a first hole 41 is formed in the position of the grid electrode of the first row, a second hole 42 is formed in the position of the first CK signal wire 31, and a third hole 43 is formed in the position of the third CK signal wire 33; for the second row of the array substrate, a first hole 41 is formed at the position of the second row gate, a second hole 42 is formed at the position of the second CK signal trace 32, and a third hole 43 is formed at the position of the fourth CK signal trace 34. The first hole 41, the second hole 42 and the third hole 43 are located outside the pixel display area 11.
The dry etching digs out the first hole 41, the second hole 42 and the third hole 43, the first hole 41 and the second hole 42 serve to provide the connection of the first CK signal trace 31 (or the second CK signal trace 32), the first signal connection line 91 and the gate 2, and the third hole 43 serves to provide the connection of the third CK signal trace 33 (or the fourth CK signal trace 34) and the second signal connection line 92.
S4, referring to FIG. 11, plating a pixel electrode 5 on the upper surface of the gate insulating layer 4, wherein the pixel electrode 5 is also positioned at the side of the gate electrode 2;
plating a first electrode block 51, a second electrode block 52 and a third electrode block 53 on the first hole 41, the second hole 42 and the third hole 43 respectively, wherein the first electrode block 51 is connected with the grid 2, the second electrode block 52 is connected with the first CK signal wire 31, and the third electrode block 53 is connected with the third CK signal wire 33;
The first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5;
the materials of the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are all selected to be ITO, mainly because ITO has good conductivity and light transmittance, PVD film formation and acid wet etching. By pre-opening the first hole 41, the second hole 42 and the third hole 43 in the gate insulating layer 4 and then filling the first electrode block 51, the second electrode block 52 and the third electrode block 53 respectively, the influence of the subsequent process etching on the metal of the first metal layer is avoided.
S5, referring to FIG. 12, plating an active layer 6 on the upper surface of the gate insulating layer 4, wherein the active layer 6 is positioned right above the grid electrode 2; the active layer 6 is in the plane of the pixel display area 11.
The material of the active layer 6 is selected from metal oxide semiconductors such as IGZO, and PVD is performed by wet etching.
S6, referring to FIG. 13, a second metal layer is plated on the upper surface of the gate insulating layer 4 to form source electrodes 7 and drain electrodes 8 which are distributed at intervals and a first signal connection line 91, wherein the source electrodes 7 are connected with the left end of the active layer 6, the drain electrodes 8 are connected with the right end of the active layer 6, the drain electrodes 8 are also connected with the pixel electrodes 5, the right ends 911 of the first signal connection line are connected with the first electrode block 51, and the left ends 912 of the first signal connection line are connected with the second electrode block 52; the second metal layer also forms TP traces 30 that are spaced apart. The source electrode 7 and the drain electrode 8 are both in the plane of the pixel display area 11.
The material of the second metal layer can be selected from an MO/AL/MO three-layer structure or a Ti/AL/Ti three-layer structure, PVD film forming and acid liquid wet etching. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, the expansion coefficient of the outer metal MO or Ti is smaller, so that the deformation of the AL in a high-temperature process can be restrained, and the oxidation of the AL can be prevented.
S7, referring to FIG. 14, plating a passivation layer 10 on the upper surfaces of the gate insulating layer 4, the active layer 6, the second metal layer and the pixel electrode 5;
simultaneously etching a fourth hole 101 and a fifth hole 102 in the passivation layer 10, wherein the third electrode block 53 is exposed out of the fourth hole 101, and the TP trace 30 is exposed out of the fifth hole 102; the fourth cutout 101 and the fifth cutout 102 are out of the pixel display area 11.
The material of the passivation layer 10 is selected to be SiO 2 CVD film formation, dry etching digs out the fourth hole 101 and the fifth hole 102, the fourth hole 101 functions to provide a junction of the third CK signal trace 33 and the conductive layer 20, and the fifth hole 102 functions to provide a junction of the common electrode 40 and the TP trace 30. Since the gate insulating layer 4 under the position of the fourth hole 101 has been dug into the third hole 43 in step S4 and the third hole 43 is covered by the third electrode block 53 of ITO having excellent conductivity and the upper surface of the TP trace 30 is positioned at the same position as the upper surface of the third electrode block 53, the etching depths of both the fourth hole 101 and the fifth hole 102 are the same as the thickness of the passivation layer 10 so that the outer protective metal of the third CK signal trace 33 of the first metal layer is not etched, and the exposure of the internal metal line (AL) to the air due to the absence of the outer protective metal (MO or Ti) of the third CK signal trace 33 is prevented Oxidation in the gas causes problems such as an increase in contact resistance.
S8, referring to fig. 15, the conductive layer 20, the second signal connection line 92 and the common electrode 40 are plated on the upper surface of the passivation layer 10, the conductive layer 20 is further located right above the drain electrode 8, the conductive layer 20 is connected to the right end of the second signal connection line 92, the left end of the second signal connection line 92 passes through the fourth hole 43 to be connected to the third electrode block 53, and the lead wire of the common electrode 40 passes through the fifth hole 102 to be connected to the TP trace 30.
As shown in fig. 7, the conductive layer 20 and the second signal connection line 92 do not cover the channel to the active layer 6; the voltage signals of the conductive layer 20 and the second signal connection line 92 are prevented from interfering with the channel of the active layer 6, and the operation stability of the active layer is ensured.
The materials of the conductive layer 20 and the common electrode 40 are selected to be ITO mainly because ITO has good conductivity and light transmittance, PVD film formation, acid wet etching. The materials of the conductive layer 20 and the common electrode 40 are ITO, so that the conductive layer 20 and the common electrode 40 can be formed into a film in the same process, thereby simplifying the substrate structure and improving the productivity. The conductive layer 20 is designed right above the source electrode 7 to form a capacitance structure with the drain electrode 8, and the capacitance of the complementary capacitance formed by the conductive layer 20 and the drain electrode 8 is identical to the capacitance of the parasitic capacitance formed by the gate electrode 2 and the drain electrode 8, so that the capacitance can be equal by regulating the right area and the film distance of the conductive layer 20.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the invention, and that equivalent modifications and variations of the invention in light of the spirit of the invention will be covered by the claims of the present invention.
Claims (10)
1. An array substrate for maintaining a potential level of a pixel electrode, comprising:
a glass substrate;
a first metal layer plated on the upper surface of the glass substrate to form grid electrodes, a first CK signal wiring and a third CK signal wiring which are distributed at intervals, wherein the potential of the first CK signal wiring is opposite to that of the third CK signal wiring;
the gate insulating layer is plated on the upper surfaces of the glass substrate and the first metal layer, a first hole, a second hole and a third hole are formed in the gate insulating layer, the gate is exposed out of the first hole, the first CK signal wire is exposed out of the second hole, and the third CK signal wire is exposed out of the third hole;
the pixel electrode is plated on the upper surface of the gate insulating layer and is also positioned at the side of the grid electrode;
The first electrode block is plated on the first hole and is also connected with the grid electrode;
the second electrode block is plated on the second hole and is also connected with the first CK signal wiring;
the third electrode block is plated on the third hole and is also connected with the third CK signal wiring;
the first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;
the active layer is plated on the upper surface of the grid insulation layer and is also positioned right above the grid;
the second metal layer is plated on the upper surface of the gate insulating layer, source electrodes, drain electrodes and first signal connecting wires which are distributed at intervals are formed, the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the drain electrodes are also connected with the pixel electrodes, the right end of the first signal connecting wire is connected with the first electrode block, and the left end of the first signal connecting wire is connected with the second electrode block;
the passivation layer is plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode, a fourth hole is formed in the passivation layer, and the third electrode block is exposed out of the fourth hole;
the conducting layer is plated on the upper surface of the passivation layer and is further positioned right above the drain electrode, a second signal connecting wire is plated on the upper surface of the passivation layer, the conducting layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire penetrates through the fourth hole to be connected with the third electrode block.
2. The array substrate for maintaining a potential level of a pixel electrode according to claim 1, further comprising:
the second metal layer also forms TP wirings which are distributed at intervals;
the passivation layer is also provided with a fifth hole, and the TP wiring is exposed out of the fifth hole;
and the public electrode is plated on the upper surface of the passivation layer, and a lead of the public electrode also passes through the fifth hole to be connected with the TP wiring.
3. The array substrate for maintaining the potential level of the pixel electrode according to claim 2, wherein the first metal layer and the second metal layer are both Ti/AL/Ti three-layer structure or MO/AL/MO three-layer structure.
4. The array substrate for maintaining a potential level of a pixel electrode according to claim 2, wherein the gate insulating layer is a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer is SiO 2 The outer insulating layer is made of SiOx, siNO or SiNx.
5. The array substrate for maintaining the potential level of the pixel electrode according to claim 2, wherein the active layer is made of IGZO, and the conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are made of ITO.
6. The array substrate for maintaining the potential level of a pixel electrode according to claim 1, wherein the first metal layer further forms second and fourth CK signal wirings which are spaced apart, and the second CK signal wiring has a potential opposite to the fourth CK signal wiring;
the first CK signal wire is connected with the grid electrode of the array substrate of the first row, the second CK signal wire is connected with the grid electrode of the array substrate of the second row, the third CK signal wire is connected with the conductive layer of the array substrate of the first row, and the fourth CK signal wire is connected with the conductive layer of the array substrate of the second row.
7. The array substrate for maintaining a potential level of a pixel electrode according to claim 6, wherein a signal timing phase of the first CK signal wiring is earlier than a signal timing phase of the second CK signal wiring by a quarter period, and a signal timing phase of the third CK signal wiring is earlier than a signal timing phase of the fourth CK signal wiring by a quarter period.
8. The manufacturing method of the array substrate for maintaining the potential level of the pixel electrode is characterized by comprising the following steps:
S1, plating a first metal layer on the upper surface of a glass substrate to form grid electrodes, first CK signal wires and third CK signal wires which are distributed at intervals, wherein the potential of the first CK signal wires is opposite to that of the third CK signal wires;
s2, plating a gate insulating layer on the upper surfaces of the glass substrate and the first metal layer;
s3, a first hole, a second hole and a third hole are formed in the gate insulating layer, the grid electrode is exposed out of the first hole, the first CK signal wire is exposed out of the second hole, and the third CK signal wire is exposed out of the third hole;
s4, plating a pixel electrode on the upper surface of the gate insulating layer, wherein the pixel electrode is also positioned at the side of the gate electrode;
plating a first electrode block, a second electrode block and a third electrode block on the first hole, the second hole and the third hole respectively, wherein the first electrode block is connected with the grid, the second electrode block is connected with the first CK signal wire, and the third electrode block is connected with the third CK signal wire;
the first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;
S5, plating an active layer on the upper surface of the gate insulating layer, wherein the active layer is positioned right above the gate electrode;
s6, plating a second metal layer on the upper surface of the gate insulating layer to form source electrodes, drain electrodes and first signal connecting lines which are distributed at intervals, wherein the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the drain electrodes are also connected with the pixel electrodes, the right end of the first signal connecting line is connected with the first electrode block, and the left end of the first signal connecting line is connected with the second electrode block;
s7, plating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode;
a fourth hole is formed in the passivation layer, and the third electrode block is exposed out of the fourth hole;
s8, plating a conductive layer and a second signal connecting wire on the upper surface of the passivation layer, wherein the conductive layer is further positioned right above the drain electrode, the conductive layer is connected with the right end of the second signal connecting wire, and the left end of the second signal connecting wire penetrates through the fourth hole to be connected with the third electrode block.
9. The method of claim 8, further comprising:
In the step S6, the second metal layer further forms TP traces distributed at intervals;
in the step S7, etching a fourth hole and a fifth hole on the passivation layer at the same time, wherein the TP wiring is exposed out of the fifth hole;
in the step S8, a conducting layer, a second signal connecting wire and a common electrode are plated on the upper surface of the passivation layer at the same time, and a lead of the common electrode is connected with the TP wiring through the fifth hole.
10. The method of claim 9, wherein the conductive layer, the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are made of ITO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310082142.6A CN116153942A (en) | 2023-01-28 | 2023-01-28 | Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310082142.6A CN116153942A (en) | 2023-01-28 | 2023-01-28 | Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116153942A true CN116153942A (en) | 2023-05-23 |
Family
ID=86352201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310082142.6A Pending CN116153942A (en) | 2023-01-28 | 2023-01-28 | Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116153942A (en) |
-
2023
- 2023-01-28 CN CN202310082142.6A patent/CN116153942A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108598087B (en) | Array substrate, manufacturing method thereof, display panel and electronic device | |
| CN100524422C (en) | Transistor circuit, display panel and electronic apparatus | |
| CN108155195A (en) | Show equipment | |
| CN108231904A (en) | Thin film transistor (TFT) and its driving method, display device and transistor circuit | |
| CN110289270B (en) | Array substrate, manufacturing method thereof and display device | |
| US20200241369A1 (en) | Pixel structure and manufacturing method thereof, array substrate and display device | |
| CN104914639A (en) | TFT baseplate and display device | |
| US20220115407A1 (en) | Array substrate and display panel | |
| CN109713043A (en) | Thin film transistor (TFT) and its manufacturing method, array substrate, electronic device | |
| CN101924122B (en) | Active matrix/organic light emitting display and manufacturing method thereof | |
| CN100530278C (en) | Display device | |
| CN102969311A (en) | Array substrate and manufacturing method thereof, and display device | |
| CN109300995A (en) | A kind of thin film transistor and its manufacturing method, array substrate and display panel | |
| CN112993041B (en) | Liquid crystal display panel, thin film transistor and manufacturing method thereof | |
| US11538395B2 (en) | Shift register unit and driving method thereof, gate drive circuit, and display device | |
| CN105572981B (en) | array substrate, display panel and liquid crystal display device | |
| CN219267658U (en) | Array substrate for maintaining potential level of pixel electrode | |
| CN219267655U (en) | Array substrate capable of reducing parasitic capacitance coupling influence | |
| CN219286412U (en) | High-aperture-ratio array substrate capable of reducing feed voltage | |
| CN219267656U (en) | Reduce array substrate of feedthru voltage | |
| CN219267657U (en) | Pixel voltage-stabilizing array substrate capable of avoiding metal overetching | |
| US20130100005A1 (en) | LCD Panel and Method of Manufacturing the Same | |
| CN116153942A (en) | Array substrate for maintaining potential level of pixel electrode and manufacturing method thereof | |
| US11705460B2 (en) | Panel, electronic device and transistor | |
| CN116130493A (en) | Array substrate capable of reducing parasitic capacitance coupling influence and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |