CN219265547U - Pressure chip - Google Patents

Abstract

The present utility model provides a pressure chip, comprising: the device layer is integrated with a pressure detection circuit in the upper surface layer, the pressure detection circuit is electrically connected with the outside through a metal electrode, and the pressure detection circuit comprises a piezoresistance element; a protective layer fixedly attached to the upper surface of the device layer, wherein contact holes for the upper and lower sides of the metal electrode to penetrate through are formed in the protective layer; an isolation connecting layer fixedly attached to the lower surface of the device layer; the support layer is fixedly attached to the lower surface of the isolation connecting layer, a first cavity is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity; the lower end of the first cavity extends to the lower surface of the isolation connecting layer to form a pressure inlet, and the upper end of the first cavity extends to the lower surface of the isolation connecting layer. The utility model can stabilize the pressure in the reference pressure cavity through absorbing the residual gas in the chip material.

Description

Pressure chip

Technical Field

The utility model relates to the technical field of sensors, in particular to a pressure chip.

Background

The piezoresistive pressure sensor manufactured by MEMS (Micro Electro Mechanical System) technology has the advantages of small volume, easy integration, reliable performance, capability of converting non-electric signals into electric signals and the like, and is commonly used for pressure measurement in the fields of automobiles, aerospace, petrochemical industry, biomedical treatment and the like. The core element is a pressure chip, and the manufacturing method of the pressure chip is as follows: and preparing a piezoresistor structure on the silicon wafer, connecting the piezoresistor into a Wheatstone bridge structure by using a metal lead area or a heavily doped silicon lead area, and preparing a cavity on the back of the wafer to enable the silicon wafer to be provided with a pressure sensing film layer. The piezoresistor is generally positioned at the edge of the film layer, and when the pressure sensing film is subjected to pressure deformation, the stress generated at the edge of the pressure sensing film layer is the largest, so that the resistance value of the piezoresistor is changed, and the output voltage of the Wheatstone bridge is also changed according to the change of the resistance value.

As shown in fig. 1, in the prior art, the back side cavity of the pressure chip is typically fabricated by wet etching, which places the wafer in a specific crystal orientation during fabrication. Therefore, when wet etching is used, the side wall of the back cavity has a fixed angle α with the plane of the wafer, which makes the plane size of the pressure chip larger, so that the utilization rate of the wafer still has room for improvement.

On the other hand, for an absolute pressure sensor, it is also necessary to provide a reference pressure chamber (typically a vacuum chamber) on the front surface of the pressure-sensitive material. Since the pressure chip inevitably uses hydrogen as a process gas or a reaction gas in many cases during the manufacturing process, part of residual hydrogen in the pressure chip slowly accumulates in the reference pressure chamber; in addition, during the bonding process of the chip, part of water vapor, nitrogen and the like can be remained. These residual gases are slowly released during use. This causes an increase in pressure in the reference pressure chamber, eventually causing a deviation in the measurement results.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

Disclosure of Invention

Aiming at the defects of the prior art, the utility model provides a pressure chip and a manufacturing method thereof, which are used for absorbing residual hydrogen in a chip material so as to stabilize the pressure in a reference pressure cavity.

To achieve the above object, the present utility model provides a pressure chip comprising:

the device layer is integrated with a pressure detection circuit in the upper surface layer, the pressure detection circuit is electrically connected with the outside through a metal electrode, and the pressure detection circuit comprises a piezoresistance element;

a protective layer fixedly attached to the upper surface of the device layer, wherein contact holes for the upper and lower sides of the metal electrode to penetrate through are formed in the protective layer;

an isolation connecting layer fixedly attached to the lower surface of the device layer;

the support layer is fixedly attached to the lower surface of the isolation connecting layer, a first cavity is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity; the lower end of the first cavity extends to the lower surface of the isolation connecting layer to form a pressure inlet, and the upper end of the first cavity extends to the lower surface of the isolation connecting layer.

Preferably, the upper surface of the protective layer is provided with a cover, a sealed reference pressure cavity is formed between the cover and the protective layer, and the piezoresistive element is located right below the reference pressure cavity.

Preferably, a gas absorbent is arranged in the reference pressure chamber.

Preferably, the gas absorbent is a gas absorbing film; the cover is inwards recessed to form a first groove corresponding to one side surface of the reference pressure cavity, and the gas absorption film is arranged at the bottom of the first groove.

Preferably, the gas absorbing film is made of Ti, zr or a hydrogen storage alloy.

Preferably, the middle part of the upper surface of the device layer is recessed inwards to form a second groove, and the edge of the upper surface of the device layer is raised relatively to form a third flange; the upper surface of the protective layer is inwards concave to form a mounting groove, and the edge of the upper surface of the protective layer is relatively convex to form a fourth flange; the contact hole is arranged on the fourth flange; the cover is connected in the mounting groove.

Preferably, the lower outer edge of the cover coincides with the bottom edge of the mounting groove.

The utility model also provides a manufacturing method of the pressure chip, which comprises the following steps:

the supporting layer and the device layer are respectively manufactured on the upper side and the lower side of the isolation connecting layer, and a shielding layer is manufactured on the upper surface of the device layer;

manufacturing a pressure detection circuit on the surface layer of the device layer through an ion implantation process;

removing the shielding layer on the surface through etching and other processes;

manufacturing a protective layer on the upper surface of the device layer through epitaxial growth;

manufacturing a contact hole on the protective layer through patterning etching;

manufacturing a metal layer on the protective layer through a PVD process;

reserving a part corresponding to the contact hole on the metal layer through patterning etching, so as to form a metal electrode;

sealing and connecting the cover on the upper surface of the protective layer to form a second cavity between the cover and the protective layer;

removing the redundant part of the cover through a DRIE process to expose the metal electrode; and forming a first cavity on the lower surface of the support layer through a wet etching process.

Preferably, the cover is made by the following method:

manufacturing a first groove and a yielding groove on the lower surface of the cover through a DRIE process;

a gas absorption film made of a metallic hydrogen storage material is manufactured on the lower surface of the cover;

the gas-absorbing film is metal etched to expose the second flange.

Drawings

FIG. 1 is a schematic diagram of a prior art pressure chip;

FIG. 2 is a schematic diagram of a pressure chip according to a first embodiment of the present utility model;

fig. 3 to 13 are schematic structural views of the components of the pressure chip according to the first embodiment of the present utility model during step-by-step fabrication;

FIG. 14 is a schematic diagram of a pressure chip according to a second embodiment of the present utility model;

FIG. 15 is a schematic diagram of a pressure chip according to a third embodiment of the present utility model;

in the figure: 1. a support layer; 1a, a first cavity; 1b, a first flange; 1c, cavity walls; 2. isolating the connection layer; 3. a device layer; 3a, resistance; 3b, conductors; 3c, contact electrode; 4. a shielding layer; 5. a protective layer; 5a, contact holes; 5c, a mounting groove; 5d, a fourth flange; 6. a metal layer; 6a, a metal electrode; 6b, a metal electrode; 7. a cover; 70. a base; 7a, a first groove; 7b, a second flange; 7c, a yielding groove; 7d, a second cavity; 8. a gas absorbing film;

Detailed Description

The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. The following examples are illustrative only and are not to be construed as limiting the utility model. In the following description, the same reference numerals are used to designate the same or equivalent elements, and duplicate descriptions are omitted.

In the description of the present utility model, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, or the directions or positional relationships conventionally put in place when the inventive product is used, or the directions or positional relationships conventionally understood by those skilled in the art are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in a specific direction, and therefore should not be construed as limiting the present utility model.

In addition, the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model can be understood as appropriate by those of ordinary skill in the art.

It should be further understood that the term "and/or" as used in the present description and the corresponding claims refers to any and all possible combinations of one or more of the listed items.

As shown in fig. 2. In a first embodiment of the utility model, the pressure chip comprises a laterally extending isolation connection layer 2, the upper surface of the isolation connection layer 2 is attached with a device layer 3, and the lower surface of the isolation connection layer 2 is attached with a support layer 1.

Wherein, the middle part of the back of the supporting layer 1 is recessed to form a first cavity 1a, and the edge part of the supporting layer 1 is opposite to form a first flange 1b. The first flange 1b is intended to be mounted on an external structure, such as a ceramic substrate. The cavity wall 1c of the first cavity 1a is inclined to the isolating connection layer 2.

The surface layer of the device layer 3 may be formed with a plurality of resistors 3a (i.e., piezoresistive elements) and conductors 3b for electrically connecting the resistors 3a by ion implantation. The plurality of resistors 3a are connected to each other by conductors 3b to form a detection circuit. Typically, four resistors 3a may be connected to the conductor 3b in a wheatstone bridge. A protective layer 5 for insulating and protecting the resistor 3a and the conductor 3b is fixedly attached to the upper surface of the device layer 3.

The four resistors 3a face downward to the first cavity 1a, i.e. the resistors 3a are all projected into the first cavity 1a along the longitudinal direction. A cover 7 is fixed to the upper surface of the protective layer 5.

The protective layer 5 and the adjacent side of the cover 7 together define a second cavity 7d. The four resistors 3a face upward to the first cavity 1a, i.e. the resistors 3a are also projected into the first cavity 1a along the longitudinal direction. Thus, the first cavity 1a and the second cavity 7d are located at two sides of the device layer 3, and act on the device layer, so that the measurement circuit generates measurement electric signals at the pressure difference at two sides. The protective layer 5 is further provided with contact holes 5a, 5b penetrating the protective layer 5 up and down. The conductor 3b is electrically connected to the outside through the metal electrodes 6a, 6b to output a measurement electric signal.

In the present embodiment, a gas absorbent is disposed in the second chamber 7d. Wherein the gas absorbent may be a film-like material. For example, the cover 7 includes a base 70, a lower surface of the base 70 is depressed inward at a middle portion thereof to form a first groove 7a, and the first groove 7a and an upper surface of the protective layer 5 together define a second chamber 7d (reference pressure chamber). A gas absorbing film 8 capable of absorbing hydrogen is adhered to the top of the inner wall of the first groove 7 a. The gas absorbent can absorb one or more of hydrogen, water vapor and nitrogen. Preferably, the gas absorbing membrane 8 may be made of a known hydrogen storage material. Meanwhile, in order for the portions of the base 70 corresponding to the metal electrodes 6a, 6b to be recessed inward, portions for giving the metal electrodes 6a, 6b protruding upward (whose thickness is that of the metal layer 6) are formed so as to be offset, and are protected in a subsequent process. In some variant embodiments, the gas-absorbing film 8 may be Ti or Zr, so that part of the hydrogen and water vapor can also be absorbed simultaneously.

Preferably, the hydrogen storage material may be a metal material such as rare earth-based, titanium-based, zirconium-based, and magnesium-based hydrogen storage alloys. These metal materials can be conveniently formed on the cover 7 or the protective layer 5 by vacuum evaporation or physical vapor deposition. These alloys are currently used for the storage of hydrogen energy but, when applied in the present utility model, are capable of absorbing small amounts of hydrogen. In particular, the second chamber 7d may be a vacuum chamber, and in this case, when a small amount of hydrogen gas can be absorbed, the measurement result deviation can be greatly reduced.

For silicon, which is a general semiconductor material, the support layer 1 and the device layer 3 may be silicon, and the isolation connection layer 2 and the protection layer 5 may be silicon oxide or silicon nitride.

As shown in fig. 3 to 13, in the present embodiment, a silicon semiconductor material is taken as an example to describe the method for manufacturing the pressure chip:

a supporting layer 1 (Silicon layer) and a device layer 3 (Silicon layer) are respectively manufactured On the upper side and the lower side of an isolation connecting layer 2 (Silicon oxide layer), and a shielding layer 4 (Silicon oxide layer) is manufactured On the upper surface of the device layer 3 to form an SOI (Silicon-On-Insulator) structure, as shown in figure 3;

the SOI structure described above may be fabricated by SIMOX (Seperation by Implant of Oxygen) techniques, or bonding techniques (WB, waferBonding), or Smart cut techniques. Among them, smart-cut technology has become one of the most competitive technologies for fabricating SOI structures, which performs exfoliation of a crystal layer by hydrogen gas, and thus hydrogen gas is introduced during the process of completely splitting a hydrogen injection sheet from a particle injection layer.

(II) performing P-type doping on a first area of the surface layer of the device layer 3 to manufacture a resistor 3a through an ion implantation process, and performing P-type doping on a part of the first area to manufacture a conductor 3b; a contact electrode 3c connected to the conductor 3b is formed on the surface layer of the device layer 3 by an ion implantation process, as shown in fig. 4; the conductor 3b may be formed directly by heavy doping;

(III) removing the surface shielding layer 4 by etching or the like, as shown in FIG. 5;

(IV) manufacturing a protective layer 5 on the upper surface of the device layer 3 through epitaxial growth, as shown in FIG. 6;

(v) making contact holes 5a, 5b on the protective layer 5 by patterning etching, as shown in fig. 7;

(VI) a metal layer 6 is produced on the protective layer 5 by means of a PVD (physical vapor deposition) process, as shown in FIG. 8;

(vii) reserving the portions corresponding to the contact holes 5a, 5b on the metal layer 6 by patterning etching, thereby forming metal electrodes 6a, 6b, as shown in fig. 9;

(VIII) the cover 7 is sealingly attached to the upper surface of the protective layer 5 by welding or the like to form the above-mentioned second cavity 7d, as shown in FIG. 10.

Wherein, the cover 7 can be made of silicon wafer: first, a first recess 7a and a relief groove 7c are formed on the lower surface of the cap 7 by a DRIE (deep reactive ion etching) process, as shown in fig. 11; then, a gas absorption film 8 made of a hydrogen storage alloy is formed on the lower surface of the cover 7, as shown in fig. 12; then, the gas-absorbing film 8 is exposed to the second flange 7b by metal etching to be bonded with the protective layer, as shown in fig. 13;

(ix) removing the excess portion of the cap 7 by a DRIE process, exposing the metal electrodes 6a, 6b; in addition, a first cavity 1a with an inclined side wall is formed on the lower surface of the supporting layer 1 through a wet etching process, so as to obtain the pressure chip shown in fig. 2.

The patterning etching is etching performed in a set pattern under the condition of a mask technique such as photolithography.

As shown in fig. 14, in the second embodiment of the present utility model, the first cavity 1a can be made also by the DRIE process on the basis of the first embodiment, and the first cavity 1a having the cavity wall 1c extending longitudinally can be made due to the anisotropy of the DRIE process. Therefore, the transverse dimension (width) of the supporting layer 1 can be obviously reduced on the premise of ensuring the minimum that the supporting layer 1 can be effectively installed on an external matrix, so that the utilization rate of the wafer is improved; wherein equipment procurement costs are saved, since the cover 7 can also be subjected to a similar DRIE process as the support layer 1.

As shown in fig. 15, in the third embodiment of the present utility model, the middle of the upper surface of the device layer 3 is recessed inwards to form a second groove, and the edge of the upper surface of the device layer 3 is raised relatively to form a third flange, and the second groove can be manufactured by using a DRIE process. Accordingly, the upper surface of the protective layer 5 is recessed inward to form a mounting groove 5c, and the upper surface edge of the protective layer 5 is relatively protruded to form a fourth flange 5d. The contact holes 5a, 5b are provided on the fourth flange 5d. The cover 7 is attached in the mounting groove 5 c. In this way, the height of the top of the cover 7 protruding above the upper surface of the protective layer 5 can be reduced, thereby reducing the risk of the cover 7 falling off during assembly or use. More preferably, the lower outer edge of the cover 7 is fitted with the bottom edge of the mounting groove 5c, thereby facilitating positioning.

In addition to the above embodiments, in the fourth embodiment of the present utility model, the gas absorbent is omitted from the cover 7, and therefore, in the case of manufacturing the pressure chip, the steps of manufacturing the gas absorbent film and metal etching can be omitted accordingly.

The scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the present disclosure.

Claims (7)

1. A pressure die, comprising:

the device layer (3) is integrated with a pressure detection circuit in the upper surface layer, the pressure detection circuit is electrically connected with the outside through metal electrodes (6 a, 6 b), and the pressure detection circuit comprises a piezoresistance element;

a protective layer (5) fixedly attached to the upper surface of the device layer (3), wherein contact holes (5 a, 5 b) for penetrating the upper and lower sides of the metal electrodes (6 a, 6 b) are formed in the protective layer;

an isolation connecting layer (2) fixedly attached to the lower surface of the device layer (3);

the support layer (1) is fixedly attached to the lower surface of the isolation connecting layer (2), a first cavity (1 a) is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity (1 a); the lower end of the first cavity (1 a) extends to the lower surface of the isolation connecting layer (2) to form a pressure introduction port, and the upper end of the first cavity (1 a) extends to the lower surface of the isolation connecting layer (2).

2. Pressure chip according to claim 1, characterized in that the upper surface of the protective layer (5) is provided with a cover (7), a sealed reference pressure chamber is formed between the cover (7) and the protective layer (5), and the piezoresistive element is located directly below the reference pressure chamber.

3. The pressure die of claim 2, wherein a gas absorbent is disposed within the reference pressure chamber.

4. A pressure chip according to claim 3, characterized in that the gas absorbent is a gas absorbing film (8); the cover (7) is inwards recessed to form a first groove (7 a) corresponding to one side surface of the reference pressure cavity, and the gas absorption film (8) is arranged at the bottom of the first groove (7 a).

5. The pressure chip according to claim 4, wherein the gas absorbing film (8) is made of Ti, zr or a hydrogen storage alloy.

6. The pressure chip according to any one of claims 1 to 5, wherein the middle of the upper surface of the device layer (3) is recessed inwards to form a second recess, and the edge of the upper surface of the device layer (3) is raised opposite to form a third flange; the upper surface of the protective layer (5) is inwards recessed to form a mounting groove (5 c), and the edge of the upper surface of the protective layer (5) is relatively protruded to form a fourth flange (5 d); the contact holes (5 a, 5 b) are arranged on the fourth flange (5 d); the cover (7) is connected in the mounting groove (5 c).

7. A pressure chip according to claim 6, characterized in that the lower outer edge of the cover (7) coincides with the bottom edge of the mounting groove (5 c).

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