CN115901030A - Pressure chip and manufacturing method thereof - Google Patents

Abstract

The invention provides a pressure chip and its preparation method, the pressure chip includes: the device layer is internally integrated with a pressure detection circuit in the upper surface layer, the pressure detection circuit is electrically connected with the outside through a metal electrode, and the pressure detection circuit comprises a piezoresistive element; the protective layer is fixedly attached to the surface of the upper side of the device layer, and a contact hole for the upper side and the lower side of the metal electrode to penetrate through is formed in the protective layer; the isolation connecting layer is fixedly attached to the lower surface of the device layer; the support layer is fixedly attached to the lower surface of the isolation connecting layer, a first cavity is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity; the lower end of the first cavity extends to the lower surface of the isolation connecting layer to form a pressure introducing port, the upper end of the first cavity extends to the lower surface of the isolation connecting layer, and the first cavity is provided with a cavity wall extending up and down.

Description

Pressure chip and manufacturing method thereof

Technical Field

The invention relates to the technical field of sensors, in particular to a pressure chip and a manufacturing method thereof.

Background

Piezoresistive pressure sensors manufactured by the MEMS (Micro Electro Mechanical System) technology have the advantages of small volume, easy integration, reliable performance, capability of converting non-electrical signals into electrical signals, and the like, and are commonly used for pressure measurement in the fields of automobiles, aerospace, petrochemicals, biomedical and the like. The core element is a pressure chip, and the manufacturing method of the pressure chip is generally as follows: a piezoresistor structure is prepared on a silicon wafer, the piezoresistors are connected into a Wheatstone bridge structure by using a metal lead region or a heavily doped silicon lead region, and then a cavity is prepared on the back of the wafer, so that the silicon wafer is provided with a pressure-sensitive film layer. The piezoresistor is generally positioned at the edge of the film layer, and when the pressure-sensitive film is deformed under pressure, the stress generated at the edge of the pressure-sensitive film layer is the largest, so that the resistance value of the piezoresistor is changed, and the output voltage of the Wheatstone bridge is also changed according to the change of the resistance value.

As shown in fig. 1, in the prior art, the back cavity of the pressure chip is usually fabricated by wet etching, which makes the silicon wafer arranged along a specific crystal orientation during fabrication. Therefore, when wet etching is used, the side wall of the back cavity and the plane of the chip have a fixed angle alpha, so that the plane size of the pressure chip is larger, and the utilization rate of the wafer still has a room for improvement.

On the other hand, for an absolute pressure sensor, it is also necessary to provide a reference pressure chamber (typically a vacuum chamber) on the front surface of the pressure sensitive material. Since the pressure chip inevitably uses hydrogen as the process gas or the reaction gas in many cases during the manufacturing process, part of the residual hydrogen in the pressure chip is slowly accumulated in the reference pressure cavity; in addition, part of water vapor, nitrogen gas and the like also remain in the bonding process of the chip. These residual gases are slowly released during use, so that the pressure in the reference pressure chamber increases, and eventually the measurement results deviate.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a pressure chip and a manufacturing method thereof, so as to improve the utilization rate of a wafer.

To achieve the above object, the present invention provides a pressure chip, including:

the device layer is internally integrated with a pressure detection circuit in the upper surface layer, the pressure detection circuit is electrically connected with the outside through a metal electrode, and the pressure detection circuit comprises a piezoresistive element;

the protective layer is fixedly attached to the surface of the upper side of the device layer, and a contact hole for the upper side and the lower side of the metal electrode to penetrate through is formed in the protective layer;

the isolation connecting layer is fixedly attached to the lower surface of the device layer;

the support layer is fixedly attached to the lower surface of the isolation connecting layer, a first cavity is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity; the lower end of the first cavity extends to the lower surface of the isolation connecting layer to form a pressure introducing port, the upper end of the first cavity extends to the lower surface of the isolation connecting layer, and the first cavity is provided with a cavity wall extending up and down.

Preferably, the upper surface of the protective layer is provided with a cover, a sealed reference pressure chamber is formed between the cover and the protective layer, and the piezoresistive element is positioned right below the reference pressure chamber.

Preferably, a gas absorbent is arranged in the reference pressure cavity.

Preferably, the gas absorbent is a gas absorbing film; a side surface of the cover corresponding to the reference pressure chamber is recessed inward to form a first groove, and the gas absorption film is arranged at the bottom of the first groove.

Preferably, the material of the gas absorption film is Ti, zr or a hydrogen storage alloy.

Preferably, the middle part of the upper surface of the device layer is inwards recessed to form a second groove, and the edge of the upper surface of the device layer is relatively raised to form a third flange; the upper surface of the protective layer is recessed inwards to form a mounting groove, and the edge of the upper surface of the protective layer is raised relatively to form a fourth flange; the contact hole is arranged on the fourth flange; the cover is connected in the mounting groove.

Preferably, the outer edge of the lower end of the cover is matched with the bottom edge of the mounting groove.

The invention also provides a manufacturing method of the pressure chip, which comprises the following steps:

respectively manufacturing a supporting layer and a device layer on the upper side and the lower side of the isolation connecting layer, and manufacturing a shielding layer on the upper surface of the device layer;

manufacturing a pressure detection circuit on the surface layer of the device layer through an ion implantation process;

removing the shielding layer on the surface by etching and other processes;

manufacturing a protective layer on the upper surface of the device layer through epitaxial growth;

making a contact hole on the protective layer by patterned etching;

manufacturing a metal layer on the protective layer by a PVD (physical vapor deposition) process;

reserving a part corresponding to the contact hole on the metal layer through patterned etching, thereby forming a metal electrode;

sealing and connecting the cover to the upper surface of the protective layer to form a second cavity between the cover and the protective layer;

removing the redundant part of the cover by a DRIE process to expose the metal electrode; and forming a first cavity with cavity walls extending up and down on the lower surface of the supporting layer by a DRIE process.

Preferably, the cap is made by the following method:

manufacturing a first groove and a abdicating groove on the lower surface of the cover through a DRIE process;

making a gas absorption film made of a metal hydrogen storage material on the lower surface of the cover;

the gas absorption film is metal-etched to expose the second flange.

Preferably, the removal of the excess portion of the cover and the fabrication of the first cavity are removed by a DRIE process.

Drawings

FIG. 1 is a schematic diagram of a pressure chip in the prior art;

FIG. 2 is a schematic structural diagram of a pressure chip according to a first embodiment of the present invention;

FIGS. 3 to 13 are schematic structural diagrams of components of a pressure chip according to a first embodiment of the present invention in a step-by-step manufacturing process;

FIG. 14 is a schematic structural diagram of a pressure chip according to a second embodiment of the present invention;

FIG. 15 is a schematic structural diagram of a pressure chip according to a third embodiment of the present invention;

in the figure: 1. a support layer; 1a, a first cavity; 1b, a first flange; 1c, a cavity wall; 2. isolating the connection layer; 3. a device layer; 3a, resistance; 3b, a conductor; 3c, a contact electrode; 4. a shielding layer; 5. a protective layer; 5a, a contact hole; 5c, mounting grooves; 5d, a fourth flange; 6. a metal layer; 6a, a metal electrode; 6b, a metal electrode; 7. a cover; 70. a substrate; 7a, a first groove; 7b, a second flange; 7c, a yielding groove; 7d, a second cavity; 8. a gas absorbing film;

Detailed Description

The technical scheme of the invention is clearly and completely described in the following with reference to the accompanying drawings. The following examples are illustrative only and are not to be construed as limiting the invention. In the following description, the same reference numerals are used to designate the same or equivalent elements, and the repetitive description is omitted.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "inside", "outside", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships that the products of the present invention are conventionally placed in use, or the orientations or positional relationships that are conventionally understood by those skilled in the art, and are used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

In addition, the terms "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood as appropriate by those of ordinary skill in the art.

It should be further understood that the term "and/or" as used in this specification and the corresponding claims refers to any and all possible combinations of one or more of the listed items.

As shown in fig. 2. In the first embodiment of the present invention, the pressure chip includes the isolation connection layer 2 extending laterally, the device layer 3 is attached to the upper surface of the isolation connection layer 2, and the support layer 1 is attached to the lower surface of the isolation connection layer 2.

Wherein, the middle part of the back of the supporting layer 1 is recessed to form a first cavity 1a, and the edge part of the supporting layer 1 is opposite to form a first flange 1b. The first flange 1b is intended to be mounted on an external structure (e.g. a ceramic substrate). The cavity wall 1c of the first cavity 1a is inclined to the isolation connection layer 2.

The surface layer of the device layer 3 may be formed with a plurality of resistors 3a (i.e., piezoresistive elements) and conductors 3b for electrically connecting the resistors 3a by ion implantation. The plurality of resistors 3a are connected by a conductor 3b to form a detection circuit. In general, four resistors 3a may be connected to the conductor 3b in a wheatstone bridge. A protective layer 5 for insulating and protecting the resistor 3a and the conductor 3b is fixedly attached to the upper surface of the device layer 3.

The four resistors 3a face downward to the first cavity 1a, that is, the resistors 3a project into the first cavity 1a along the longitudinal direction. A cover 7 is fixed to the upper surface of the protective layer 5.

The protective layer 5 and the adjacent side of the lid 7 together define a second cavity 7d. The four resistors 3a face upward and directly face the first cavity 1a, that is, the resistors 3a are projected into the first cavity 1a along the longitudinal direction. Thus, the first cavity 1a and the second cavity 7d are both located on two sides of the device layer 3 to act on the device layer, and then the measuring circuit generates a measuring electric signal by the pressure difference between the two sides. The protective layer 5 is also provided with contact holes 5a and 5b penetrating the protective layer 5 vertically. The conductor 3b is electrically connected to the outside through the metal electrodes 6a, 6b to output a measurement electric signal.

In the present embodiment, a gas absorbent is disposed in the second cavity 7d. Wherein the gas absorbent may be a film-like material. For example, the lid 7 includes a base 70, and a central portion of a lower surface of the base 70 is recessed inward to form a first groove 7a, and the first groove 7a and an upper surface of the protective layer 5 together define a second chamber 7d (reference pressure chamber). The top of the inner wall of the first groove 7a is attached with a gas absorption film 8 which can absorb hydrogen. The gas absorbent can absorb one or more of hydrogen, water vapor and nitrogen. Preferably, the gas absorption membrane 8 may be made of a known hydrogen storage material. Meanwhile, in order to recess the portions of the base 70 corresponding to the metal electrodes 6a and 6b inward, portions (having a thickness equal to that of the metal layer 6) protruding upward from the metal electrodes 6a and 6b are formed to give way and protected in a subsequent process. In some variations, the gas absorbing film 8 may be Ti or Zr, which may also absorb some of the hydrogen gas and water vapor simultaneously.

Preferably, the hydrogen storage material may be a metallic material such as rare earth-based, titanium-based, zirconium-based, and magnesium-based hydrogen storage alloys. These metal materials can be conveniently formed on the cover 7 or the protective layer 5 by vacuum evaporation or physical vapor deposition. These alloys are currently used for storage of hydrogen energy, but when used in the present invention, they are only capable of absorbing small amounts of hydrogen. In particular, the second chamber 7d may be a vacuum chamber, and in this case, when a small amount of hydrogen gas can be absorbed, the measurement result deviation can be greatly reduced.

For silicon, which is a general semiconductor material, the support layer 1 and the device layer 3 may be silicon, and the isolation connection layer 2 and the protection layer 5 may be silicon oxide or silicon nitride.

As shown in fig. 3 to 13, in the present embodiment, the manufacturing method of the pressure chip is described by taking a silicon semiconductor material as an example:

(I) respectively manufacturing a supporting layer 1 (Silicon layer) and a device layer 3 (Silicon layer) On the upper side and the lower side of an isolation connecting layer 2 (Silicon oxide layer), and manufacturing a shielding layer 4 (Silicon oxide layer) On the upper surface of the device layer 3 to form an SOI (Silicon-On-Insulator) structure, as shown in figure 3;

the SOI structure may be fabricated by SIMOX (separation by implantation of Oxygen) technology, WB (wafer bonding), or Smart-cut (Smart-cut) technology. Among them, smart-cut technology has become the most competitive technology for fabricating SOI structures, in which the delamination of the crystal layer is performed by hydrogen gas, so that hydrogen gas is also introduced during the process of completely breaking the hydrogen implantation wafer from the particle implantation layer.

(II) carrying out P-type doping on a first region of the surface layer of the device layer 3 through an ion implantation process to manufacture a resistor 3a, and then carrying out P-type doping on a partial region of the first region to manufacture a conductor 3b; by the ion implantation process, a contact electrode 3c connected to the conductor 3b is formed on the surface layer of the device layer 3, as shown in fig. 4; wherein, the conductor 3b can also be directly formed by heavy doping;

(III) removing the shielding layer 4 on the surface by etching or the like, as shown in FIG. 5;

(IV) manufacturing a protective layer 5 on the upper surface of the device layer 3 by epitaxial growth, as shown in FIG. 6;

(v) forming contact holes 5a, 5b in the protective layer 5 by patterned etching, as shown in fig. 7;

(vi) forming a metal layer 6 on the protective layer 5 by a PVD (physical vapor deposition) process, as shown in fig. 8;

(vii) leaving portions corresponding to the contact holes 5a, 5b on the metal layer 6 by patterned etching, thereby forming metal electrodes 6a, 6b, as shown in fig. 9;

(viii) the lid 7 is hermetically attached to the upper surface of the protective layer 5 by welding or the like to form the second chamber 7d described above, as shown in fig. 10.

Wherein the lid 7 may be made from a silicon wafer: first, a first recess 7a and a relief groove 7c are formed in the lower surface of the lid 7 by a DRIE (deep reactive ion etching) process, as shown in fig. 11; then, a gas absorption film 8 made of a hydrogen absorbing alloy is formed on the lower surface of the lid 7, as shown in fig. 12; then, the gas absorption film 8 is subjected to metal etching to expose the second flange 7b to be bonded to the protective layer, as shown in fig. 13;

(ix) removing the excess portion of the cover 7 by DRIE to expose the metal electrodes 6a, 6b; in addition, a first cavity 1a with an inclined sidewall is formed on the lower surface of the support layer 1 through a wet etching process, so that the pressure chip shown in fig. 2 is obtained.

The patterned etching is etching performed in a predetermined pattern under the condition of a mask technique such as photolithography.

As shown in fig. 14, in the second embodiment of the present invention, the first chamber 1a can be formed by the DRIE process as well, and the first chamber 1a having the longitudinally extending chamber walls 1c can be formed due to the anisotropy of the DRIE process, in addition to the first embodiment. Therefore, the transverse size (width) of the supporting layer 1 can be obviously reduced on the premise of ensuring the minimum limit for effectively installing the supporting layer 1 on an external base body, and the utilization rate of the wafer is improved; wherein, the cover 7 can also be processed by DRIE process similar to the supporting layer 1, thereby saving the purchase cost of equipment.

As shown in fig. 15, on the basis of the above embodiments, in the third embodiment of the present invention, the middle portion of the upper surface of the device layer 3 is recessed inward to form a second groove, the edge of the upper surface of the device layer 3 is raised relative to the third flange, and the second groove can be formed by DRIE process. Accordingly, the upper surface of the protective layer 5 is recessed inward to form a mounting groove 5c, and the edge of the upper surface of the protective layer 5 is raised relatively to form a fourth flange 5d. The contact holes 5a, 5b are provided on the fourth flange 5d. The cover 7 is coupled in the mounting groove 5 c. In this way, the height of the top of the cover 7 protruding above the upper surface of the protective layer 5 can be reduced, thereby reducing the risk of the cover 7 falling off during assembly or use. Preferably, the outer edge of the lower end of the cover 7 is fitted into the bottom edge of the mounting groove 5c, thereby facilitating positioning.

In addition to the above embodiments, in the fourth embodiment of the present invention, since the gas absorbent is omitted from the cover 7, the steps of forming the gas absorbent film and etching the metal can be omitted when the pressure chip is formed.

The scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the present disclosure.

Claims (10)

1. A pressure chip, comprising:

the device comprises a device layer (3), wherein a pressure detection circuit is integrated in the upper surface layer of the device layer, the pressure detection circuit is electrically connected with the outside through metal electrodes (6 a and 6 b), and the pressure detection circuit comprises a piezoresistive element;

a protective layer (5) fixedly attached to the upper surface of the device layer (3), and contact holes (5 a, 5 b) for the upper and lower sides of the metal electrodes (6 a, 6 b) to penetrate are formed in the protective layer;

the isolation connecting layer (2) is fixedly attached to the lower surface of the device layer (3);

the support layer (1) is fixedly attached to the lower surface of the isolation connecting layer (2), a first cavity (1 a) is arranged in the support layer, and the piezoresistive element is positioned right above the first cavity (1 a); the lower end of the first cavity (1 a) extends to the lower surface of the isolation connecting layer (2) to form a pressure introducing port, the upper end of the first cavity (1 a) extends to the lower surface of the isolation connecting layer (2), and the first cavity (1 a) is provided with a cavity wall (1 c) extending up and down.

2. A pressure chip according to claim 1, characterised in that the upper surface of the protective layer (5) is provided with a cover (7), a sealed reference pressure chamber being formed between the cover (7) and the protective layer (5), and the piezoresistive element being located directly below the reference pressure chamber.

3. The pressure chip of claim 2, wherein a gas absorbent is disposed within the reference pressure chamber.

4. A pressure chip according to claim 3, characterised in that the gas absorbent is a gas-absorbent membrane (8); one side surface of the cover (7) corresponding to the reference pressure cavity is recessed inwards to form a first groove (7 a), and the gas absorption film (8) is arranged at the bottom of the first groove (7 a).

5. A pressure chip according to claim 4, characterised in that the material of the gas-absorbing membrane (8) is Ti, zr or a hydrogen storage alloy.

6. A pressure chip according to any one of claims 1 to 5, characterized in that the middle of the upper surface of the device layer (3) is recessed inwards to form a second groove, and the edge of the upper surface of the device layer (3) is raised relative to the third flange; the upper surface of the protective layer (5) is recessed inwards to form a mounting groove (5 c), and the edge of the upper surface of the protective layer (5) is raised relatively to form a fourth flange (5 d); contact holes (5 a, 5 b) are provided on the fourth flange (5 d); the cover (7) is connected in the mounting groove (5 c).

7. A pressure chip according to claim 6, characterised in that the lower outer edge of the lid (7) coincides with the bottom edge of the mounting groove (5 c).

8. A manufacturing method of a pressure chip is characterized by comprising the following steps:

respectively manufacturing a support layer (1) and a device layer (3) on the upper side and the lower side of an isolation connection layer (2), and manufacturing a shielding layer (4) on the upper surface of the device layer (3);

manufacturing a pressure detection circuit on the surface layer of the device layer (3) through an ion implantation process;

removing the shielding layer (4) on the surface by etching and other processes;

manufacturing a protective layer (5) on the upper surface of the device layer (3) through epitaxial growth;

making contact holes (5 a, 5 b) on the protective layer (5) by patterned etching;

manufacturing a metal layer (6) on the protective layer (5) by a PVD process;

keeping parts corresponding to the contact holes (5 a, 5 b) on the metal layer (6) through patterned etching, thereby forming metal electrodes (6 a, 6 b);

the cover (7) is hermetically connected with the upper surface of the protective layer (5), so that a second cavity (7 d) is formed between the cover and the protective layer;

removing the excess part of the cover (7) by DRIE process to expose the metal electrodes (6 a, 6 b); and forming a first cavity (1 a) with cavity walls (1 c) extending up and down on the lower surface of the support layer (1) by a DRIE process.

9. Method for manufacturing a pressure chip according to claim 8, characterized in that the cover (7) is made by:

a first groove (7 a) and an abdicating groove (7 c) are manufactured on the lower surface of the cover (7) through a DRIE process;

a gas absorption film (8) made of a metal hydrogen storage material is made on the lower surface of the cover (7);

the gas absorption film (8) is subjected to metal etching to expose the second flange (7 b).

10. Method for manufacturing a pressure chip according to any of the claims 8 to 9, characterized in that the removal of the excess part of the cover (7) and the manufacture of the first cavity (1 a) are removed by means of a DRIE process.

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