CN219247850U

CN219247850U - Anti-interference optical communication module

Info

Publication number: CN219247850U
Application number: CN202321313893.6U
Authority: CN
Inventors: 杜秀君; 黄应强; 代艳霞; 梅容芳; 唐思均
Original assignee: Yibin Vocational and Technical College
Current assignee: Yibin Vocational and Technical College
Priority date: 2023-05-29
Filing date: 2023-05-29
Publication date: 2023-06-23
Anticipated expiration: 2033-05-29

Abstract

The utility model discloses an anti-interference optical communication module, which belongs to the technical field of optical communication, and comprises a carrier module, a four-phase two-phase conversion module, a data wireless transceiver module, an FPGA chip and a FLASH memory; the output end of the data wireless receiving and transmitting module is connected with the carrier module, the output end of the carrier module is connected with the input end of the four-phase two-phase conversion module, the four-phase two-phase conversion module is electrically connected with the FPGA chip, and the FPGA chip is interactively connected with the FLASH memory; the output end of the zero crossing detection circuit is connected with the input end of the signal modulation coupling circuit, and the output end of the signal modulation coupling circuit is connected with the input end of the signal carrier demodulation circuit; the four-phase two-phase conversion module adopts a QDI circuit model, two-phase level double-track coding and four-phase double-track coding; the utility model can realize the aims of good anti-interference effect and high signal transmission efficiency on the premise of ensuring the accuracy of data.

Description

Anti-interference optical communication module

Technical Field

The utility model belongs to the technical field of optical communication, and particularly relates to an anti-interference optical communication module.

Background

In recent years, china has developed rapidly, and optical communication technology has received much attention. The optical communication has the advantages of large communication capacity, long relay distance, good confidentiality, strong adaptability, small volume, light weight, abundant raw material sources and low potential price, thereby being widely applied. The advent of optical communication networks is an advancement in the development of communication networks. The optical communication network has the characteristics of lower energy consumption and larger channel capacity, and communication energy consumption is reduced and communication speed is improved mainly through the application of optical fiber technology. The optical communication network is composed of three parts, including an access network, a metropolitan area network and a core network, wherein the access network and the metropolitan area network belong to an edge network. The system comprises an access layer and a convergence layer, wherein the access layer is directly connected with a backbone network and can provide outward network connection; and the convergence layer is responsible for the connection of network traffic convergence devices in the area. The application of the stable local area network technology comprises metropolitan area Ethernet, optical wavelength division multiplexing rings and synchronous optical networks; the core network is a core component of an optical communication network, and has a very wide application range and is distributed worldwide. The core network is typically an internet type structure, and traffic data collected from the edge network is transmitted. As long as a network interface is arranged between the metropolitan area network and the core network to distribute and collect data traffic, users of each metropolitan area network can realize long-distance network communication by using the core network. In increasingly complex electromagnetic environments, communication channels are often subject to interference from noise of different origins when transmitting signals, resulting in the difficulty in distinguishing valid information from the received signals. The prior anti-interference method for the communication channel mainly realizes anti-interference at a receiving end by performing processing such as transformation, coding and the like on signals transmitted in the channel on a time domain and a frequency domain from the perspective of a software algorithm. The method has high complexity, and causes high error rate in the channel, so that the accuracy of the data is difficult to ensure. Therefore, it is necessary to provide an anti-interference optical communication module with good anti-interference effect and high signal transmission efficiency on the premise of ensuring data accuracy.

Disclosure of Invention

The utility model can realize the aims of good anti-interference effect and high signal transmission efficiency on the premise of ensuring the accuracy of data.

The anti-interference optical communication module comprises a carrier module 1, a four-phase two-phase conversion module 2, a data wireless receiving and transmitting module 3, an FPGA chip 4 and a FLASH memory 5; the output end of the data wireless receiving and transmitting module 3 is connected with the carrier module 1, the output end of the carrier module 1 is connected with the input end of the four-phase two-phase conversion module 2, the four-phase two-phase conversion module 2 is electrically connected with the FPGA chip 4, and the FPGA chip 4 is interactively connected with the FLASH memory 5.

Further, the carrier module 1 includes a zero-crossing detection circuit 11, a signal modulation coupling circuit 12, and a signal carrier demodulation circuit 13, where an output end of the zero-crossing detection circuit 11 is connected to an input end of the signal modulation coupling circuit 12, and an output end of the signal modulation coupling circuit 12 is connected to an input end of the signal carrier demodulation circuit 13.

Further, the four-phase two-phase conversion module 2 is a QDI circuit model, a two-phase level two-rail code and a four-phase two-rail code, wherein the output end of the two-phase level two-rail code is connected with the input end of the QDI circuit model, and the output end of the QDI circuit model is connected with the input end of the four-phase two-rail code.

Further, the zero-crossing detection circuit 11 comprises an alternating current optocoupler, an INP port device, a self-bias chip, a current amplifier, and a constant source current compression device; the output end of the alternating current optocoupler is connected with a self-bias chip, the self-bias chip is in interactive connection with a constant source current compression device, the output end of the constant source current compression device is connected with a current amplifier, and the output end of the current amplifier is connected with INP port equipment.

The utility model has the beneficial effects that:

(1) The utility model can better identify noise through the carrier module and the four-phase two-phase conversion module, thereby processing.

(2) The utility model integrally improves the anti-interference capability and improves the channel communication quality by processing the communication channel.

(3) The anti-interference optical communication module can effectively reduce the error rate in a channel and has stable anti-interference capability.

Drawings

FIG. 1 is a block diagram of an anti-interference optical communication module according to the present utility model;

FIG. 2 is a diagram of a zero crossing detection circuit of an anti-interference optical communication module according to the present utility model;

FIG. 3 is a circuit diagram of an anti-interference optical communication module according to the present utility model;

fig. 4 is a circuit diagram of a plug connector of an anti-interference optical communication module according to the present utility model.

In the figure, a 1-carrier module, an 11-zero crossing detection circuit, a 12-signal modulation coupling circuit, a 13-signal carrier demodulation circuit, a 2-four-phase two-phase conversion module, a 3-data wireless transceiver module, a 4-FPGA chip and a 5-FLASH memory.

Detailed Description

In order that the utility model may be readily understood, a more complete description of the utility model will be rendered by reference to the appended drawings. Exemplary embodiments of the present utility model are illustrated in the accompanying drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model.

Example 1: as shown in fig. 1-4, the anti-interference optical communication module includes a carrier module 1, a four-phase two-phase conversion module 2, a data wireless transceiver module 3, an FPGA chip 4, and a FLASH memory 5. The output end of the data wireless receiving and transmitting module 3 is connected with the carrier module 1, and four data receiving and transmitting modes are included, wherein the four data receiving and transmitting modes comprise a power-down mode, a standby mode, a receiving mode and a transmitting mode, and each mode adopts pins with the same function.

The carrier module 1 comprises a zero-crossing detection circuit 11, a signal modulation coupling circuit 12 and a signal carrier demodulation circuit 13, wherein the output end of the zero-crossing detection circuit 11 is connected with the input end of the signal modulation coupling circuit 12, and the output end of the signal modulation coupling circuit 12 is connected with the input end of the signal carrier demodulation circuit 13.

The zero-crossing detection circuit 11 comprises an alternating current optocoupler, INP port equipment, a self-bias chip, a current amplifier and a constant source current compression device; the output end of the alternating current optocoupler is connected with a self-bias chip, the self-bias chip is in interactive connection with a constant source current compression device, the output end of the constant source current compression device is connected with a current amplifier, and the output end of the current amplifier is connected with INP port equipment.

The output end of the carrier module 1 is connected with the input end of the four-phase two-phase conversion module 2. The four-phase two-phase conversion module 2 is a QDI circuit model, a two-phase level double-track code and a four-phase double-track code. The output end of the two-phase level double-track code is connected with the input end of the QDI circuit model, and the output end of the QDI circuit model is connected with the input end of the four-phase double-track code. Two-phase level double-track coding adopts LEDR coding, and one bit of data is represented by two coded physical lines. Four-phase double-track coding improves NC encoders and converts the LEDR coding into an improved NC encoder using the QDI circuit model. NC encoders are a common absolute encoder naming convention in which the NC encoder can memorize the number of encoder turns through a code wheel. The conversion between the four-section handshake protocol and the two-section handshake protocol is realized by using a QDI circuit model, two-phase level double-track coding and four-phase double-track coding. The four-phase two-phase conversion module 2 is electrically connected with the FPGA chip 4, and the FPGA chip 4 is interactively connected with the FLASH memory 5. And an embedded access point with anti-interference channels is built on the FPGA chip 4 so as to realize dynamic selection of communication channels.

The FPGA chip 4 adopts floating point operation, so that the dynamic range and operation precision of data are ensured, and the waste of operation resources is reduced. When executing the interrupt portion of the Bootloader program, the interrupt service jump is defined according to an interrupt vector table in the form of a floating point number, so as to adjust updating in time when the communication channel changes. The kernel address is copied from the FLASH memory 5, and the storage address of the instruction is copied by using the void function jump instruction value. After the root file is mounted on the FPGA kernel, a corresponding image file is constructed according to the file directory. After the dynamic selection program is programmed into the FPGA through the JTAG interface, the program in the CS layer in the FPGA is accessed upwards when the communication channel is dynamically selected.

The working principle of the utility model is as follows:

the data wireless transceiver module 3 receives data to be transmitted. After the carrier module 1 receives the data, the zero-crossing detection circuit 11 performs zero-crossing detection and corrects the zero-crossing detection waveform. Meanwhile, the alternating current optocoupler protects and isolates the circuit. The four-phase two-phase conversion module 2 realizes conversion between a four-segment handshake protocol and a two-segment handshake protocol by using a QDI circuit model and two-phase level two-rail coding and four-phase two-rail coding. The logic 0 of the four-phase double-track code is represented by 00; logical 1 s are denoted by 01, 10, and the NC encoder is modified and the LEDR encoding is transcoded using the QDI circuit model to a modified NC encoder.

The FPGA chip 4 adopts floating point number operation, so that the dynamic range and operation precision of data are ensured, and the waste of operation resources is reduced. When executing the interrupt portion of the Bootloader program, the interrupt service jump is defined according to an interrupt vector table in the form of a floating point number, so as to adjust updating in time when the communication channel changes. The FPGA chip 4 copies the kernel address from the FLASH memory 5, and uses the void function jump instruction value to copy the storage address of the instruction. After the root file is mounted on the FPGA kernel, a corresponding image file is constructed according to the file directory. After the dynamic selection program is programmed into the FPGA through the JTAG interface, the program in the CS layer in the FPGA is accessed upwards when the communication channel is dynamically selected. And carrying out channel estimation by using the minimum mean square error of the transmitted signal and the received signal to obtain estimated values of all communication channels in the communication network. When in multi-channel communication, adjacent channels mutually compare the correlation value between the information spreading sequence generated by spreading the spreading code period and the original signal, the channel with larger correlation value is output to be compared again, and the above process is repeated to obtain the expected source signal after separation processing in the final channel, thus realizing the anti-interference processing on the communication channel.

The embodiments of the present utility model have been described above with reference to the accompanying drawings, but the present utility model is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present utility model and the scope of the claims, which are to be protected by the present utility model.

Claims

1. An anti-interference optical communication module, characterized in that: the anti-interference optical communication module comprises a carrier module (1), a four-phase two-phase conversion module (2), a data wireless transceiver module (3), an FPGA chip (4) and a FLASH memory (5); the output end of the data wireless receiving and transmitting module (3) is connected with the carrier module (1), the output end of the carrier module (1) is connected with the input end of the four-phase two-phase conversion module (2), the four-phase two-phase conversion module (2) is electrically connected with the FPGA chip (4), and the FPGA chip (4) is in interactive connection with the FLASH memory (5).

2. The anti-interference optical communication module according to claim 1, wherein: the carrier module (1) comprises a zero-crossing detection circuit (11), a signal modulation coupling circuit (12) and a signal carrier demodulation circuit (13), wherein the output end of the zero-crossing detection circuit (11) is connected with the input end of the signal modulation coupling circuit (12), and the output end of the signal modulation coupling circuit (12) is connected with the input end of the signal carrier demodulation circuit (13).

3. The anti-interference optical communication module according to claim 1, wherein: the four-phase two-phase conversion module (2) is a QDI circuit model, a two-phase level double-track code and a four-phase double-track code, wherein the output end of the two-phase level double-track code is connected with the input end of the QDI circuit model, and the output end of the QDI circuit model is connected with the input end of the four-phase double-track code.

4. The anti-interference optical communication module according to claim 2, wherein: the zero-crossing detection circuit (11) comprises an alternating current optocoupler, INP port equipment, a self-bias chip, a current amplifier and a constant source current compression device; the output end of the alternating current optocoupler is connected with a self-bias chip, the self-bias chip is in interactive connection with a constant source current compression device, the output end of the constant source current compression device is connected with a current amplifier, and the output end of the current amplifier is connected with INP port equipment.