CN219226293U - Display panel - Google Patents
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- CN219226293U CN219226293U CN202223602793.3U CN202223602793U CN219226293U CN 219226293 U CN219226293 U CN 219226293U CN 202223602793 U CN202223602793 U CN 202223602793U CN 219226293 U CN219226293 U CN 219226293U
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Abstract
The present utility model provides a display panel, comprising: the device comprises a first substrate, a second substrate and a first electrode, wherein a conductive layer group is arranged on one side surface of the first substrate, and comprises a first conductive layer and a second conductive layer which are arranged at intervals; the insulating layer is positioned on one side of the first substrate, the insulating layer is provided with a first opening and a second opening which are arranged at intervals, the first opening is positioned above the first conductive layer, and the second opening is positioned above the second conductive layer; a first bonding layer located in the first opening, the first bonding layer being located on an upper surface of the first conductive layer; the second bonding layer is positioned in the second opening and is positioned on the upper surface of the second conductive layer; micro-LED chip, micro-LED chip includes: a P-type electrode and an N-type electrode; the P-type electrode is in contact with the first bonding layer and the N-type electrode is in contact with the second bonding layer. The display panel can avoid short circuit between the first conductive layer and the second conductive layer.
Description
Technical Field
The utility model relates to the technical field of display, in particular to a display panel.
Background
Light emitting diodes (Light Emitting Diode, LEDs) are an important optoelectronic semiconductor component. The light emitting diode has the advantages of low power consumption, small size, high brightness, easy matching with an integrated circuit, high reliability and the like, and is widely used as a light source. With the development of technology, micro-LEDs have been applied in the fields of display, optical communication, indoor positioning, biology and medical treatment, and are expected to be further expanded to multiple fields of wearable/implantable devices, augmented reality/virtual reality, vehicle-mounted display, ultra-large display, optical communication/optical interconnection, medical detection, intelligent car lights, space imaging and the like, and have clear and considerable market prospects. The light emitting diode is manufactured by connecting the P-type electrode of the Mi cro-LED chip with the first conductive layer of the first substrate and connecting the N-type electrode of the Mi cro-LED chip with the second conductive layer of the first substrate through a bonding process, but in the prior art, the first conductive layer and the second conductive layer in the first substrate are not separated by an insulating layer, so that short circuits between the first conductive layer and the second conductive layer are easily caused by melting and flowing of bonding materials during the bonding process, and therefore, it is necessary to provide a display panel capable of avoiding short circuits between the first conductive layer and the second conductive layer.
Disclosure of Invention
Therefore, the technical problem to be solved by the utility model is to overcome the defect that the first conductive layer and the second conductive layer of the display panel in the prior art are easy to short-circuit, so as to provide the display panel.
The present utility model provides a display panel, comprising: the device comprises a first substrate, a second substrate and a first electrode, wherein a conductive layer group is arranged on one side surface of the first substrate, and comprises a first conductive layer and a second conductive layer which are arranged at intervals; the insulating layer is positioned on one side of the first substrate, a first opening and a second opening are arranged in the insulating layer at intervals, the first opening is positioned above the first conductive layer, and the second opening is positioned above the second conductive layer; a first bonding layer located in the first opening, the first bonding layer being located on an upper surface of the first conductive layer; a second bonding layer located in the second opening, the second bonding layer being located on an upper surface of the second conductive layer; a Mi cro-LED chip, the Mi cro-LED chip comprising: a P-type electrode and an N-type electrode; the P-type electrode is in contact with the first bonding layer, and the N-type electrode is in contact with the second bonding layer.
Optionally, the Mi cro-LED chip further includes: a chip body; the P-type electrode and the N-type electrode are both positioned on part of the surface of one side of the chip body; the P-type electrode is embedded in the first opening, and the N-type electrode is embedded in the second opening; the chip body is in contact with the top surface of part of the insulating layer.
Optionally, the chip body includes: an N-type semiconductor layer; an active layer located on a part of the surface of one side of the N-type semiconductor layer; the P-type semiconductor layer is positioned on one side surface of the active layer, which is away from the N-type semiconductor layer; the P-type electrode is positioned on one side surface of part of the P-type semiconductor layer, which is away from the active layer; the N-type electrode is positioned on the active layer, the P-type semiconductor layer and part of the surface of one side of the N-type semiconductor layer at the side part of the P-type electrode; the P-type semiconductor layer around the P-type electrode is in contact with a top surface of the insulating layer around the first opening.
Optionally, the width of the first opening gradually increases from the bottom to the top of the first opening; the width of the second opening gradually increases from the bottom to the top of the second opening.
Optionally, the cross-sectional pattern of the first opening in the direction perpendicular to the surface of the first substrate comprises an inverted trapezoid, and the cross-sectional pattern of the second opening in the direction perpendicular to the surface of the first substrate comprises an inverted trapezoid.
Optionally, the distance between the first conductive layer and the second conductive layer is 5 μm to 20 μm.
Optionally, the thickness of the insulating layer is 0.5 μm to 10 μm.
Optionally, the insulating layer is a single-layer structure, and the insulating layer is a silicon dioxide insulating layer, a polyimide insulating layer, a silicon nitride insulating layer or a photoresist insulating layer; alternatively, the insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked; the first sub-insulating layer is a silicon dioxide sub-insulating layer, the second sub-insulating layer is a silicon nitride sub-insulating layer, or the first sub-insulating layer is a silicon nitride sub-insulating layer, and the second sub-insulating layer is a silicon dioxide sub-insulating layer.
The technical scheme of the utility model has the following advantages:
the utility model provides a display panel, one side surface of a first substrate is provided with a conductive layer group, the conductive layer group comprises a first conductive layer and a second conductive layer which are arranged at intervals, the insulating layer is provided with a first opening and a second opening which are arranged at intervals, the first opening is positioned above the first conductive layer, the second opening is positioned above the second conductive layer, the first bonding layer is positioned in the first opening, the second bonding layer is positioned in the second opening, a P-type electrode of a Micro-LED chip is contacted with the first bonding layer, an N-type electrode of the Micro-LED chip is contacted with the second bonding layer, the first opening can be used for limiting the P-type electrode, improving accurate alignment of the P-type electrode and the first bonding layer, the second opening can be used for limiting the N-type electrode, improving accurate alignment of the N-type electrode and the second bonding layer, the first opening and the second opening can be used for preventing the Micro-LED chip from being transversely offset, and the insulating layer between the first opening and the second opening can be used for preventing the first conducting layer and the second conducting layer from being short-circuited, so that the display panel can be used for preventing the first conducting layer and the second conducting layer from being short-circuited.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the utility model;
FIG. 2 is a flowchart of a method for manufacturing a display panel according to an embodiment of the utility model;
fig. 3 to 9 are schematic structural diagrams illustrating a manufacturing process of a display panel according to an embodiment of the utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.
The present embodiment provides a display panel, referring to fig. 1, including:
a first substrate 1, wherein a conductive layer group is arranged on one side surface of the first substrate 1, and the conductive layer group comprises a first conductive layer 21 and a second conductive layer 22 which are arranged at intervals;
an insulating layer 3 located on one side of the first substrate 1, wherein the insulating layer 3 has a first opening and a second opening that are arranged at intervals, the first opening is located above the first conductive layer 21, and the second opening is located above the second conductive layer 22;
a first bonding layer 41 located in the first opening, the first bonding layer 41 being located on an upper surface of the first conductive layer 21; a second bonding layer 42 located in the second opening, the second bonding layer 42 being located on an upper surface of the second conductive layer 22;
a Micro-LED chip, the Micro-LED chip comprising: a P-type electrode 51 and an N-type electrode 52; the P-type electrode 51 is in contact with the first bonding layer 41, and the N-type electrode 52 is in contact with the second bonding layer 42.
In the display panel provided in this embodiment, the conductive layer group is disposed on one side surface of the first substrate 1, the conductive layer group includes a first conductive layer 21 and a second conductive layer 22 disposed at intervals, the insulating layer 3 includes a first opening and a second opening disposed at intervals, the first opening is located above the first conductive layer 21, the second opening is located above the second conductive layer 22, the first bonding layer 41 is located in the first opening, the second bonding layer 42 is located in the second opening, the N-type electrode 52 of the Micro-LED chip is in contact with the second bonding layer 42, the first opening can limit the P-type electrode 51, the P-type electrode 51 is improved to be aligned with the first bonding layer 41, the second opening can limit the N-type electrode 52, the first opening can be improved to be aligned with the second bonding layer 52, the second opening can be prevented from being aligned with the second bonding layer, and short circuit can be avoided between the second opening and the second bonding layer, and the second opening can be prevented from being shorted with the first bonding layer, and the second opening can avoid the short circuit between the second bonding layer and the second bonding layer.
In one embodiment, the distance between the first conductive layer 21 and the second conductive layer 22 is 5 μm to 20 μm, for example 15 μm, if the distance between the first conductive layer and the second conductive layer is less than 5 μm, the difficulty of the process for preparing the first conductive layer and the second conductive layer may be increased; if the distance between the first conductive layer and the second conductive layer is greater than 20 μm, it is not advantageous to improve the integration of the display panel.
In one embodiment, the material of the first conductive layer 21 includes: molybdenum or indium tin oxide; the materials of the second conductive layer 22 include: molybdenum or indium tin oxide.
In another embodiment, the first conductive layer 21 includes: a titanium conductive layer, an aluminum conductive layer and a titanium conductive layer which are sequentially laminated on the surface of the first substrate; the second conductive layer 22 includes: and a titanium conductive layer, an aluminum conductive layer and a titanium conductive layer which are sequentially laminated on the surface of the first substrate.
In another embodiment, the first conductive layer 21 includes: a titanium conductive layer, an aluminum conductive layer, a titanium conductive layer and a nickel conductive layer which are sequentially laminated on the surface of the first substrate; the second conductive layer 22 includes: and a titanium conductive layer, an aluminum conductive layer, a titanium conductive layer and a nickel conductive layer are sequentially laminated on the surface of the first substrate.
In another embodiment, the first conductive layer 21 includes: an indium tin oxide conductive layer, a silver conductive layer and an indium tin oxide conductive layer which are sequentially laminated on the surface of the first substrate; the second conductive layer 22 includes: and an indium tin oxide conductive layer, a silver conductive layer and an indium tin oxide conductive layer which are sequentially laminated on the surface of the first substrate.
In one embodiment, the thickness of the insulating layer 3 is 0.5 μm to 10 μm, for example, 3 μm, and if the thickness of the insulating layer is less than 0.5 μm, the depths of the first opening and the second opening formed are too small, and the effect of the insulating layer between the first opening and the second opening to avoid the occurrence of short circuit between the first conductive layer and the second conductive layer is not obvious; if the thickness of the insulating layer is greater than 10 μm, the P-type electrode 51 may not be easily contacted with the first bonding layer 41, and the N-type electrode 52 may not be easily contacted with the second bonding layer 42.
In one embodiment, the insulating layer of the insulating layer 3 is a single-layer structure, and the insulating layer is a silicon oxide insulating layer, a polyimide insulating layer, a silicon nitride insulating layer, or a photoresist insulating layer.
In another embodiment, the insulating layer includes a stacked first sub-insulating layer and second sub-insulating layer; the first sub-insulating layer is a silicon dioxide sub-insulating layer, the second sub-insulating layer is a silicon nitride sub-insulating layer, or the first sub-insulating layer is a silicon nitride sub-insulating layer, and the second sub-insulating layer is a silicon dioxide sub-insulating layer.
In one embodiment, the Micro-LED chip further comprises: a chip body; the P-type electrode 51 and the N-type electrode 52 are both positioned on a part of the surface of one side of the chip body; the P-type electrode 51 is embedded in the first opening, and the N-type electrode 52 is embedded in the second opening; the chip body is in contact with a portion of the top surface of the insulating layer 3.
In one embodiment, the width of the first opening increases gradually from the bottom to the top of the first opening; the width of the second opening gradually increases from the bottom to the top of the second opening.
In one embodiment, the first opening has a cross-sectional profile perpendicular to the first substrate surface that includes an inverted trapezoid, and the second opening has a cross-sectional profile perpendicular to the first substrate surface that includes an inverted trapezoid.
In other embodiments, the cross-sectional pattern of the first opening in the direction perpendicular to the surface of the first substrate may further include, without limitation, other patterns with wide upper part and narrow lower part, and the cross-sectional pattern of the second opening in the direction perpendicular to the surface of the first substrate may further include, without limitation, other patterns with wide upper part and narrow lower part.
In one embodiment, the chip body includes: an N-type semiconductor layer 501; an active layer 502 located on a part of the surface of the N-type semiconductor layer 501; a P-type semiconductor layer 503 located on a side surface of the active layer 502 facing away from the N-type semiconductor layer 501; the P-type electrode 51 is located on a surface of a portion of the P-type semiconductor layer 503 facing away from the active layer 502; the N-type electrode 52 is located on the active layer 502, the P-type semiconductor layer 503, and a part of the surface of the P-type electrode 51 on the N-type semiconductor layer 501 side; the P-type semiconductor layer 503 around the P-type electrode 51 is in contact with the top surface of the insulating layer 3 around the first opening.
In one embodiment, the difference between the total area of the side surface of the P-type semiconductor layer 503 facing away from the active layer 502 and the projected area of the P-type electrode 51 on the surface of the P-type semiconductor layer 503 is 50 μm 2 ～200μm 2 For example 50. Mu.m 2 、80μm 2 、100μm 2 、120μm 2 、150μm 2 、180μm 2 Or 200 μm 2 。
The embodiment also provides a method for manufacturing a display panel, referring to fig. 2, including the following steps:
step S1: providing a first substrate, wherein a conductive layer group is arranged on one side surface of the first substrate, and the conductive layer group comprises a first conductive layer and a second conductive layer which are arranged at intervals;
step S2: forming an insulating layer on one side of the first substrate with a conductive layer group, wherein the insulating layer is provided with a first opening and a second opening which are arranged at intervals, the bottom of the first opening exposes the first conductive layer, and the bottom of the second opening exposes the second conductive layer;
step S3: forming a first bonding layer in the first opening and forming a second bonding layer in the second opening;
step S4: providing a second substrate, wherein one side of the second substrate is provided with a Micro-LED chip, and the Micro-LED chip comprises: a P-type electrode and an N-type electrode;
step S5: and bonding the P-type electrode and the first bonding layer and bonding the N-type electrode and the second bonding layer at the same time.
According to the manufacturing method of the display panel, in the process of bonding the P-type electrode and the first bonding layer and bonding the N-type electrode and the second bonding layer, the insulating layer between the first opening and the second opening can avoid short circuit between the first conductive layer and the second conductive layer caused by melting and flowing of the first bonding layer and the second bonding layer in the bonding process. Therefore, the manufacturing method of the display panel can avoid short circuit between the first conductive layer and the second conductive layer.
The method of manufacturing the display panel is described in detail below with reference to fig. 3 to 9.
Referring to fig. 3 and 4, a first substrate 1 is provided, and a conductive layer group 2 is provided on one side surface of the first substrate 1, and the conductive layer group 2 includes a first conductive layer 21 and a second conductive layer 22 which are disposed at intervals. The step of forming the conductive layer group 2 includes: referring to fig. 3, an initial conductive layer group 200 is formed on one side surface of the first substrate 1; thereafter, referring to fig. 4, a portion of the initial group of conductive layers 200 is removed, such that the initial group of conductive layers 200 forms group of conductive layers 2.
In one embodiment, the process of forming the initial group of conductive layers 200 includes: sputtering or evaporation.
In one embodiment, the process of removing a portion of the initial group of conductive layers includes: photolithography, etching, and photoresist removal processes.
In one embodiment, the material of the initial group of conductive layers comprises: molybdenum or indium tin oxide.
In another embodiment, the initial group of conductive layers includes: and a titanium conductive layer, an aluminum conductive layer and a titanium conductive layer which are sequentially laminated on the surface of the first substrate.
In another embodiment, the initial group of conductive layers includes: and a titanium conductive layer, an aluminum conductive layer, a titanium conductive layer and a nickel conductive layer are sequentially laminated on the surface of the first substrate.
In another embodiment, the initial group of conductive layers includes: and an indium tin oxide conductive layer, a silver conductive layer and an indium tin oxide conductive layer which are sequentially laminated on the surface of the first substrate.
In one embodiment, the distance between the first conductive layer 21 and the second conductive layer 22 is 5 μm to 20 μm, for example 15 μm, if the distance between the first conductive layer and the second conductive layer is less than 5 μm, the difficulty of the process for preparing the first conductive layer and the second conductive layer may be increased; if the distance between the first conductive layer and the second conductive layer is greater than 20 μm, it is not advantageous to improve the integration of the display panel.
In other embodiments, the distance between the first conductive layer 21 and the second conductive layer 22 is adjusted according to the distance between the P-type electrode and the N-type electrode of the Micro-LED chip.
Referring to fig. 5, an insulating layer 3 is formed on a side of the first substrate 1 having the conductive layer group 2, the insulating layer 3 has a first opening K1 and a second opening K2 disposed at intervals, the bottom of the first opening K1 exposes the first conductive layer 21, and the bottom of the second opening K2 exposes the second conductive layer 22.
In one embodiment, the width of the first opening increases gradually from the bottom to the top of the first opening; the width of the second opening gradually increases from the bottom to the top of the second opening. This is advantageous in that the process of forming the first opening and the second opening is simplified.
The thickness of the insulating layer 3 is greater than the thickness of the first conductive layer 21 and greater than the thickness of the second conductive layer 22.
In one embodiment, the thickness of the insulating layer 3 is 0.5 μm to 10 μm, for example, 3 μm, and if the thickness of the insulating layer is less than 0.5 μm, the depth of the first opening and the second opening is too small, and the effect of the insulating layer between the first opening and the second opening to avoid the occurrence of short circuit between the first conductive layer and the second conductive layer is not obvious; if the thickness of the insulating layer is greater than 10 μm, the P-type electrode 51 may not be easily contacted with the first bonding layer 41, and the N-type electrode 52 may not be easily contacted with the second bonding layer 42.
In one embodiment, the insulating layer 3 is a single-layer structure, and the insulating layer 3 is a silicon oxide insulating layer, a polyimide insulating layer, a silicon nitride insulating layer, or a photoresist insulating layer.
In another embodiment, the insulating layer includes a stacked first sub-insulating layer and second sub-insulating layer; the first sub-insulating layer is a silicon dioxide sub-insulating layer, the second sub-insulating layer is a silicon nitride sub-insulating layer, or the first sub-insulating layer is a silicon nitride sub-insulating layer, and the second sub-insulating layer is a silicon dioxide sub-insulating layer.
Referring to fig. 6, a first bonding layer 41 is formed in the first opening K1, and a second bonding layer 42 is formed in the second opening K2.
In one embodiment, the process of forming the first bonding layer 41 includes an electroplating process; the process of forming the second bonding layer 42 includes an electroplating process.
In one embodiment, the first bonding layer 41 and the second bonding layer 42 are formed simultaneously, which is advantageous in simplifying the process; in other embodiments, the first bonding layer 41 is formed first; thereafter, the second bonding layer 42 is formed, or the second bonding layer 42 is formed first; after that, the first bonding layer 41 is formed.
Referring to fig. 7, a second substrate 10 is provided, one side of the second substrate 10 having a Micro-LED chip including: p-type electrode 51 and N-type electrode 52.
The Micro-LED chip further includes: a chip body; the P-type electrode 51 and the N-type electrode 52 are both positioned on a part of the surface of one side of the chip body.
In one embodiment, with continued reference to fig. 7, the chip body 5 includes: an N-type semiconductor layer 501; an active layer 502 located on a part of the surface of the N-type semiconductor layer 501; a P-type semiconductor layer 503 located on a side surface of the active layer 502 facing away from the N-type semiconductor layer 501; the P-type electrode 51 is located on a surface of a portion of the P-type semiconductor layer 503 facing away from the active layer 502; the N-type electrode 52 is located on the active layer 502, the P-type semiconductor layer 503, and a part of the surface of the P-type electrode 51 on the N-type semiconductor layer 501 side.
In one embodiment, the difference between the total area of the side surface of the P-type semiconductor layer 503 facing away from the active layer 502 and the projected area of the P-type electrode 51 on the surface of the P-type semiconductor layer 503 is 50 μm 2 ～200μm 2 For example 50. Mu.m 2 、80μm 2 、100μm 2 、120μm 2 、150μm 2 、180μm 2 Or 200 μm 2 。
In one embodiment, a third bonding layer 20 is provided between the second substrate 10 and the Micro-LED chip.
Referring to fig. 8, the P-type electrode 51 is bonded to the first bonding layer 41 and the N-type electrode 52 is bonded to the second bonding layer 42.
In other embodiments, the thickness of the insulating layer may be adjusted according to the thickness of the P-type electrode, the thickness of the N-type electrode, the thickness of the first bonding layer, and the thickness of the second bonding layer of the Micro-LED chip.
In one embodiment, in the step of bonding the P-type electrode 51 to the first bonding layer 41 and bonding the N-type electrode 52 to the second bonding layer 42, the insulating layer 3 is used to support the chip body, the P-type electrode 51 is embedded in the first opening k1, and the N-type electrode 52 is embedded in the second opening k 2. The first opening k1 limits the P-type electrode 51, so that accurate alignment of the P-type electrode 51 and the first bonding layer 41 can be improved, the first opening k1 can avoid lateral offset of the Mi cro-LED chip in the bonding process of the P-type electrode 51 and the first bonding layer 41, the second opening k2 limits the N-type electrode 52, accurate alignment of the N-type electrode 52 and the second bonding layer 42 can be improved, and the second opening k2 can also avoid lateral offset of the Mi cro-LED chip in the bonding process of the N-type electrode 52 and the second bonding layer 42, so that the manufacturing method of the display panel can improve structural stability of the display panel.
In one embodiment, with continued reference to fig. 8, the insulating layer 3 supports the P-type semiconductor layer around the P-type electrode 51 during the bonding of the P-type electrode 51 to the first bonding layer 41 and the bonding of the N-type electrode 52 to the second bonding layer 42. Thus, flatness of the top surfaces of the Mi cro-LED chips at one side deviating from the second substrate is guaranteed to a certain extent, and consistency of light emitting angles of the Mi cro-LED chips is enhanced; and the effective light emitting area of the Mi cro-LED chip increases.
Referring to fig. 9, after bonding the P-type electrode 51 and the first bonding layer 41 and simultaneously bonding the N-type electrode 52 and the second bonding layer 42, the method further includes: and (3) debonding the second substrate 10 from the Micro-LED chip, and stripping the third bonding layer 20 from the Mi cro-LED chip in the debonding process of the second substrate 10 from the Micro-LED chip.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the utility model.
Claims (8)
1. A display panel, comprising:
the device comprises a first substrate, a second substrate and a first electrode, wherein a conductive layer group is arranged on one side surface of the first substrate, and comprises a first conductive layer and a second conductive layer which are arranged at intervals;
the insulating layer is positioned on one side of the first substrate, a first opening and a second opening are arranged in the insulating layer at intervals, the first opening is positioned above the first conductive layer, and the second opening is positioned above the second conductive layer;
a first bonding layer located in the first opening, the first bonding layer being located on an upper surface of the first conductive layer; a second bonding layer located in the second opening, the second bonding layer being located on an upper surface of the second conductive layer;
a Micro-LED chip, the Micro-LED chip comprising: a P-type electrode and an N-type electrode; the P-type electrode is in contact with the first bonding layer, and the N-type electrode is in contact with the second bonding layer.
2. The display panel of claim 1, wherein the Micro-LED chip further comprises: a chip body; the P-type electrode and the N-type electrode are both positioned on part of the surface of one side of the chip body; the P-type electrode is embedded in the first opening, and the N-type electrode is embedded in the second opening; the chip body is in contact with the top surface of part of the insulating layer.
3. The display panel of claim 2, wherein the chip body comprises: an N-type semiconductor layer; an active layer located on a part of the surface of one side of the N-type semiconductor layer; the P-type semiconductor layer is positioned on one side surface of the active layer, which is away from the N-type semiconductor layer;
the P-type electrode is positioned on one side surface of part of the P-type semiconductor layer, which is away from the active layer;
the N-type electrode is positioned on the active layer, the P-type semiconductor layer and part of the surface of one side of the N-type semiconductor layer at the side part of the P-type electrode;
the P-type semiconductor layer around the P-type electrode is in contact with a top surface of the insulating layer around the first opening.
4. The display panel of claim 1, wherein the width of the first opening increases gradually from the bottom to the top of the first opening; the width of the second opening gradually increases from the bottom to the top of the second opening.
5. The display panel according to claim 4, wherein the first opening has a cross-sectional pattern in a direction perpendicular to the first substrate surface that includes an inverted trapezoid, and the second opening has a cross-sectional pattern in a direction perpendicular to the first substrate surface that includes an inverted trapezoid.
6. The display panel according to claim 1, wherein a distance between the first conductive layer and the second conductive layer is 5 μm to 20 μm.
7. The display panel according to claim 1, wherein the thickness of the insulating layer is 0.5 μm to 10 μm.
8. The display panel according to claim 1, wherein the insulating layer is a single-layer structure, and the insulating layer is a silicon oxide insulating layer, a polyimide insulating layer, a silicon nitride insulating layer, or a photoresist insulating layer;
alternatively, the insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked; the first sub-insulating layer is a silicon dioxide sub-insulating layer, the second sub-insulating layer is a silicon nitride sub-insulating layer, or the first sub-insulating layer is a silicon nitride sub-insulating layer, and the second sub-insulating layer is a silicon dioxide sub-insulating layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223602793.3U CN219226293U (en) | 2022-12-30 | 2022-12-30 | Display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223602793.3U CN219226293U (en) | 2022-12-30 | 2022-12-30 | Display panel |
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| CN219226293U true CN219226293U (en) | 2023-06-20 |
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| CN202223602793.3U Active CN219226293U (en) | 2022-12-30 | 2022-12-30 | Display panel |
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