CN219105366U - Multiplexing analog switch intelligent control circuit based on CPLD control - Google Patents
Multiplexing analog switch intelligent control circuit based on CPLD control Download PDFInfo
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- CN219105366U CN219105366U CN202223551241.4U CN202223551241U CN219105366U CN 219105366 U CN219105366 U CN 219105366U CN 202223551241 U CN202223551241 U CN 202223551241U CN 219105366 U CN219105366 U CN 219105366U
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Abstract
The utility model provides a multiplexing analog switch intelligent control circuit based on CPLD control, which comprises a signal input conditioning unit, an analog switch intelligent control unit and an output signal conditioning unit, and solves the problems of untimely accurate control and rapid switching of multiple complex signals, low reliability, inaccurate control precision, slow response time and the like. The control system has the advantages that the quick control on the airborne equipment, the missile-borne equipment and the surrounding circuits is realized, the safety and the reliability are realized, and the safe and stable operation of the control system can be ensured.
Description
Technical Field
The utility model belongs to the technical field of circuit control systems, and particularly relates to an intelligent control circuit of a multiplexing analog switch based on CPLD control.
Background
In the field of circuit control systems of various devices such as airborne devices and missile-borne devices, the circuit control system is particularly important for ensuring the stability, the accuracy and the quick control of control signals and safety display. The control of the circuit in the prior art has the problems of instability, inaccuracy and slow response time.
Therefore, a control circuit for realizing quick control of airborne, missile-borne equipment and surrounding circuits, which is safe and reliable and can ensure safe and stable operation of a control system is needed.
Disclosure of Invention
In order to solve the problems, the utility model provides an intelligent control circuit of a multiplexing analog switch based on CPLD control, which is used for the fields of high control precision, control with high requirements on quick switching and the like.
The utility model aims to provide a multiplexing analog switch intelligent control circuit based on CPLD control, which comprises
The signal input conditioning unit is used for performing signal conditioning and amplification processing on the input switch given signal so as to meet the signal input of the intelligent control unit of the analog switch, thereby providing an intelligent control signal of the switch of the CPLD processor;
the analog signal intelligent control unit is used for receiving the four paths of CPLD control signals provided by the signal input conditioning unit, generating multiple paths of logic combination control signals, and outputting the multiple paths of logic combination control signals to the multiplexer chip for controlling eight paths of switch signals in the chip;
the analog signal output conditioning unit is used for conditioning the switch control signals given by the analog signal intelligent control unit, and is used for outputting and controlling other state quantities or loads.
The multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model is also characterized in that the signal input conditioning unit comprises an input signal 1, an input signal 2, an input signal 3, an input signal 4, a short circuit resistor R139 and a resistor R140, a short circuit resistor R130 and a resistor R131, a linear amplifier N3 and a linear amplifier N4, current limiting resistors R137 and R132, a capacitor C52, a capacitor C103, a zero drift amplifier N7, current limiting resistors R132 and R133, a capacitor C101, a capacitor C102 and a current limiting resistor R94,
the input signals 3 and 4 are respectively connected with the 4 th pin and the 1 st pin of the linear amplifier N4,
after the resistor R139 and the resistor R140 are short-circuited, two ends of the resistor R139 are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N3,
the two ends of the resistor R130 and the resistor R131 after being short-circuited are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N4,
the 5 th pin and the 8 th pin of the linear amplifier N3 and the linear amplifier N4 are respectively connected with a power supply VCC-and a power supply VCC+,
the 7 th pins of the linear amplifier N3 and the linear amplifier N4 are respectively connected with one ends of the current limiting resistors R137 and R132,
one end of the current limiting resistor R137 is connected to the common terminal of the capacitor C52 and the current limiting resistor R136,
the common terminal of the current limiting resistor R136 and the capacitor C103 is connected to pin 5 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C103 is grounded, the 7 th pin of the zero drift amplifier N7 is connected with the common end of the 6 th pin reverse input end of the zero drift amplifier N7 and one end of the capacitor C52,
one end of the current limiting resistor R132 is connected to the common terminal of the capacitor C101 and the current limiting resistor R133,
the common terminal of the current limiting resistor R133 and the capacitor C102 is connected to pin 3 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C102 is grounded, the 1 st pin of the zero-shift amplifier N7 is connected with the common end of one end of the capacitor C101 and the 2 nd pin of the zero-shift amplifier N7,
the 7 th pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N1 and one end of the current limiting resistor R94, and the 1 st pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N2 and one end of the current limiting resistor R101.
The multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model has the characteristics that four paths of CPLD control signals in the analog signal intelligent control unit control eight paths of switch signals, and can generate state quantities of various control states for controlling the eight paths of switches, wherein the control states comprise states capable of controlling one or more combinations of the eight paths of switches.
The multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model is also characterized in that the analog control signal control unit comprises four paths of control signals, a multiplexer N1, a multiplexer N2, filter capacitors C6, C62, C5, C63, C4, C65, C64, C3, filter capacitors C18, C60, C17, C61, C19, C13, C16, C14, short-circuit capacitors C56, C75, grounding resistors R70, R104 and current limiting resistors R74, R232,
the four-way control signal comprises a control signal 1, a control signal 2, a control signal 3 and a control enabling signal 4,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N1 are respectively connected to one ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64, C3,
the common ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64 and C3 are connected with the 7 th pin of the zero drift amplifier N7,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N2 are respectively connected to one ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16, C14,
the common ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16 and C14 are connected with the 1 st pin of the zero drift amplifier N7,
the 8 th pin of the multiplexer N1 is connected with the common end of the shorting capacitor C56, the grounding resistor R70 and the current limiting resistor R74,
the 8 th pin of the multiplexer N2 is connected with the common end of the short circuit capacitor C75, the grounding resistor R104 and the current limiting resistor R232,
the common ground of the ground resistor R70 and the filter capacitor C65,
the common ground of the ground resistor R104 and the filter capacitor C75,
VDD and VSS of the multiplexer N1 and the multiplexer N2 are respectively connected to the power vcc+ and the power VCC-.
The multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model is also characterized in that the analog signal output conditioning unit comprises zero drift amplifiers N5 and N6, current limiting resistors R94, R92, R73, R72, R71, R101, R86, R230, R87 and R231, filter capacitors C7, C8, C9, C66, C41, C73, C72 and C71, an output end 1 and an output end 2,
the current limiting resistor R94 and the filter capacitor C7 are connected to a common terminal of the current limiting resistor R92,
the common terminal of the filter capacitor C8 and the positive input terminal of the zero drift amplifier N5 is connected to one terminal of a current limiting resistor R92,
one end of the filter capacitor C8 is grounded,
the common terminal of the filter capacitor C7 and the current limiting resistor R73 is connected to the inverting input terminal of the zero drift amplifier N5,
the current-limiting resistor R73 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N5, the common ends of the current-limiting resistor and the filter capacitor,
the current limiting resistor R71 and the common terminal of the filter capacitor C66 and the output 1 are connected to a first leg of the zero drift amplifier N5,
the current limiting resistor R101 and the filter capacitor C41 are connected to a common terminal of the current limiting resistor R86,
the common terminal of the filter capacitor C73 and the positive input terminal of the zero drift amplifier N6 is connected to one terminal of a current limiting resistor R86,
one end of the filter capacitor C73 is grounded,
the common terminal of the filter capacitor C41 and the current limiting resistor R230 is connected to the inverting input terminal of the zero drift amplifier N6,
the current-limiting resistor R230 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N6, the common ends of the current-limiting resistor and the filter capacitor,
the common terminal of the current limiting resistor R231, the filter capacitor C71 and the output terminal 1 is connected to the first pin of the zero drift amplifier N6, and the power supplies of the zero drift amplifiers N5 and N6 are VCC+ and VCC-.
The beneficial effects are that:
the multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model comprises a signal input conditioning unit, an analog switch intelligent control unit and an output signal conditioning unit, and solves the problems of untimely accurate control and quick switching of multiple complex signals, low reliability, inaccurate control precision, slow response time and the like. The control system has the advantages that the quick control on the airborne equipment, the missile-borne equipment and the surrounding circuits is realized, the safety and the reliability are realized, and the safe and stable operation of the control system can be ensured.
Drawings
In order to more clearly illustrate the technical solutions of the present utility model, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a multiplexing analog switch intelligent control circuit based on CPLD control according to an embodiment of the present utility model.
Detailed Description
In order to make the technical means, creation characteristics, achievement purposes and effects achieved by the utility model easy to understand, the following embodiment describes the multiplexing analog switch intelligent control circuit based on CPLD control provided by the utility model specifically with reference to the accompanying drawings.
In the description of the embodiments of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present utility model and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the utility model.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.
The terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the creation of the present utility model can be understood by those of ordinary skill in the art in a specific case.
As shown in fig. 1, there is provided a multiplexing analog switch intelligent control circuit based on CPLD control, the control circuit comprising
The signal input conditioning unit is used for performing signal conditioning and amplification processing on the input switch given signal so as to meet the signal input of the intelligent control unit of the analog switch, thereby providing an intelligent control signal of the switch of the CPLD processor;
the analog signal intelligent control unit is used for receiving the four paths of CPLD control signals provided by the signal input conditioning unit, generating multiple paths of logic combination control signals, and outputting the multiple paths of logic combination control signals to the multiplexer chip for controlling eight paths of switch signals in the chip;
the analog signal output conditioning unit is used for conditioning the switch control signals given by the analog signal intelligent control unit, and is used for outputting and controlling other state quantities or loads.
In some embodiments, the signal input conditioning unit includes input signal 1, input signal 2, input signal 3, input signal 4, shorting resistor R139 and resistor R140, shorting resistor R130 and resistor R131, linear amplifier N3 and linear amplifier N4, current limiting resistors R137 and R132, capacitor C52, capacitor C103, zero shift amplifier N7, current limiting resistors R132 and R133, capacitor C101, capacitor C102, and current limiting resistor R94,
the input signals 3 and 4 are respectively connected with the 4 th pin and the 1 st pin of the linear amplifier N4,
after the resistor R139 and the resistor R140 are short-circuited, two ends of the resistor R139 are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N3,
the two ends of the resistor R130 and the resistor R131 after being short-circuited are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N4,
the 5 th pin and the 8 th pin of the linear amplifier N3 and the linear amplifier N4 are respectively connected with a power supply VCC-and a power supply VCC+,
the 7 th pins of the linear amplifier N3 and the linear amplifier N4 are respectively connected with one ends of the current limiting resistors R137 and R132,
one end of the current limiting resistor R137 is connected to the common terminal of the capacitor C52 and the current limiting resistor R136,
the common terminal of the current limiting resistor R136 and the capacitor C103 is connected to pin 5 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C103 is grounded, the 7 th pin of the zero drift amplifier N7 is connected with the common end of the 6 th pin reverse input end of the zero drift amplifier N7 and one end of the capacitor C52,
one end of the current limiting resistor R132 is connected to the common terminal of the capacitor C101 and the current limiting resistor R133,
the common terminal of the current limiting resistor R133 and the capacitor C102 is connected to pin 3 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C102 is grounded, the 1 st pin of the zero-shift amplifier N7 is connected with the common end of one end of the capacitor C101 and the 2 nd pin of the zero-shift amplifier N7,
the 7 th pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N1 and one end of the current limiting resistor R94, and the 1 st pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N2 and one end of the current limiting resistor R101.
In some embodiments, the four-way CPLD control signal in the analog signal intelligent control unit controls the eight-way switch signal, and may generate a plurality of control states to control the state quantity of the eight-way switch, where the control states include states that may control one or more combinations of the eight-way switch.
In some embodiments, the analog control signal control unit includes four paths of control signals, a multiplexer N1, a multiplexer N2, filter capacitors C6, C62, C5, C63, C4, C65, C64, C3, filter capacitors C18, C60, C17, C61, C19, C13, C16, C14, shorting capacitors C56, C75, ground resistors R70, R104, and current limiting resistors R74, R232,
the four-way control signal comprises a control signal 1, a control signal 2, a control signal 3 and a control enabling signal 4,
control signals 1, 2, 3 and 4 are respectively connected to the 1 st, 16 th, 15 th and 2 nd pins of the multiplexer N1 and the multiplexer N2 pin,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N1 are respectively connected to one ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64, C3,
the common ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64 and C3 are connected with the 7 th pin of the zero drift amplifier N7,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N2 are respectively connected to one ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16, C14,
the common ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16 and C14 are connected with the 1 st pin of the zero drift amplifier N7,
the 8 th pin of the multiplexer N1 is connected with the common end of the shorting capacitor C56, the grounding resistor R70 and the current limiting resistor R74,
the 8 th pin of the multiplexer N2 is connected with the common end of the short circuit capacitor C75, the grounding resistor R104 and the current limiting resistor R232,
the common ground of the ground resistor R70 and the filter capacitor C65,
the common ground of the ground resistor R104 and the filter capacitor C75,
VDD and VSS of the multiplexer N1 and the multiplexer N2 are respectively connected to the power vcc+ and the power VCC-.
In some embodiments, the analog signal output conditioning unit includes zero drift amplifiers N5, N6, current limiting resistors R94, R92, R73, R72, R71, R101, R86, R230, R87, R231, filter capacitors C7, C8, C9, C66, C41, C73, C72, C71, output 1 and output 2,
the current limiting resistor R94 and the filter capacitor C7 are connected to a common terminal of the current limiting resistor R92,
the common terminal of the filter capacitor C8 and the positive input terminal of the zero drift amplifier N5 is connected to one terminal of a current limiting resistor R92,
one end of the filter capacitor C8 is grounded,
the common terminal of the filter capacitor C7 and the current limiting resistor R73 is connected to the inverting input terminal of the zero drift amplifier N5,
the current-limiting resistor R73 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N5, the common ends of the current-limiting resistor and the filter capacitor,
the current limiting resistor R71 and the common terminal of the filter capacitor C66 and the output 1 are connected to a first leg of the zero drift amplifier N5,
the current limiting resistor R101 and the filter capacitor C41 are connected to a common terminal of the current limiting resistor R86,
the common terminal of the filter capacitor C73 and the positive input terminal of the zero drift amplifier N6 is connected to one terminal of a current limiting resistor R86,
one end of the filter capacitor C73 is grounded,
the common terminal of the filter capacitor C41 and the current limiting resistor R230 is connected to the inverting input terminal of the zero drift amplifier N6,
the current-limiting resistor R230 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N6, the common ends of the current-limiting resistor and the filter capacitor,
the common terminal of the current limiting resistor R231, the filter capacitor C71 and the output terminal 1 is connected to the first pin of the zero drift amplifier N6, and the power supplies of the zero drift amplifiers N5 and N6 are VCC+ and VCC-.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model. The foregoing is merely a preferred embodiment of the present utility model, and it should be noted that it will be apparent to those skilled in the art that modifications and variations can be made without departing from the technical principles of the present utility model, and these modifications and variations should also be regarded as the scope of the utility model.
Claims (5)
1. A multiplexing analog switch intelligent control circuit based on CPLD control is characterized in that the control circuit comprises
The signal input conditioning unit is used for performing signal conditioning and amplification processing on the input switch given signal so as to meet the signal input of the intelligent control unit of the analog switch, thereby providing an intelligent control signal of the switch of the CPLD processor;
the analog signal intelligent control unit is used for receiving the four paths of CPLD control signals provided by the signal input conditioning unit, generating multiple paths of logic combination control signals, and outputting the multiple paths of logic combination control signals to the multiplexer chip for controlling eight paths of switch signals in the chip;
and the analog signal output conditioning unit is used for conditioning the switch control signal given by the analog signal intelligent control unit, and outputting the control state quantity or the load.
2. The CPLD control based multiplexing analog switch intelligent control circuit according to claim 1, wherein the signal input conditioning unit comprises an input signal 1, an input signal 2, an input signal 3, an input signal 4, a shorting resistor R139 and a resistor R140, a shorting resistor R130 and a resistor R131, a linear amplifier N3 and a linear amplifier N4, current limiting resistors R137 and R132, a capacitor C52, a capacitor C103, a zero drift amplifier N7, current limiting resistors R132 and R133, a capacitor C101, a capacitor C102 and a current limiting resistor R94,
input signal 1 and input signal 2 are connected to pins 4 and 1 of linear amplifier N3,
the input signals 3 and 4 are respectively connected with the 4 th pin and the 1 st pin of the linear amplifier N4,
after the resistor R139 and the resistor R140 are short-circuited, two ends of the resistor R139 are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N3,
the two ends of the resistor R130 and the resistor R131 after being short-circuited are respectively connected with the 3 rd pin and the 2 nd pin of the linear amplifier N4,
the 5 th pin and the 8 th pin of the linear amplifier N3 and the linear amplifier N4 are respectively connected with a power supply VCC-and a power supply VCC+,
the 7 th pins of the linear amplifier N3 and the linear amplifier N4 are respectively connected with one ends of the current limiting resistors R137 and R132,
one end of the current limiting resistor R137 is connected to the common terminal of the capacitor C52 and the current limiting resistor R136,
the common terminal of the current limiting resistor R136 and the capacitor C103 is connected to pin 5 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C103 is grounded, the 7 th pin of the zero drift amplifier N7 is connected with the common end of the 6 th pin reverse input end of the zero drift amplifier N7 and one end of the capacitor C52,
one end of the current limiting resistor R132 is connected to the common terminal of the capacitor C101 and the current limiting resistor R133,
the common terminal of the current limiting resistor R133 and the capacitor C102 is connected to pin 3 of the positive input terminal of the zero drift amplifier N7,
one end of the capacitor C102 is grounded, the 1 st pin of the zero-shift amplifier N7 is connected with the common end of one end of the capacitor C101 and the 2 nd pin of the zero-shift amplifier N7,
the 7 th pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N1 and one end of the current limiting resistor R94, and the 1 st pin of the zero-shift amplifier N7 is connected to the common terminal of the 4 th pin of the multiplexer N2 and one end of the current limiting resistor R101.
3. The intelligent control circuit for the multiplexing analog switch based on the CPLD control according to claim 1, wherein four CPLD control signals in the intelligent control unit for analog signals control eight switch signals, and state quantities for controlling eight switches in various control states can be generated, and the control states comprise states for controlling one or more combinations of eight switches.
4. The CPLD control based multiplexing analog switch intelligent control circuit according to claim 3, wherein the analog control signal control unit comprises four-way control signals, a multiplexer N1, a multiplexer N2, filter capacitors C6, C62, C5, C63, C4, C65, C64, C3, filter capacitors C18, C60, C17, C61, C19, C13, C16, C14, shorting capacitors C56, C75, ground resistors R70, R104, and current limiting resistors R74, R232,
the four-way control signal comprises a control signal 1, a control signal 2, a control signal 3 and a control enabling signal 4,
control signals 1, 2, 3 and 4 are respectively connected to the 1 st, 16 th, 15 th and 2 nd pins of the multiplexer N1 and the multiplexer N2 pin,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N1 are respectively connected to one ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64, C3,
the common ends of the filter capacitors C6, C62, C5, C63, C4, C65, C64 and C3 are connected with the 7 th pin of the zero drift amplifier N7,
the 4 th, 5 th, 6 th, 7 th, 12 th, 11 th, 10 th, 9 th pins of the multiplexer N2 are respectively connected to one ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16, C14,
the common ends of the filter capacitors C18, C60, C17, C61, C19, C13, C16 and C14 are connected with the 1 st pin of the zero drift amplifier N7,
the 8 th pin of the multiplexer N1 is connected with the common end of the shorting capacitor C56, the grounding resistor R70 and the current limiting resistor R74,
the 8 th pin of the multiplexer N2 is connected with the common end of the short circuit capacitor C75, the grounding resistor R104 and the current limiting resistor R232,
the common ground of the ground resistor R70 and the filter capacitor C65,
the common ground of the ground resistor R104 and the filter capacitor C75,
VDD and VSS of the multiplexer N1 and the multiplexer N2 are respectively connected to the power vcc+ and the power VCC-.
5. The intelligent control circuit for a multiplexing analog switch based on CPLD control according to claim 1, wherein the analog signal output conditioning unit comprises zero drift amplifiers N5, N6, current limiting resistors R94, R92, R73, R72, R71, R101, R86, R230, R87, R231, filter capacitors C7, C8, C9, C66, C41, C73, C72, C71, an output terminal 1 and an output terminal 2,
the current limiting resistor R94 and the filter capacitor C7 are connected to a common terminal of the current limiting resistor R92,
the common terminal of the filter capacitor C8 and the positive input terminal of the zero drift amplifier N5 is connected to one terminal of a current limiting resistor R92,
one end of the filter capacitor C8 is grounded,
the common terminal of the filter capacitor C7 and the current limiting resistor R73 is connected to the inverting input terminal of the zero drift amplifier N5,
the current-limiting resistor R73 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N5, the common ends of the current-limiting resistor and the filter capacitor,
the current limiting resistor R71 and the common terminal of the filter capacitor C66 and the output 1 are connected to a first leg of the zero drift amplifier N5,
the current limiting resistor R101 and the filter capacitor C41 are connected to a common terminal of the current limiting resistor R86,
the common terminal of the filter capacitor C73 and the positive input terminal of the zero drift amplifier N6 is connected to one terminal of a current limiting resistor R86,
one end of the filter capacitor C73 is grounded,
the common terminal of the filter capacitor C41 and the current limiting resistor R230 is connected to the inverting input terminal of the zero drift amplifier N6,
the current-limiting resistor R230 is respectively connected with the 7 th pin and the 2 nd pin of the zero drift amplifier N6, the common ends of the current-limiting resistor and the filter capacitor,
the common terminal of the current limiting resistor R231, the filter capacitor C71 and the output terminal 1 is connected to the first pin of the zero drift amplifier N6, and the power supplies of the zero drift amplifiers N5 and N6 are VCC+ and VCC-.
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