CN219018517U

CN219018517U - System for negotiating and adjusting power supply capacity with power adapter

Info

Publication number: CN219018517U
Application number: CN202223469397.8U
Authority: CN
Inventors: 丁松; 陈杨剑
Original assignee: Fujian Newland Payment Technology Co ltd
Current assignee: Fujian Newland Payment Technology Co ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-05-12
Anticipated expiration: 2032-12-23

Abstract

The utility model discloses a system for negotiating and adjusting power supply capacity with a power adapter, which is applied to the power adapter and an electronic terminal; the system comprises: the power supply interface circuit is positioned in the power adapter, and the power supply circuit, the power-on detection circuit, the PD identification negotiation circuit, the QC identification negotiation circuit and the main control circuit are positioned in the electronic terminal; the main control circuit is respectively connected with the power-on detection circuit, the PD identification negotiation circuit and the QC identification negotiation circuit, the power supply interface circuit and the power-on detection circuit are both connected to the power supply circuit, and the power supply interface circuit is respectively connected with the PD identification negotiation circuit and the QC identification negotiation circuit. The utility model is mainly applied to the condition that the electronic terminal is powered on by the USB Type-C interface, different power adapters support different quick-charging protocols, and in order to enable the power adapters to achieve the optimal power supply capacity, negotiation of QC2.0 and PD partial quick-charging protocols is realized.

Description

System for negotiating and adjusting power supply capacity with power adapter

Technical Field

The present utility model relates to the field of power supply technologies, and in particular, to a system for negotiating and adjusting power supply capability with a power adapter.

Background

In the use process of the electronic terminal, especially in a mobile scene, there is often no fixed power adapter, so only different power adapters can be used to supply power to the electronic terminal, if the electronic terminal does not have the compatibility of a fast charging protocol, the power supply capacity of the power adapter may be only 5v 1a, which is insufficient to support continuous high-intensity work of the electronic terminal, and the following power adapter power supply schemes are mainly available in the market at present:

1. no negotiation scheme: the scheme is simplest in the complexity of the system, but only supports the default low power supply capacity of the power adapter, continuous high-strength work of the electronic terminal cannot be met, when the electronic terminal is in instantaneous high power demand, the problems that the system power supply voltage drops, the system is abnormally shut down and the like occur, even the power adapter can stop externally supplying power, for example, a part of the power adapter only supports the PD protocol, the default of the adapter is not negotiated, the power supply is not externally supplied, and the system cannot be started.

2. Negotiating an IC scheme: the scheme has the best performance in terms of negotiation efficiency and compatibility, and can meet the negotiation of the power supply capacity of different power adapters, but requires a CPU inside the electronic terminal to integrate a fast charge negotiation protocol or an independent fast charge protocol chip, thereby causing the limitation of CPU selection and the rise of terminal cost.

Disclosure of Invention

In view of the above, the present utility model aims to provide a system for negotiating and adjusting power supply capability with a power adapter, which is mainly applied to the situation that an electronic terminal is powered on an USB Type-C interface, because different power adapters support different fast charging protocols, in order to enable the power adapter to achieve the optimal power supply capability, the present utility model implements negotiation of the QC2.0 and PD partial fast charging protocols.

In order to achieve the technical purpose, the utility model adopts the following technical scheme:

a system for negotiating and adjusting power supply capacity with a power adapter is applied to the power adapter and an electronic terminal; the system comprises: the power supply interface circuit is positioned in the power adapter, and the power supply circuit, the power-on detection circuit, the PD identification negotiation circuit, the QC identification negotiation circuit and the main control circuit are positioned in the electronic terminal;

the main control circuit is respectively connected with the power-on detection circuit, the PD identification negotiation circuit and the QC identification negotiation circuit, the power supply interface circuit and the power-on detection circuit are both connected to the power supply circuit, and the power supply interface circuit is respectively connected with the PD identification negotiation circuit and the QC identification negotiation circuit.

Further, the power supply interface circuit comprises a chip J1, wherein an A4 pin, an A9 pin, a B4 pin and a B9 pin of the chip J1 are all connected to the power supply circuit, an A5 pin and a B5 pin of the chip J1 are all connected to the PD identification negotiation circuit, and an A7 pin, an A6 pin, a B7 pin and a B6 pin of the chip J1 are all connected to the QC identification negotiation circuit; the chip J1 is characterized in that the A1 pin, the A12 pin, the B1 pin, the B12 pin, the G1 pin, the G2 pin, the G3 pin, the G4 pin, the G5 pin and the G6 pin of the chip J1 are all grounded, and the A8 pin, the B8 pin, the A3 pin, the A2 pin, the B10 pin, the B11 pin, the B3 pin, the B2 pin, the A10 pin and the A11 pin of the chip J1 are suspended.

Further, the power-on detection circuit comprises an NPN triode Q1, a resistor R2 and a resistor R3, wherein the b pole of the NPN triode Q1 is connected with one end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R2 is connected to the power supply circuit, the c pole of the NPN triode Q1 is connected with one end of the resistor R1 and the main control circuit respectively, the other end of the resistor R1 is connected to a power supply V, and the e pole of the NPN triode Q1 and the other end of the resistor R3 are grounded.

Further, the PD discernment negotiation circuit includes resistance R4, resistance R5, resistance R6 and resistance R7, the one end of resistance R4 and the one end of resistance R5 are all connected to the master control circuit, the other end of R4 is connected with resistance R6's one end and power supply interface circuit respectively, the other end of R5 is connected with resistance R7's one end and power supply interface circuit respectively, the other end of resistance R6 and the other end of resistance R7 are all grounded.

Further, the QC identification negotiation circuit comprises a first power matching circuit, a second power matching circuit and a level detection circuit, wherein the first power matching circuit is respectively connected with the main control circuit and the power supply interface circuit, the second power matching circuit is respectively connected with the main control circuit and the power supply interface circuit, and the level detection circuit is respectively connected with the main control circuit and the power supply interface circuit.

Further, the first power matching circuit includes an NPN triode Q2, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, a c pole of the NPN triode Q2 is connected to the power supply V, an e pole of the NPN triode Q2 is connected to one end of the resistor R10 and the power supply interface circuit through the resistor R8, the other end of the resistor R10 is grounded, a b pole of the NPN triode Q2 is connected to one end of the resistor R9 and one end of the resistor R11, the other end of the resistor R11 is grounded, and the other end of the resistor R9 is connected to the master control circuit.

Further, the level detection circuit comprises an NMOS tube Q3, a resistor R12 and a resistor R13, wherein the D electrode of the NMOS tube Q3 is respectively connected with one end of the resistor R12 and the main control circuit, the other end of the resistor R12 is connected to a power supply V, the G electrode of the NMOS tube Q3 is connected to the power supply interface circuit through the resistor R13, and the S electrode of the NMOS tube Q3 is grounded.

Further, the second power matching circuit includes an NPN triode Q4, an NPN triode Q5, an NPN triode Q6, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, and a resistor R22;

the c pole of the NPN triode Q4 is connected to a power supply V, the e pole of the NPN triode Q4 is respectively connected with one end of a resistor R16 and a power supply interface circuit through a resistor R14, the other end of the resistor R16 is grounded, the b pole of the NPN triode Q4 is respectively connected with one end of a resistor R15 and one end of a resistor R17, and the other end of the resistor R15 is connected to a main control circuit;

the c pole of the NPN triode Q5 is connected to a power supply V, the e pole of the NPN triode Q5 is connected to a power supply interface circuit through a resistor R18, the b pole of the NPN triode Q5 is respectively connected with one end of a resistor R21, one end of a resistor R19 and the c pole of the NPN triode Q6, and the other end of the resistor R21 is grounded;

the pole b of the NPN triode Q6 is respectively connected with one end of a resistor R20 and one end of a resistor R22, the other end of the resistor R19 and the other end of the resistor R20 are both connected to a main control circuit, and the other end of the resistor R22 and the pole e of the NPN triode Q6 are both grounded.

Further, the master control circuit comprises a chip U1, a resistor R137, a resistor R138, a capacitor C106 and a capacitor C107, wherein a seventh pin of the chip U1 is connected with the power-on detection circuit, a tenth pin of the chip U1 is connected with the PD identification negotiation circuit, and a twelfth pin, a thirteenth pin and a fourteenth pin of the chip U1 are all connected with the QC identification negotiation circuit; the sixteenth pin, the fifth pin, one end of the resistor R137, one end of the resistor R138 and one end of the capacitor C106 of the chip U1 are all connected to the power supply V, the first pin of the U1 is connected to the other end of the resistor R138, the fourth pin of the chip U1 is respectively connected to the other end of the resistor R137 and one end of the capacitor C107, and the fifteenth pin of the chip U1, the other end of the capacitor C106 and the other end of the capacitor C107 are all grounded; the second pin, the third pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the seventeenth pin, the eighteenth pin, the nineteenth pin and the twentieth pin of the chip U1 are all suspended.

Further, the model of the chip U1 is STM32F030F4; the model of the chip J1 is MUP-U20201.

By adopting the technical scheme, compared with the prior art, the utility model has the beneficial effects that: the system for negotiating and adjusting the power supply capacity with the power adapter is designed, partial fast charging protocols of PD and QC2.0 are intelligently negotiated, the power supply capacity of the power adapter is improved, the problem that the power supply capacity of the power adapter is insufficient or no output exists is avoided, and the power supply requirement of high-power and high-strength operation of the system is met. The requirements of the electronic terminal are also simplified, a CPU of the electronic terminal is not required to integrate a fast charging protocol interface, and an additional new fast charging protocol chip is not required, so that intelligent negotiation of the power supply capacity of the power adapter can be realized.

1. In contrast to the no negotiation scheme: the power supply negotiation protocol of more adapters can be compatible, the high-power liability requirement is met, and the problems of system power supply voltage drop, abnormal system shutdown and the like caused by weak default power supply capability are avoided. Under the condition that only the PD protocol power adapter is supported, if the handshake protocol action is not performed, normal power supply cannot be performed, at the moment, the power supply system cannot supply power, and the situation that the terminal cannot be started occurs.

2. In contrast to the negotiation IC scheme: the CPU in the electronic terminal is not required to integrate the fast charge negotiation protocol, the electronic terminal is not required to additionally integrate an independent fast charge protocol chip, the special E-MARK chip is not required to be integrated on the USB charging line, the CPU type selection limit is reduced, the power accessory requirement is reduced, and the cost of the electronic terminal is reduced.

Drawings

In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of the overall architecture of a system for negotiating power supply adjustment with a power adapter in accordance with the present utility model.

FIG. 2 is a schematic diagram of a system for negotiating and adjusting power supply capability with a power adapter according to the present utility model.

The reference numerals in the figures illustrate:

the power adapter 100, the power supply interface circuit 11, the electronic terminal 200, the power supply circuit 21, the power-on detection circuit 22, the PD identification negotiation circuit 23, the QC identification negotiation circuit 24, the first power matching circuit 241, the level detection circuit 242, the second power matching circuit 243, and the main control circuit 25.

Detailed Description

The utility model is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present utility model, but do not limit the scope of the present utility model. Likewise, the following examples are only some, but not all, of the examples of the present utility model, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present utility model.

The utility model provides a system for negotiating and adjusting power supply capacity with a power adapter, which can enable the power adapter to achieve optimal power supply capacity.

Referring to fig. 1 and fig. 2, a system for negotiating and adjusting power supply capability with a power adapter according to the present utility model is applied to a power adapter 100 and an electronic terminal 200; the system comprises: a power supply interface circuit 11 located in the power adapter 100, and a power supply circuit 21, a power-on detection circuit 22, a PD identification negotiation circuit 23, a QC identification negotiation circuit 24, and a main control circuit 25 located in the electronic terminal 200;

the main control circuit 25 is respectively connected with the power-on detection circuit 22, the PD identification negotiation circuit 23 and the QC identification negotiation circuit 24, the power supply interface circuit 11 and the power-on detection circuit 22 are both connected to the power supply circuit 21, and the power supply interface circuit 11 is respectively connected with the PD identification negotiation circuit 23 and the QC identification negotiation circuit 24. The power adapter 100 can be compatible with and support the PD fast charging protocol and the QC fast charging protocol, improves the power supply capacity of the power adapter 100, and meets different power supply requirements.

The power supply interface circuit 11 is a connection interface for connecting the power adapter 100 (power supply end) and the electronic terminal 200 (power consumption end), and inserts the electronic terminal 200 onto the power adapter 100 through the interface, so that the power adapter 100 can supply power to the electronic terminal 200;

the power supply circuit 21 is configured to supply power to the entire system of the electronic terminal 200, the power supply circuit 21 is respectively connected to the system load of the electronic terminal 200 and the power supply interface circuit 11, and the entire power supply process is as follows: power adapter 100→power supply interface circuit 11→power supply circuit 21→system load of electronic terminal 200; that is, the power adapter 100 supplies power to the power supply circuit 21, and the power supply circuit 21 supplies power to the whole system of the electronic terminal 200;

the power-on detection circuit 22 is configured to detect whether the power adapter 100 has a power source available for power supply (power input) by connecting with the power supply interface circuit 11, where the detection purpose is that the power adapter 100 can only have the power supply capability when the power source is available, and the power supply condition of the power adapter 100 needs to be reasonably configured and negotiated according to the power supply requirement of the user on the electronic terminal 200; the power adapter 100 can be connected with a mains supply row for supplying power, and can also be a mobile power supply;

the PD identification negotiation circuit 23 is configured to identify and negotiate a PD part protocol, intelligently identify and configure output power of the power adapter 100, and support identification of a 5V voltage domain; PD is a fast charging specification established by the USB-IF organization, and is one of the current mainstream fast charging protocols. The USB-PD fast charging protocol is output by a Type-C interface;

the QC identification negotiation circuit 24 is configured to identify and negotiate a QC2.0 protocol, intelligently identify and configure output power of the power adapter 100, and support identification of 5V, 9V and 12V voltage domains; QC2.0 fast charging means the latest mobile phone fast charging scheme combined with the high-pass Cell 800 series chip set, and the self-adaptive output of the charger can reach 9V and 12V so as to fast charge mobile devices such as mobile phones;

the main control circuit 25 is configured to reasonably configure the output power of the power adapter 100 by controlling the PD identification negotiation circuit 23 and the QC identification negotiation circuit 24, so as to supply power to the electronic terminal 200.

In this embodiment, the power supply interface circuit 11 includes a chip J1, and the model of the chip J1 is MUP-U20201; the pin A4, the pin A9, the pin B4 and the pin B9 of the chip J1 are all connected to a power supply circuit 21 (for example, a power supply VBUS), the pin A5 and the pin B5 of the chip J1 are all connected to a PD identification negotiation circuit 23 (for example, the pin A5 of the chip J1 is respectively connected with one end of a resistor R4 and one end of a resistor R6, the pin B5 of the chip J1 is respectively connected with one end of a resistor R5 and one end of a resistor R7), the pin A7, the pin A6, the pin B7 and the pin B6 of the chip J1 are all connected to a QC identification negotiation circuit 24 (for example, the pin A7 and the pin B7 of the chip J1 are respectively connected to one end of a resistor R8, a resistor R10 and one end of a resistor R13 after being connected in parallel, the pin A6 and the pin B6 of the chip J1 are respectively connected to one end of a resistor R14, a resistor R16 and one end of a resistor R18 after being connected in parallel); the chip J1 is characterized in that the A1 pin, the A12 pin, the B1 pin, the B12 pin, the G1 pin, the G2 pin, the G3 pin, the G4 pin, the G5 pin and the G6 pin of the chip J1 are all grounded, and the A8 pin, the B8 pin, the A3 pin, the A2 pin, the B10 pin, the B11 pin, the B3 pin, the B2 pin, the A10 pin and the A11 pin of the chip J1 are suspended. The power supply interface circuit 11 adopts a USB-Type-C interface.

In this embodiment, the power-on detection circuit 22 includes an NPN triode Q1, a resistor R2 and a resistor R3, wherein a pole b of the NPN triode Q1 is connected with one end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R2 is connected to a power supply circuit 21 (e.g., a power supply VBUS), a pole c of the NPN triode Q1 is connected with one end of the resistor R1 and a main control circuit 25 (e.g., a seventh pin of the chip U1) respectively, the other end of the resistor R1 is connected to a power supply V, and a pole e of the NPN triode Q1 and the other end of the resistor R3 are grounded. The power-on detection circuit 22 DETECTs the power supply voltage input by the power supply interface circuit 11 (USB Type-C interface), determines the voltage value that can trigger identification through resistor voltage division, plays a role in judging whether the USB Type-C interface has an effective power supply input, and outputs the judging result to the main control circuit 25 (i.e., the singlechip, such as the seventh pin of the access chip U1) through the C pole (vbus_detect pin) of the NPN triode Q1 as a judging basis for the next action of the singlechip.

In this embodiment, the PD identification negotiation circuit 23 includes a resistor R4, a resistor R5, a resistor R6, and a resistor R7, wherein one end of the resistor R4 and one end of the resistor R5 are both connected to the master control circuit 25 (e.g., the tenth pin of the chip U1), the other end of the resistor R4 is respectively connected to one end of the resistor R6 and the power supply interface circuit 11 (e.g., the A5 pin of the chip J1), the other end of the resistor R5 is respectively connected to one end of the resistor R7 and the power supply interface circuit 11 (e.g., the B5 pin of the chip J1), and the other end of the resistor R6 and the other end of the resistor R7 are both grounded. The PD identification negotiation circuit 23 may support negotiation of A5V voltage domain, and increase the ground resistance of 5.1K on the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 to inform the supporting PD protocol power adapter 100 to negotiate handshake to enter the basic PD protocol power supply, the power supply level is 5V voltage domain, and the maximum current may reach 3A, and the specific current depends on the power supply capability supported by the power adapter 100. The A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 are respectively connected in parallel through resistors connected in series and then are input into the main control module 25 (namely, a singlechip, such as a tenth pin of the chip U1), the singlechip distinguishes the power supply CURRENT of the power adapter 100 according to the size of the identified ADC value to intelligently adjust the load of the electronic terminal 200, the relation table of the power supply CURRENT level standard of the PD protocol 5V voltage domain and the output level of the CC pins (the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1) is shown as follows, and the singlechip is matched with the voltage value acquired by the PD_CURRENT_ADC pin to be compared and confirmed one by one according to the following table parameters.

PD protocol 5V voltage domain power supply current level standard and CC pin output level relation table

Power supply current gear	Minimum voltage of CC foot	Maximum voltage of CC foot	Change threshold
				5V 500mA	0.25V	0.61V	0.66V
5V 1.5A	0.70V	1.16V	1.23V
				5V 3A	1.31V	2.04V

In this embodiment, the QC identification negotiation circuit 24 includes a first power matching circuit 241, a level detection circuit 242, and a second power matching circuit 243, wherein the first power matching circuit 241 is respectively connected to the master control circuit 25 and the power supply interface circuit 11, the second power matching circuit 243 is respectively connected to the master control circuit 25 and the power supply interface circuit 11, and the level detection circuit 242 is respectively connected to the master control circuit 25 and the power supply interface circuit 11.

Specifically, the first power matching circuit 241 includes an NPN triode Q2, a resistor R8, a resistor R9, a resistor R10, and a resistor R11, wherein a c-pole of the NPN triode Q2 is connected to the power supply V, an e-pole of the NPN triode Q2 is connected to one end of the resistor R10 and the power supply interface circuit 11 (e.g., an A7 pin and a B7 pin of the chip J1) respectively through the resistor R8, the other end of the resistor R10 is grounded, a B-pole of the NPN triode Q2 is connected to one end of the resistor R9 and one end of the resistor R11 respectively, the other end of the resistor R11 is grounded, and the other end of the resistor R9 is connected to the main control circuit 25 (e.g., a fourteenth pin of the chip U1).

Specifically, the level detection circuit 242 includes an NMOS transistor Q3, a resistor R12, and a resistor R13, wherein a D electrode of the NMOS transistor Q3 is connected to one end of the resistor R12 and the master control circuit, the other end of the resistor R12 is connected to the power source V, a G electrode of the NMOS transistor Q3 is connected to the power supply interface circuit 11 (e.g., an A7 pin and a B7 pin of the chip J1) through the resistor R13, and an S electrode of the NMOS transistor Q3 is grounded.

Specifically, the second power matching circuit 243 includes an NPN transistor Q4, an NPN transistor Q5, an NPN transistor Q6, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, and a resistor R22;

the c pole of the NPN triode Q4 is connected to the power supply V, the e pole of the NPN triode Q4 is connected to one end of the resistor R16 and the power supply interface circuit 11 (e.g. pin A6 and pin B6 of the chip J1) respectively through the resistor R14, the other end of the resistor R16 is grounded, the B pole of the NPN triode Q4 is connected to one end of the resistor R15 and one end of the resistor R17 respectively, and the other end of the resistor R15 is connected to the main control circuit 25 (e.g. thirteenth pin of the chip U1);

the c pole of the NPN triode Q5 is connected to the power supply V, the e pole of the NPN triode Q5 is connected to the power supply interface circuit 11 (e.g. pin A6 and pin B6 of the chip J1) through the resistor R18, the B pole of the NPN triode Q5 is connected to one end of the resistor R21, one end of the resistor R19 and the c pole of the NPN triode Q6, respectively, and the other end of the resistor R21 is grounded;

the b pole of the NPN triode Q6 is connected to one end of the resistor R20 and one end of the resistor R22, the other end of the resistor R19 and the other end of the resistor R20 are both connected to the main control circuit 25 (e.g., the other end of the resistor R19 is connected to the fourteenth pin of the chip U1, and the other end of the resistor R20 is connected to the thirteenth pin of the chip U1), and the other end of the resistor R22 and the e pole of the NPN triode Q6 are both grounded. The QC identification negotiation circuit 24 employs QC2.0.

Among these, QC identification negotiation circuit 24 may support negotiations of 5V, 9V and 12V voltage domains, and the process first needs to enter a handshake phase: in the initial state, the main control module 25 (single chip microcomputer) sets the voltage values of the thirteenth pin (qc2.0_gpio 1 pin) and the fourteenth pin (qc2.0_gpio 2 pin) of the chip U1 to 0V, no input voltage is applied to the DM pins (DM 1 pin and DM2 pin) and the DP pins (DP 1 pin and DP2 pin) of the chip J1, at this time, the NMOS transistor Q3 in the level detection circuit 242 is not turned on, and the resistor R12 pulls the high level, i.e., the twelfth pin (qc2.0_detect pin) of the chip U1 outputs the high level; the singlechip identifies whether a power input exists in the power supply circuit 21 through a seventh pin (VBUS_DETECT pin) of the chip U1, namely, whether a supported power adapter 100 is inserted is judged, after the power supply circuit 22 judges that the power adapter 100 is inserted, the singlechip outputs 3.3V through setting a QC2.0_GPIO1 pin, the QC2.0_GPIO2 pin keeps 0V, under the action of a second power matching circuit 243, 0.6V voltage is output through a DP pin of the power supply interface circuit 11, the power adapter 100 supporting QC2.0 protocol receives the voltage signal and enters a negotiation handshake process, meanwhile, the inside of the power adapter 100 conducts the DM pin and the DP pin, so that the DM pin also outputs 0.6V voltage, at the moment, an NMOS tube Q3 in the level detection circuit 242 is conducted, the level is pulled down by a resistor R13, namely, the QC2.0_DETECT pin is output to be low level, and the level is identified to change by the 2.0_DET pin. After the DM pin and the DP pin are turned on for 1.2 seconds, the power adapter 100 automatically disconnects the DM pin from the DP pin, at this time, the DM pin outputs 0V, the NMOS Q3 in the level detection circuit 242 is not turned on, the level is pulled up by the resistor R12, that is, the output of the QC2.0_detect pin changes to the high level again, and the singlechip of the electronic terminal 200 enters the negotiation handshake process after receiving the voltage signal. Thereby completing the handshake between the electronic terminal 200 and the power adapter 100, between which a negotiation may be performed to adjust the required power.

Then the singlechip enters a power class adjustment stage, and the singlechip adjusts the output voltage values of the QC2.0_GPIO1 pin and the QC2.0_GPIO2 pin according to the load power supply requirement of the system to control the levels of the DP pin and the DM pin of the power supply interface circuit, so as to inform the power adapter 100 of the voltage domain required to be provided. The relevant DP, DM levels and power adapter supply voltage domain relationships are shown in the table below.

QC2.0 protocol output voltage domain and DP, DM voltage value relation table

DP	DM	Power adapter output voltage domain
			0.6V	0V	5V
3.3V	0.6V	9V
			0.6V	0.6V	12V

In order to realize the voltage values required by the relation diagram of the table, the QC2.0_GPIO1 pin and the QC2.0_GPIO2 pin need to perform combined actions, and a corresponding conversion circuit is added to realize level conversion and meet the relation requirement of the table, and the relation action table of the lower diagram design circuit diagram is as follows:

the QC2.0_GPIO1 pin and QC2.0_GPIO2 pin combination form outputs the corresponding table of the relation between the DP pin and the DM pin.

QC2.0_GPIO1	QC2.0_GPIO2	DP	DM
				3.3V	0V	0.6V	0V
0V	3.3V	3.3V	0.6V
				3.3V	3.3V	0.6V	0.6V

As can be seen from the two tables, when the QC2.0_gpio1 pin outputs a high level (e.g., 3.3V) and the QC2.0_gpio2 pin outputs a low level (e.g., 0V), the power adapter 100 adjusts to power into the 5V voltage domain. When QC2.0_GPIO1 pin outputs low level (0V, for example), QC2.0_GPIO2 pin outputs high level (3.3V, for example), the power adapter adjusts to enter 9V voltage domain for power supply. When QC2.0_GPIO1 pin outputs high level (e.g., 3.3V), QC2.0_GPIO2 pin outputs high level (e.g., 3.3V), power adapter 100 adjusts to enter 12V voltage domain for power supply.

In this embodiment, the master control circuit 25 includes a chip U1, a resistor R137, a resistor R138, a capacitor C106, and a capacitor C107, where the model of the chip U1 is STM32F030F4;

the seventh pin of the chip U1 is connected to the power-on detection circuit 22 (e.g., the c pole of the NPN triode Q1), the tenth pin of the chip U1 is connected to the PD identification negotiation circuit 23 (e.g., the resistor R4 and the resistor R5), the twelfth pin, the thirteenth pin and the fourteenth pin of the chip U1 are all connected to the QC identification negotiation circuit 24 (e.g., the twelfth pin of the chip U1 is connected to the D pole of the NMOS tube Q3, the thirteenth pin of the chip U1 is connected to the resistor R15 and the resistor R20, and the fourteenth pin of the chip U1 is connected to the resistor R9 and the resistor R19, respectively); the sixteenth pin, the fifth pin, one end of the resistor R137, one end of the resistor R138 and one end of the capacitor C106 of the chip U1 are all connected to the power supply V, the first pin of the U1 is connected to the other end of the resistor R138, the fourth pin of the chip U1 is respectively connected to the other end of the resistor R137 and one end of the capacitor C107, and the fifteenth pin of the chip U1, the other end of the capacitor C106 and the other end of the capacitor C107 are all grounded; the second pin, the third pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the seventeenth pin, the eighteenth pin, the nineteenth pin and the twentieth pin of the chip U1 are all suspended.

Example 1

When the power adapter 100 supports only the PD fast charge protocol, the power adapter 100 only provides 5V of power for charging. The singlechip identifies whether the power supply circuit 21 has power input or not through the power-on detection circuit 22 connected with the VBUS_DETECT pin, namely, whether the power adapter 100 is plugged in is judged, if the power adapter 100 has power supply, the power-on detection circuit 22 sends an identified detection signal to the singlechip; meanwhile, the power supply interface circuit 11 sends a voltage value to the pd_current_adc pin of the singlechip through the CC1 pin and the CC2 pin, and the singlechip judges the power which can be provided by the power adapter 100 through the voltage value collected by the pd_current_adc pin.

If the output voltage values of the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 are in the range of 0.25V to 0.61V, for example: the output voltage values of the pin A5 and the pin B5 of the chip J1 are both 0.5V, and the single chip microcomputer recognizes that the pin pd_current_adc collects the corresponding voltage value, which indicates that the power supply CURRENT file that the power adapter 100 can provide at this time is: 5V 500mA, at this time, the electronic terminal 200 needs to adjust the system load suitable for charging under the power supply current level according to the power supply current level;

if the output voltage values of the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 are in the range of 0.70V to 1.16V, for example: the output voltage values of the pin A5 and the pin B5 of the chip J1 are both 0.8V, and the single chip microcomputer recognizes that the pin pd_current_adc collects the corresponding voltage value, which indicates that the power supply CURRENT file that the power adapter 100 can provide at this time is: 5V 1.5A, at this time, the electronic terminal 200 needs to adjust the system load suitable for charging under the power supply current level according to the power supply current level;

if the output voltage values of the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 are in the range of 1.31V to 2.04V, the following are: the output voltage values of the pin A5 and the pin B5 of the chip J1 are both 1.5V, and the single chip microcomputer recognizes that the pin pd_current_adc collects the corresponding voltage value, which indicates that the power supply CURRENT file that the power adapter 100 can provide at this time is: 5v 3a, at this time, the electronic terminal 200 needs to adjust a system load suitable for charging in the power supply current range according to the power supply current range;

if the output voltage values of the A5 pin (CC 1) and the B5 pin (CC 2) of the chip J1 are not in the above listed ranges, the singlechip identifies that the pd_current_adc pin collects the corresponding voltage value, and the singlechip cannot know the power supply CURRENT level that can be provided by the power adapter 100 at this time, and the power adapter 100 defaults to provide the lowest power: and 5V 500mA is used for charging the electronic terminal.

Example 2

When the power adapter 100 supports only the QC-fast-charge protocol, the power adapter 100 may provide 5V, 9V, and 12V power for charging. The singlechip identifies whether the power supply circuit 21 has power input or not through the power-on detection circuit 22 connected with the VBUS_DETECT pin, namely, whether the power adapter 100 is plugged in is judged, if the power adapter 100 has power supply, the power-on detection circuit 22 sends an identified detection signal to the singlechip; meanwhile, the singlechip adjusts output voltage values of the QC2.0_GPIO1 pin and the QC2.0_GPIO2 pin according to load power supply requirements of a system of the singlechip to control the levels of the DP pin and the DM pin of the power supply interface circuit 11, so that a voltage domain required to be provided by the power adapter 100 is informed.

If the system load of the singlechip needs 5V power for power supply, the singlechip adjusts the output voltage value of the QC2.0_GPIO1 pin to be 3.3V and the output voltage value of the QC2.0_GPIO2 pin to be 0V, so as to control the input voltage value of the DP pin of the power supply interface circuit 11 to be 0.6V and the voltage value of the DM pin to be 0V, thereby informing the power supply adapter 100 that the voltage domain needed to be provided is 5V, and at the moment, the power supply adapter 100 outputs 5V power to the power supply circuit 21 through the power supply interface circuit 11, and provides 5V power for the system load of the electronic terminal 200 through the power supply circuit 21;

if the system load of the singlechip needs 9V power for power supply, the singlechip adjusts the output voltage value of the QC2.0_GPIO1 pin to 0V and the output voltage value of the QC2.0_GPIO2 pin to 3.3V to control the input voltage value of the DP pin of the power supply interface circuit 11 to 3.3V and the voltage value of the DM pin to 0.6V, so as to inform the power supply adapter 100 that the voltage domain required to be provided is 9V, and at the moment, the power supply adapter 100 outputs 9V power to the power supply circuit 21 through the power supply interface circuit 11 and provides 9V power for the system load of the electronic terminal 200 through the power supply circuit 21;

if the system load of the singlechip needs 12V power for power supply, the singlechip adjusts the output voltage value of the QC2.0_gpio1 pin to 3.3V and the output voltage value of the QC2.0_gpio2 pin to 3.3V to control the input voltage value of the DP pin of the power supply interface circuit 11 to 0.6V and the voltage value of the DM pin to 0.6V, so as to inform the power adapter 100 that the voltage domain required to be provided is 12V, at this time, the power adapter 100 outputs 12V power to the power supply circuit 21 through the power supply interface circuit 11, and provides 12V power for the system load of the electronic terminal 200 through the power supply circuit 21.

Example 3

When the power adapter 100 supports both the PD fast charge protocol and the QC fast charge protocol, the power adapter 100 may provide 5V, 9V, and 12V power for charging.

According to the schemes of embodiment 1 and embodiment 2, the power adapter 100 can send voltage signals to the singlechip at the same time, and the singlechip can select a required scheme to supply power.

The foregoing description is only a partial embodiment of the present utility model, and is not intended to limit the scope of the present utility model, and all equivalent devices or equivalent processes using the descriptions and the drawings of the present utility model or directly or indirectly applied to other related technical fields are included in the scope of the present utility model.

Claims

1. The system for negotiating and adjusting the power supply capacity with the power adapter is characterized by being applied to the power adapter and the electronic terminal; the system comprises: the power supply interface circuit is positioned in the power adapter, and the power supply circuit, the power-on detection circuit, the PD identification negotiation circuit, the QC identification negotiation circuit and the main control circuit are positioned in the electronic terminal;

2. The system for negotiating power supply capability adjustment with a power adapter according to claim 1, wherein the power supply interface circuit comprises a chip J1, the A4 pin, the A9 pin, the B4 pin and the B9 pin of the chip J1 are all connected to a power supply circuit, the A5 pin and the B5 pin of the chip J1 are all connected to a PD identification negotiation circuit, and the A7 pin, the A6 pin, the B7 pin and the B6 pin of the chip J1 are all connected to a QC identification negotiation circuit; the chip J1 is characterized in that the A1 pin, the A12 pin, the B1 pin, the B12 pin, the G1 pin, the G2 pin, the G3 pin, the G4 pin, the G5 pin and the G6 pin of the chip J1 are all grounded, and the A8 pin, the B8 pin, the A3 pin, the A2 pin, the B10 pin, the B11 pin, the B3 pin, the B2 pin, the A10 pin and the A11 pin of the chip J1 are suspended.

3. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 1, wherein the power-on detection circuit comprises an NPN triode Q1, a resistor R2 and a resistor R3, a pole b of the NPN triode Q1 is respectively connected with one end of the resistor R2 and one end of the resistor R3, the other end of the resistor R2 is connected to a power supply circuit, a pole c of the NPN triode Q1 is respectively connected with one end of the resistor R1 and a main control circuit, the other end of the resistor R1 is connected to a power supply V, and poles e of the NPN triode Q1 and the other end of the resistor R3 are grounded.

4. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 1, wherein the PD identification negotiation circuit comprises a resistor R4, a resistor R5, a resistor R6 and a resistor R7, wherein one end of the resistor R4 and one end of the resistor R5 are connected to the master control circuit, the other end of the resistor R4 is connected to one end of the resistor R6 and the power supply interface circuit, the other end of the resistor R5 is connected to one end of the resistor R7 and the power supply interface circuit, and the other end of the resistor R6 and the other end of the resistor R7 are grounded.

5. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 1, wherein said QC identification negotiation circuit comprises a first power matching circuit, a second power matching circuit and a level detection circuit, said first power matching circuit being connected to the master control circuit and the power supply interface circuit, respectively, said second power matching circuit being connected to the master control circuit and the power supply interface circuit, respectively, and said level detection circuit being connected to the master control circuit and the power supply interface circuit, respectively.

6. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 5, wherein said first power matching circuit comprises an NPN triode Q2, a resistor R8, a resistor R9, a resistor R10 and a resistor R11, a c pole of said NPN triode Q2 is connected to a power source V, an e pole of said NPN triode Q2 is connected to one end of said resistor R10 and a power supply interface circuit through said resistor R8, another end of said resistor R10 is grounded, a b pole of said NPN triode Q2 is connected to one end of said resistor R9 and one end of said resistor R11, another end of said resistor R11 is grounded, and another end of said resistor R9 is connected to a master control circuit.

7. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 5, wherein said level detection circuit comprises an NMOS transistor Q3, a resistor R12 and a resistor R13, wherein the D pole of said NMOS transistor Q3 is connected to one end of said resistor R12 and a master control circuit, respectively, the other end of said resistor R12 is connected to a power source V, the G pole of said NMOS transistor Q3 is connected to a power supply interface circuit through said resistor R13, and the S pole of said NMOS transistor Q3 is grounded.

8. The system for negotiating power supply capability with a power adapter according to claim 5, wherein said second power matching circuit comprises NPN transistor Q4, NPN transistor Q5, NPN transistor Q6, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21 and resistor R22;

9. The system for negotiating and adjusting power supply capacity with a power adapter according to claim 1, wherein said main control circuit comprises a chip U1, a resistor R137, a resistor R138, a capacitor C106 and a capacitor C107, a seventh pin of said chip U1 is connected to a power-on detection circuit, a tenth pin of said chip U1 is connected to a PD identification negotiation circuit, and a twelfth pin, a thirteenth pin and a fourteenth pin of said chip U1 are all connected to a QC identification negotiation circuit; the sixteenth pin, the fifth pin, one end of the resistor R137, one end of the resistor R138 and one end of the capacitor C106 of the chip U1 are all connected to the power supply V, the first pin of the U1 is connected to the other end of the resistor R138, the fourth pin of the chip U1 is respectively connected to the other end of the resistor R137 and one end of the capacitor C107, and the fifteenth pin of the chip U1, the other end of the capacitor C106 and the other end of the capacitor C107 are all grounded; the second pin, the third pin, the sixth pin, the eighth pin, the ninth pin, the eleventh pin, the seventeenth pin, the eighteenth pin, the nineteenth pin and the twentieth pin of the chip U1 are all suspended.

10. A system for negotiating power supply capability with a power adapter as claimed in claim 9, wherein said chip U1 is of the type STM32F030F4; the model of the chip J1 is MUP-U20201.