CN218995898U - High-precision IRIG-BAC time code generator based on FPGA - Google Patents
High-precision IRIG-BAC time code generator based on FPGA Download PDFInfo
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- CN218995898U CN218995898U CN202320180649.0U CN202320180649U CN218995898U CN 218995898 U CN218995898 U CN 218995898U CN 202320180649 U CN202320180649 U CN 202320180649U CN 218995898 U CN218995898 U CN 218995898U
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Abstract
The utility model discloses a high-precision IRIG-BAC time code generator based on an FPGA (field programmable gate array), which relates to the technical field of time synchronization and comprises an FPGA core module, a high-precision DA (digital-analog) conversion module, an ultra-low noise amplification module and an IRIG-BAC output module, wherein the FPGA core module is used for receiving, demodulating and outputting reference time information; the IRIG-BAC time code output by the high-precision IRIG-BAC time code generator based on the FPGA has the advantages of small noise, high waveform reduction degree, high synchronization precision, realization of 100ns level, small debugging difficulty and short delivery cycle.
Description
Technical Field
The utility model relates to the technical field of time synchronization, in particular to a high-precision IRIG-BAC time code generator based on an FPGA.
Background
At present, the traditional IRIG-BAC time code generation module adopts an analog circuit implementation mode, so that the output IRIG-BAC time code has large noise, waveform distortion, low synchronization precision as a subtle level and large debugging difficulty.
Disclosure of Invention
The utility model aims to solve the problems and designs a high-precision IRIG-BAC time code generator based on the FPGA.
The utility model realizes the above purpose through the following technical scheme:
high-precision IRIG-BAC time code generator based on FPGA includes:
an FPGA core module; the FPGA core module is used for receiving, demodulating and outputting reference time information;
a high-precision DA conversion module; the high-precision DA conversion module is used for performing high-precision low-noise DA conversion on the reference time information to generate a high-precision analog time signal, and the signal output end of the FPGA core module is connected with the signal input end of the high-precision DA conversion module;
an ultra-low noise amplification module; the ultra-low noise amplification module is used for carrying out ultra-low noise amplification and low-pass filtering on the high-precision analog time signal, suppressing the amplified signal noise, and the signal output end of the high-precision DA conversion module is connected with the signal input end of the ultra-low noise amplification module;
IRIG-BAC output module; the IRIG-BAC output module is used for generating an IRIG-BAC waveform according to the high-precision analog time signal processed by the ultra-low noise amplification module, filtering the high-frequency signal through a 2-order pi-type filter with the cut-off frequency of 1.9khz, and reducing output signal noise and burrs, so that the second pulse precision after decoding is greatly improved, and the signal output end of the ultra-low noise amplification module is connected with the signal input end of the IRIG-BAC output module.
The utility model has the beneficial effects that: the IRIG-BAC time code output by the high-precision IRIG-BAC time code generator based on the FPGA has the advantages of small noise, high waveform reduction degree, high synchronization precision, realization of 100ns level, small debugging difficulty and short delivery cycle.
Drawings
FIG. 1 is a schematic diagram of the structure of the FPGA-based high-precision IRIG-BAC timecode generator of the present utility model.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present utility model, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, or the directions or positional relationships conventionally put in place when the inventive product is used, or the directions or positional relationships conventionally understood by those skilled in the art are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific direction, be configured and operated in a specific direction, and therefore should not be construed as limiting the present utility model.
Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, terms such as "disposed," "connected," and the like are to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
The following describes specific embodiments of the present utility model in detail with reference to the drawings.
As shown in fig. 1, the high-precision IRIG-BAC timecode generator based on FPGA includes:
an FPGA core module; the FPGA core module is used for receiving, demodulating and outputting reference time information;
a high-precision DA conversion module; the high-precision DA conversion module is used for performing high-precision low-noise DA conversion on the reference time information to generate a high-precision analog time signal, and the signal output end of the FPGA core module is connected with the signal input end of the high-precision DA conversion module;
an ultra-low noise amplification module; the ultra-low noise amplification module is used for carrying out ultra-low noise amplification and low-pass filtering on the sinusoidal signals, suppressing the amplified signal noise, and the signal output end of the high-precision DA conversion module is connected with the signal input end of the ultra-low noise amplification module;
IRIG-BAC output module; the IRIG-BAC output module is used for generating an IRIG-BAC waveform according to the sinusoidal signal processed by the ultralow noise amplification module, filtering high-frequency signals through a 2-step pi filter with the cutoff frequency of 1.9khz, and reducing output signal noise and burrs, so that the second pulse precision after decoding is greatly improved, and the signal output end of the ultralow noise amplification module is connected with the signal input end of the IRIG-BAC output module.
The FPGA core module comprises an FPGA chip, an input circuit and an output circuit, wherein the input circuit is used for receiving and inputting external signals, the FPGA chip is used for demodulating the external signals to generate reference time information, the output circuit is used for outputting the reference time information, and a signal output end of the input circuit and a signal input end of the output circuit are respectively connected with a signal input end and a signal output end of the FPGA chip.
The high-precision DA conversion module comprises a high-precision DAC chip and a first ultralow noise LDO chip, and a signal output end of the first ultralow noise LDO chip and a signal output end of the output circuit are connected with a signal input end of the high-precision DAC chip.
The ultra-low noise amplification module comprises a low-pass filter, an ultra-low noise transimpedance amplifier, a second ultra-low noise LDO chip, an ultra-low noise operational amplifier and a gain control circuit, wherein the low-pass filter is used for carrying out low-pass filtering on a time signal, the ultra-low noise transimpedance amplifier is used for converting a current signal output by the high-precision DA conversion module into a voltage signal, the ultra-low noise operational amplifier is used for amplifying the voltage signal, the gain control circuit is used for adjusting the amplification factor of the ultra-low noise operational amplifier, the signal output end of the high-precision DA conversion module and the signal input end of the ultra-low noise transimpedance amplifier are respectively connected with the signal input end and the signal output end of the low-pass filter, the signal output end of the ultra-low noise transimpedance amplifier and the signal input end of the IRIG-BAC output module are respectively connected with the signal input end of the ultra-low noise transimpedance amplifier, the signal output end of the ultra-low noise transimpedance amplifier is respectively connected with the signal input end of the ultra-low noise transimpedance amplifier, the ultra-low noise transimpedance amplifier and the ultra-low noise operational amplifier is the same in amplification factor, the ultra-low noise transimpedance amplifier is the same type, and the ultra-low noise transimpedance amplifier is a sine power supply with the same type, and the power supply has reduced interference to the power supply.
The IRIG-BAC output module comprises an analog switch, a pi-type filter, a transformer and a third ultralow noise LDO chip, wherein the analog switch is used for controlling output waveforms, a signal input end and a signal output end of the analog switch are respectively connected with a signal output end of the ultralow noise amplification module and a signal input end of the pi-type filter, a signal input end of the transformer is connected with a signal output end of the pi-type filter, and a signal output end of the third ultralow noise LDO chip is connected with a signal input end of the analog switch.
The FPGA chip adopts a programmable chip based on a TSMC28nmHPC+ technology, and 350K programmable logic with the gate circuit number of 4.29 hundred million is cooperated with an on-chip memory, various system functional components, I/O peripherals, a programmable logic part and the like to form an on-chip programmable system with rich functions.
The high-precision IRIG-BAC time code generation module based on the FPGA has the advantages of high precision, low noise and low cost.
The model of the FPGA chip is JFMK50
The model of the high-precision DAC chip is ： AD9767ASTZ
The model of the first ultralow noise LDO chip is as follows: LT1763IS8-5, output +.5V
The low-pass filter is an RC low-pass filter composed of resistance and capacitance, and the cut-off frequency is 2.2Khz
The model of the ultra-low noise transimpedance amplifier is as follows: LTC6228IS6# TRMPBF, converting the + -20 mA current signal output by the DAC into a + -1V voltage signal
The model of the ultra-low noise operational amplifier is as follows: LTC6228IS6# TRMPBF, amplifying a voltage signal of + -1V to + -5.5V and within
The model of the gain controller is as follows: AD7376ARUZ10, the amplification factor of the ultra-low noise operational amplifier is adjusted by controlling the resistance value of the gain unit
The model of the second ultralow noise LDO chip and the third ultralow noise LDO chip is LT3032EDE#PBF, and outputs +/-5.5V
The model of the analog switch is as follows: ADG1419BRMZ, controlling the output B (AC) waveform by a switch
The pi-type filter is a 2-order pi-type low-pass filter formed by inductance and capacitance, and the model of the transformer with the cutoff frequency of 1.9Khz is as follows: TRS86003.
The technical scheme of the utility model is not limited to the specific embodiment, and all technical modifications made according to the technical scheme of the utility model fall within the protection scope of the utility model.
Claims (5)
1. The high-precision IRIG-BAC time code generator based on the FPGA is characterized by comprising the following components:
an FPGA core module; the FPGA core module is used for receiving, demodulating and outputting reference time information;
a high-precision DA conversion module; the high-precision DA conversion module is used for performing high-precision low-noise DA conversion on the reference time information to generate a high-precision analog time signal, and the signal output end of the FPGA core module is connected with the signal input end of the high-precision DA conversion module;
an ultra-low noise amplification module; the ultra-low noise amplification module is used for carrying out ultra-low noise amplification and low-pass filtering on the high-precision analog time signal, and the signal output end of the high-precision DA conversion module is connected with the signal input end of the ultra-low noise amplification module;
IRIG-BAC output module; the IRIG-BAC output module is used for generating IRIG-BAC waveforms according to the high-precision analog time signals processed by the ultra-low noise amplification module, and the signal output end of the ultra-low noise amplification module is connected with the signal input end of the IRIG-BAC output module.
2. The high-precision IRIG-BAC time code generator based on the FPGA of claim 1, wherein the FPGA core module comprises an FPGA chip, an input circuit and an output circuit, the input circuit is used for receiving an input external signal, the FPGA chip is used for demodulating the external signal to generate reference time information, the output circuit is used for outputting the reference time information, and a signal output end of the input circuit and a signal input end of the output circuit are respectively connected with a signal input end and a signal output end of the FPGA chip.
3. The FPGA-based high-precision IRIG-BAC time code generator of claim 2 wherein the high-precision DA conversion module comprises a high-precision DAC chip and a first ultra-low noise LDO chip, the signal output of the first ultra-low noise LDO chip and the signal output of the output circuit are both connected to the signal input of the high-precision DAC chip.
4. The high-precision IRIG-BAC time code generator based on the FPGA of claim 1, wherein the ultra-low noise amplification module includes a low pass filter, an ultra-low noise transimpedance amplifier, a second ultra-low noise LDO chip, an ultra-low noise operational amplifier and a gain control circuit, the low pass filter is used for low pass filtering the time signal, the ultra-low noise transimpedance amplifier is used for converting the current signal output by the high-precision DA conversion module into a voltage signal, the ultra-low noise operational amplifier is used for amplifying the voltage signal, the gain control circuit is used for adjusting the amplification factor of the ultra-low noise operational amplifier, the signal output end of the high-precision DA conversion module and the signal input end of the ultra-low noise transimpedance amplifier are respectively connected with the signal input end and the signal output end of the low pass filter, the signal output end of the ultra-low noise transimpedance amplifier and the signal input end of the IRIG-BAC output module are respectively connected with the signal input end of the ultra-low noise operational amplifier and the signal input end of the ultra-low noise operational amplifier.
5. The high-precision IRIG-BAC time code generator based on the FPGA of claim 1, wherein the IRIG-BAC output module comprises an analog switch, a pi-type filter, a transformer and a third ultra-low noise LDO chip, the analog switch is used for controlling output waveforms, a signal input end and a signal output end of the analog switch are respectively connected with a signal output end of the ultra-low noise amplification module and a signal input end of the pi-type filter, a signal input end of the transformer is connected with a signal output end of the pi-type filter, and a signal output end of the third ultra-low noise LDO chip is connected with a signal input end of the analog switch.
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