CN218995505U

CN218995505U - Voltage and current detection circuit and device thereof

Info

Publication number: CN218995505U
Application number: CN202222654784.2U
Authority: CN
Inventors: 占育锋; 刘洋; 韩佳鑫; 刘志雄
Original assignee: Shenzhen 3Nod Digital Technology Co Ltd
Current assignee: Shenzhen 3Nod Digital Technology Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2023-05-09
Anticipated expiration: 2032-09-30

Abstract

The embodiment of the application belongs to the technical field of signal sampling, and relates to a voltage and current detection circuit and a device thereof, wherein the voltage and current detection circuit comprises an interface input end, a DC-DC power supply module, a current detection module, a voltage detection module, an ADC data acquisition module, a wireless communication module and an interface output end; the interface input end transmits an input power supply to the current detection module, the voltage detection module and the DC-DC power supply module, and transmits communication data to the interface output end; the DC-DC power module provides working voltages for all modules, and the current detection module converts the collected first voltage signals into voltage amplification signals; the voltage detection module acquires a second voltage signal; the ADC data acquisition module converts the second voltage signal and the voltage amplification signal into digital signals and transmits the digital signals to the wireless communication module; the wireless communication module transmits the digital signal to the display device; the interface output end transmits the communication data to the back-end equipment. The technical scheme that this application provided can reduce manufacturing cost by a wide margin, reduces test space, reduces power consumption.

Description

Voltage and current detection circuit and device thereof

Technical Field

The present disclosure relates to the field of signal sampling technologies, and in particular, to a voltage and current detection circuit and a device thereof.

Background

There are many products in the market that support the detection of various USB interface currents and voltages, called USB voltmeters or USB voltmeters. The interface is complete, the input and the output of all interfaces such as MICRO-USB, TYPE-C, USB-A and the like are supported, and the display screen is provided, so that the numerical values of current and voltage are directly displayed, and the interface is visual. However, the existing product cannot perform data transmission wirelessly, collect voltage and current data, send the voltage and current data to a computer end through a wireless WiFi module to display the voltage and current data synchronously, compare the data, and judge whether the current test value meets the test standard requirement.

The traditional production test link is to detect the voltage and the current of the power supply end of the equipment by using a digital precise direct current power supply and matching with control software matched with a computer end, so as to judge whether the working voltage and the working current of the equipment are normal. The price of the digital precise direct current power supply is generally expensive, and enterprises need to purchase tens or even hundreds of digital precise direct current power supplies with high precision in order to meet the production efficiency in the production link, so that the manufacturing cost of the enterprises is high, and the production cost of the enterprises is increased. Meanwhile, the digital precise direct current power supply occupies a large amount of test space and has high power consumption.

Disclosure of Invention

The technical problem to be solved by the embodiment of the application is that the production link test equipment in the related technology is high in cost, occupies a large amount of test space and is high in power consumption.

In order to solve the above technical problems, the embodiments of the present application provide a voltage and current detection circuit, which adopts the following technical scheme:

the device comprises an interface input end, a DC-DC power module, a current detection module, a voltage detection module, an ADC data acquisition module, a wireless communication module and an interface output end;

the interface input end is respectively connected to the DC-DC power supply module, the current detection module, the voltage detection module and the interface output end, and is used for transmitting an input power supply to the current detection module, the voltage detection module and the DC-DC power supply module through power lines and transmitting communication data to the interface output end through data lines;

the DC-DC power module is connected with the current detection module, the ADC data acquisition module and the wireless communication module and is used for providing working voltages for the current detection module, the ADC data acquisition module and the wireless communication module;

the current detection module is connected to the ADC data acquisition module and the interface output end and is used for acquiring a first voltage signal of the input power supply and transmitting a voltage amplification signal obtained by proportionally converting the first voltage signal to the ADC data acquisition module, wherein the first voltage signal is used for calculating the current of the input power supply;

The voltage detection module is connected with the ADC data acquisition module and is used for acquiring a second voltage signal of the input power supply and transmitting the second voltage signal to the ADC data acquisition module;

the ADC data acquisition module is connected to the wireless communication module and is used for carrying out analog-to-digital conversion on the second voltage signal and the voltage amplification signal to obtain a digital signal, and transmitting the digital signal to the wireless communication module;

the wireless communication module is connected with a display device through a wireless signal and is used for transmitting the digital signal to the display device so as to display the acquired voltage and current of the input power supply;

the interface output end is connected to the back-end equipment and is used for transmitting the communication data to the back-end equipment.

Further, the interface input end comprises an interface input chip, a first filter circuit and an electrostatic protection circuit;

the interface input chip comprises a power input end, a data receiving interface, a first communication interface and a first channel configuration interface, wherein the power input end transmits the input power to the current detection module, the voltage detection module and the DC-DC power module through the power line; the data receiving interface, the first communication interface and the first channel configuration interface are connected to the interface output end;

The first end of the first filter circuit is respectively connected with the power input end and the input power, and the second end of the first filter circuit is grounded and used for filtering interference signals in the input power;

the first end of the electrostatic protection circuit is respectively connected with the power input end and the input power supply, and the second end of the electrostatic protection circuit is grounded and used for electrostatic discharge and surge relief.

Further, the current detection module comprises a first current detection chip and a sampling resistor, wherein a first power supply voltage pin, a first grounding pin, a first positive current detection pin, a first negative current detection pin, a first output pin and a first turn-off control pin are arranged on the first current detection chip;

the first power supply voltage pin is connected with the working voltage output by the DC-DC power supply module, the first grounding pin is grounded, the first positive current detection pin is connected with the first end of the sampling resistor, the first negative current detection pin is connected with the second end of the sampling resistor, the first output pin is connected to the ADC data acquisition module, and the first turn-off control pin is connected to the input power supply;

The first end of the sampling resistor is connected with the input power supply, and the second end of the sampling resistor is connected with the output end of the interface through the output power supply of the power line.

Further, the current detection module further comprises a second current detection chip, and a second power supply voltage pin, a second grounding pin, a second positive current detection pin, a second negative current detection pin, a second output pin and a second turn-off control pin are arranged on the second current detection chip;

the second power supply voltage pin is connected with the DC-DC power supply module, the second grounding pin is grounded, the second positive current detection pin is connected with the second end of the sampling resistor, the first negative current detection pin is connected with the first end of the sampling resistor, the second output pin is connected with the ADC data acquisition module, and the second turn-off control pin is connected with the input power supply.

Further, the ADC data collection module includes a voltage detection chip, where the voltage detection chip is provided with a third ground pin, an analog voltage pin, a reference voltage pin, a voltage signal input pin, a current input signal pin, a channel selection pin, a pull-down enable pin, an output serial interface, and a digital voltage pin;

The third grounding pin is grounded; the analog voltage pin, the reference voltage pin and the digital voltage pin are connected with a voltage output end of the DC-DC power supply module; the reference voltage pin is connected with the voltage output end of the DC-DC power supply module; the voltage signal input pin is connected with the interface input end; the current input signal pin is connected with the current detection module; the channel select pin and the pull-down enable pin are connected to the wireless communication module; the output serial interface is connected with the wireless communication module and is used for transmitting the digital signal to the wireless communication module.

Further, the wireless communication module comprises a wireless communication chip, wherein the wireless communication chip is provided with a reset pin, an enable pin, a third power supply voltage pin, an input serial interface, a first general input and output pin, a second general input and output pin and an indicator lamp control pin;

the reset pin is connected with a reset circuit; the enabling pin and the third power supply voltage pin are connected with the voltage output end of the DC-DC power supply module; the input serial interface is connected with the output serial interface; the first general input and output pin is connected with the pull-down enabling pin; the second common input and output pins are connected with the channel selection pins; the indicator lamp control pin is connected to the indicator lamp circuit and used for controlling the on or off of the indicator lamp.

Further, the pilot lamp circuit includes first resistance, second resistance, switch tube and pilot lamp, wherein:

the common connection point of the first end of the first resistor and the first end of the second resistor is connected with the voltage output end of the DC-DC power supply module, and the second end of the first resistor is respectively connected with the control pin of the indicator lamp and the grid electrode of the switching tube;

the second end of the second resistor is connected with the drain electrode of the switching tube;

the source electrode of the switch tube is connected with the indicator lamp.

Further, the DC-DC power module comprises a power chip, a charging unit, an overload short-circuit protection unit, a voltage division unit and an acquisition unit, wherein:

the power supply chip is connected to the input power supply through an input end of the power supply chip and performs voltage conversion on the input power supply;

the first end of the charging unit is connected with the input power supply and the input end of the power supply chip respectively, the second end of the charging unit is connected to the enabling end of the power supply chip, and the third end of the charging unit is grounded;

the first input end of the overload short-circuit protection unit is connected with the voltage bootstrap end of the power supply chip, the second input end of the overload short-circuit protection unit is connected with the switch end of the power supply chip, and the output end of the overload short-circuit protection unit is connected with the current detection module, the ADC data acquisition module and the wireless communication module;

The input end of the voltage dividing unit is connected with the feedback end of the power supply chip, and the output end of the voltage dividing unit is commonly connected with the output end of the overload short-circuit protection unit;

the first input end of the acquisition unit is connected with the voltage acquisition end of the power chip, the second input end of the acquisition unit is connected with the load switching end of the power chip, and the output end of the acquisition unit is grounded.

Further, the interface output end comprises an interface output chip and a second filter circuit;

the interface output chip is connected with the current detection module and the first end of the second filter circuit through an output power supply, and a data output interface and a second communication interface of the interface output chip are connected with the interface input end;

the second end of the second filter circuit is grounded and used for filtering interference signals in the circuit.

In order to solve the above technical problems, the embodiments of the present application further provide a voltage and current detection device, which adopts the following technical scheme:

the device comprises an adapter, a display device, a back-end device and a voltage and current detection circuit as described above;

the adapter is connected to the interface input end through a TYPE-C interface and is used for providing starting voltage for the voltage and current detection circuit;

The display equipment is connected with the wireless communication module through wireless signals and is used for displaying the acquired voltage and current of the input power supply after digital-to-analog conversion of the received digital signals;

the back-end equipment is connected with the interface output end through a power data input interface and is used for receiving communication data.

Compared with the prior art, the embodiment of the application has the following main beneficial effects:

the voltage and current detection circuit comprises an interface input end, a DC-DC power supply module, a current detection module, a voltage detection module, an ADC data acquisition module, a wireless communication module and an interface output end; the interface input end is respectively connected to the DC-DC power supply module, the current detection module, the voltage detection module and the interface output end, and is used for transmitting an input power supply to the current detection module, the voltage detection module and the DC-DC power supply module through power lines and transmitting communication data to the interface output end through data lines; the DC-DC power module is connected with the current detection module, the ADC data acquisition module and the wireless communication module and is used for providing working voltages for the current detection module, the ADC data acquisition module and the wireless communication module; the current detection module is connected to the ADC data acquisition module and the interface output end and is used for acquiring a first voltage signal of the input power supply and transmitting a voltage amplification signal obtained by proportionally converting the first voltage signal to the ADC data acquisition module, wherein the first voltage signal is used for calculating the current of the input power supply; the voltage detection module is connected with the ADC data acquisition module and is used for acquiring a second voltage signal of the input power supply and transmitting the second voltage signal to the ADC data acquisition module; the ADC data acquisition module is connected to the wireless communication module and is used for carrying out analog-to-digital conversion on the second voltage signal and the voltage amplification signal to obtain a digital signal and transmitting the digital signal to the wireless communication module; the wireless communication module is connected with the display equipment through wireless signals and is used for transmitting digital signals to the display equipment so as to display the acquired voltage and current of the input power supply; the interface output end is connected to the back-end equipment and used for transmitting communication data to the back-end equipment; the voltage and current detection circuit replaces a digital precise direct current power supply used in the traditional production test link to detect the voltage and current of the equipment power supply end, so that whether the equipment working voltage and current are normal or not is judged, the implementation mode is simple, the production cost can be greatly reduced, the occupied test space is reduced, and the power consumption is reduced.

Drawings

For a clearer description of the solution in the present application, a brief description will be given below of the drawings that are needed in the description of the embodiments, it being obvious that the drawings in the following description are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a voltage-current detection circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a voltage and current detection device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of one embodiment of an interface input provided herein;

FIG. 4 is a schematic diagram of another embodiment of an interface input provided herein;

FIG. 5 is a schematic diagram of one embodiment of a current detection module provided herein;

FIG. 6 is a schematic diagram of one embodiment of an ADC data acquisition module provided herein;

fig. 7 is a schematic structural diagram of one embodiment of a wireless communication module provided herein;

FIG. 8 is a schematic diagram of one embodiment of an indicator light circuit provided herein;

FIG. 9 is a schematic diagram of one embodiment of a DC-DC power module provided herein;

Fig. 10 is a schematic structural diagram of an embodiment of an interface output provided in the present application.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The embodiment of the application provides a voltage and current detection circuit 1, referring to fig. 1 and 2, the voltage and current detection circuit 1 includes an interface input terminal 10, a DC-DC power module 20, a current detection module 30, a voltage detection module 40, an ADC data acquisition module 50, a wireless communication module 60, and an interface output terminal 70.

The interface input end 10 is externally connected to an interface corresponding to the adapter, and is connected to the DC-DC power module 20, the current detection module 30, the voltage detection module 40 and the interface output end 70 respectively, and is configured to receive an input power transmitted by the adapter, provide a starting voltage for the voltage-current detection circuit 1, specifically, transmit an input power usb_vbus to the current detection module 30, the voltage detection module 40 and the wireless communication module 60 through a power line, and transmit received communication data to the interface output end 70 through a data line.

The DC-DC power module 20 is connected to the current detection module 30, the ADC data acquisition module 50 and the wireless communication module 60, and is configured to perform voltage conversion on the input power usb_vbus, and provide an operating voltage for the current detection module 30, the ADC data acquisition module 50 and the wireless communication module 60.

The current detection module 30 is connected to the ADC data acquisition module 50 and the interface output end 70, and is configured to acquire a first voltage signal of the input power supply usb_vbus, and transmit a voltage amplified signal obtained by converting the first voltage signal according to a ratio to the ADC data acquisition module 50, where the first voltage signal is used to calculate and obtain a current of the input power supply usb_vbus.

The voltage detection module 40 is connected to the ADC data acquisition module 50, and is configured to acquire a second voltage signal of the input power usb_vbus, and transmit the second voltage signal to the ADC data acquisition module 50.

The ADC data acquisition module 50 is connected to the wireless communication module 60, and is configured to perform analog-to-digital conversion on the second voltage signal and the voltage amplification signal to obtain a digital signal, and transmit the digital signal to the wireless communication module 60.

The wireless communication module 60 is connected to the display device 3 through a wireless signal, and is used for transmitting a digital signal to the display device 3 to display the collected voltage and current of the input power supply usb_vbus.

The interface output 70 is connected to the back-end device 4 for transmitting communication data to the back-end device 4 for enabling communication between the voltage current detection circuit 1 and the back-end device 4.

In this embodiment, after the voltage and current detection circuit 1 is connected in series through the interface input end 10, the data communication network (i.e. the data line) is directly connected inside the voltage and current detection circuit 1, and is communicated with the back-end device without being affected, the input power supply usb_vbus of the power supply is monitored through the current detection module 30 and the voltage detection module 40 in the voltage and current detection circuit 1, and after the monitored data is subjected to analog-to-digital conversion through the ADC data acquisition module 50, the monitored data is reported to the display device in real time through the wireless communication module 60 for displaying, and then whether the back-end device works normally can be determined according to the monitored data of the voltage and the current.

Referring to fig. 3, in the present embodiment, the interface input terminal 10 includes a TYPE-C interface input terminal including an interface input chip CON1, a first filter circuit 11, and an electrostatic protection circuit 12.

The interface input chip CON1 includes a power input end, a data receiving interface, a first communication interface and a first channel configuration interface, where the power input end transmits an input power usb_vbus to the current detection module 30, the voltage detection module 40 and the DC-DC power module 20 through power lines; the data receiving interface, the first communication interface and the first channel configuration interface are connected to the interface output 70.

Specifically, the interface input chip CON1 is provided with a pin VBUS1, a pin VBUS2, a pin VBUS3 and a pin VBUS4, and a common connection point of the pin VBUS1, the pin VBUS2, the pin VBUS3 and the pin VBUS4 is a power input end; the data receiving interface comprises a positive signal data receiving interface USB_DP and a negative signal data receiving interface USB_DN, the interface input chip CON1 is provided with a pin A_D+, a pin A_D-, a pin B_D+ and a pin B_D-, the common connection point of the pin A_D+ and the pin B_D+ is the positive signal data receiving interface USB_DP, and the common connection point of the pin A_D-and the pin B_D-is the negative signal data receiving interface USB_DN; the first communication interface comprises a first communication transmitting interface UART_TX and a first communication receiving interface UART_RX, a pin RXP1, a pin RXN1, a pin RXP2 and a pin RXN2 are arranged on an interface input chip CON1, a common connection point of the pin RXP1 and the pin RXP2 is the first communication transmitting interface UART_TX, and a common connection point of the pin RXN1 and the pin RXN2 is the first communication receiving interface UART_RX; the first channel configuration interface is a pin CC1 and a pin CC2 which are arranged on the interface input chip CON1, the voltage and current detection circuit 1 is connected with the Type-C interface through the pin CC1 and the pin CC2, and then is communicated with the adapter, after the communication is successful, the output power of the adapter can be adjusted according to the power actually required by the back-end equipment, so that the voltage output after the adjustment of the adapter is transmitted to the back-end equipment for the back-end equipment to use.

It should be appreciated that the TYPE-C interface input supports fast charging, improving charging efficiency.

In this embodiment, the positive signal data receiving interface usb_dp and the negative signal data receiving interface usb_dn are further provided with corresponding anti-series zener diodes ESD1 and ESD2, which are both used for ESD (Electro-Static discharge) protection.

The first end of the ESD1 is connected with the positive signal data receiving interface USB_DP, and the second end of the ESD1 is grounded; the first end of the ESD2 is connected with the negative signal data receiving interface USB_DN, and the second end of the ESD2 is grounded; the common connection point of the first end of the ESD1 and the positive signal data receiving interface usb_dp is used as a test point TP3, and the common connection point of the first end of the ESD2 and the negative signal data receiving interface usb_dn is used as a test point TP4 for detecting data transmission conditions.

In a specific implementation, the model of the interface input chip CON1 may select the model 41600390.

The first end of the first filter circuit 11 is connected to the power input end and the input power usb_vbus, respectively, and the second end of the first filter circuit 11 is grounded and used for filtering interference signals in the input power usb_vbus.

Specifically, the first filter circuit 11 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, where a common connection point of the first end of the first capacitor C1, the first end of the second capacitor C2, the first end of the third capacitor C3, and the first end of the fourth capacitor C4 is the first end of the first filter circuit 11; the common connection point of the second end of the first capacitor C1, the second end of the second capacitor C2, the second end of the third capacitor C3, and the second end of the fourth capacitor C4 is the second end of the first filter circuit 11.

The capacitance values of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 may be the same or different, for example, the capacitance values of the first capacitor C1 and the second capacitor C2 may be 22 μf, and the capacitance values of the third capacitor C3 and the fourth capacitor C4 may be 10nF.

The first end of the electrostatic protection circuit 12 is connected to the power input end and the input power usb_vbus, respectively, and the second end of the electrostatic protection circuit 12 is grounded for electrostatic discharge and surge relief.

Specifically, the electrostatic protection circuit 12 is an anti-series zener diode for ESD protection.

In this embodiment, a test point TP1 is disposed on a power line of a power input end of the interface input chip CON1, and a test point TP2 is disposed on a ground end for detecting an abnormal condition of a circuit.

In some optional implementations of this embodiment, the interface input chip CON1 is further provided with a pin TXP1, a pin TXN1, a pin TXP2, a pin TXN2, and pins GND1-GND10, where a common connection point of the pin TXP1 and the pin TXP2 is a BOOT5 interface, the BOOT5 interface is connected to the BOOT5 interface of the interface output end 70, a start mode after circuit reset is selected by setting a state of the BOOT5 interface, and the pin TXN1 and the pin TXN2 are not connected to any device; the common connection point of pins GND1-GND4 is grounded; the common connection point of the pins GND7-GND10 is grounded, and the test points TP5 and TP6 are set at the common connection point, and the pins GND5 and GND6 are left empty and can be set as required.

In this embodiment, the input end of the voltage detection module 40 is connected to the power input end and the input power usb_vbus respectively, the first output end of the voltage detection module 40 is connected to the ADC data acquisition module 50, and the second output end of the voltage detection module 40 is grounded for transmitting the acquired second voltage signal of the input power usb_vbus to the ADC data acquisition module 50.

Specifically, the voltage detection module 40 includes a first voltage dividing resistor Rd1 and a second voltage dividing resistor Rd2, the first end of the first voltage dividing resistor Rd1 is an input end of the voltage detection module 40, a common connection point between the second end of the first voltage dividing resistor Rd1 and the first end of the second voltage dividing resistor Rd2 is a first output end of the voltage detection module 40, the second end of the second voltage dividing resistor Rd2 is a second output end of the voltage detection module 40, and the voltage detection module 40 transmits the acquired divided voltage of the input power supply usb_vbus to the ADC data acquisition module 50 as a second voltage signal for voltage conversion.

The resistances of the first voltage dividing resistor Rd1 and the second voltage dividing resistor Rd2 are different, and the resistance of the first voltage dividing resistor Rd1 is far greater than that of the second voltage dividing resistor Rd2, for example, the resistance of the first voltage dividing resistor Rd1 is 20kΩ, and the resistance of the second voltage dividing resistor Rd2 is 2kΩ.

In some alternative implementations of the present embodiment, the interface input terminal 10 further includes a MICRO-USB interface input terminal, as shown in fig. 4, where the MICRO-USB interface input terminal includes an interface input chip CON2, and the interface input chip CON2 includes a power input terminal and a data receiving interface, and specifically, a pin VBUS is provided on the interface input chip CON2 as a power input terminal; the interface input chip CON2 is also provided with a pin D-and a pin D+ and the pin D-is a negative signal data receiving interface USB_DN and the pin D+ is a positive signal data receiving interface USB_DP.

The interface input chip CON2 is also provided with a grounding pin GND and pins SHELL1-SHELL4, the grounding pin GND is grounded, and the pins SHELL1-SHELL4 are also grounded, so that the running stability of the circuit is ensured.

In this embodiment, the TYPE-C interface input terminal and the MICRO-USB interface input terminal are connected in parallel, so as to support multi-interface connection and realize compatibility of the voltage and current detection circuit 1.

In this embodiment, referring to fig. 5, the current detection module 30 includes a first current detection chip U1 and a sampling resistor Rs, and a first power supply voltage pin VDD1, a first ground pin GND, a first positive current detection pin rs1+, a first negative current detection pin Rs1-, a first output pin OUT1, and a first off control pin SHDN1 are disposed on the first current detection chip U1.

The first power supply voltage pin VDD1 is connected to the working voltage VCC output by the DC-DC power module 20, the first ground pin GND is grounded, the first positive current detection pin RS1+ is connected to the first end of the sampling resistor RS, the first negative current detection pin RS 1-is connected to the second end of the sampling resistor RS, the first output pin OUT1 is connected to the ADC data acquisition module 50, and the first shutdown control pin SHDN1 is connected to the input power supply usb_vbus.

The first terminal of the sampling resistor Rs is connected to the input power source usb_vbus, and the second terminal of the sampling resistor Rs is connected to the interface output terminal 70 through the output power source vbus_out of the power line.

In this embodiment, the first voltage signal passing through the sampling resistor RS is collected through the first positive current detection pin RS1+ and the first negative current detection pin RS1 of the first current detection chip U1, the first voltage signal is proportionally converted into a voltage amplified signal in the first current detection chip U1, and the voltage amplified signal is transmitted to the voltage detection circuit 40 through the first output pin OUT 1.

The first voltage signal is converted according to a ratio, that is, the first voltage signal is amplified according to a ratio, so that the first voltage signal can be identified by the ADC data acquisition module 50. In this embodiment, a high-precision sampling resistor Rs is used, for example, the resistance of the sampling resistor Rs is 0.1 Ω, and the collected current can be calculated by collecting the first voltage signal and using ohm's law according to the first voltage signal. The method is simple, convenient, efficient and high in accuracy.

It should be noted that, the first off control pin SHDN1 corresponds to a switching signal, and when the switching signal is connected to a high level or a low level, the operation of the chip can be inhibited, so as to protect the circuit from being damaged.

In some alternative implementations of the present embodiment, the current detection module 30 further includes a fifth capacitor C5 and a sixth capacitor C6, where the fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, for filtering the interference signal of the current detection module 30, specifically, a common connection point of the first end of the fifth capacitor C5 and the first end of the sixth capacitor C6 is connected to the input power usb_vbus, and a common connection point of the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 is grounded.

In this embodiment, the capacitance of the fifth capacitor C5 is different from the capacitance of the sixth capacitor C6, for example, the capacitance of the fifth capacitor C5 is 4.7 μf, and the capacitance of the sixth capacitor C6 is 0.1 μf.

In some alternative implementations, the current detection module 30 further includes a second current detection chip U2, where the second current detection chip U2 is provided with a second supply voltage pin VDD2, a second ground pin GND, a second positive current detection pin rs2+, a second negative current detection pin RS2-, a second output pin OUT2, and a second shutdown control pin SHDN2.

The second supply voltage pin VDD2 is connected to the DC-DC power supply module 20, the second ground pin GND is grounded, the second positive current detection pin RS2+ is connected to the second end of the sampling resistor RS, the first negative current detection pin RS 2-is connected to the first end of the sampling resistor RS, the second output pin OUT2 is connected to the ADC data acquisition module 50, and the second shutdown control pin SHDN2 is connected to the input power supply usb_vbus.

In this embodiment, the first current detection chip U1 and the second current detection chip U2 are connected with the sampling resistor RS in opposite directions through the first positive current detection pin RS1+, the first negative current detection pin RS 1-and the second positive current detection pin RS2+, and the second negative current detection pin RS2 of the voltage acquisition interface, so that the adapter can be connected from any end of the Type-C port to realize current monitoring, i.e., the adapter can be connected from the interface input end 10 (i.e., forward connection) or from the interface output end 70 (i.e., reverse connection).

Specifically, when the adapter is accessed from the interface input end 10, the first positive current detection pin RS1+ and the first negative current detection pin RS 1-of the first current detection chip U1 are used as a voltage acquisition interface to acquire the voltage of the sampling resistor Rs; when the adapter is accessed from the interface output end 70, the second positive current detection pin RS2+ and the second negative current detection pin RS 2-of the second current detection chip U2 are used as a voltage acquisition interface to acquire the voltage of the sampling resistor Rs.

It should be noted that, in order to avoid that when the adapter performs the forward connection and the reverse connection simultaneously, the collected first voltage signal is converted and transmitted to the ADC data collecting module 50, so that the ADC data collecting module 50 is difficult to distinguish, the second output pin OUT2 may be directly connected to the wireless communication module 60, and the voltage amplified signal obtained by the reverse connection is directly transmitted to the wireless communication module 60, and is subjected to analog-to-digital conversion by the wireless communication module 60, so that the efficiency and accuracy of signal processing are improved.

In this embodiment, the current detection module 30 further includes a seventh capacitor C7 and an eighth capacitor C8, where the seventh capacitor C7 and the eighth capacitor C8 are connected in parallel, and are configured to filter out an interference signal at the end of the second current detection chip U2, specifically, a common connection point between the first end of the seventh capacitor C7 and the first end of the eighth capacitor C8 is connected to the input power usb_vbus, and a common connection point between the second end of the seventh capacitor C7 and the second end of the eighth capacitor C8 is grounded.

It should be understood that the capacitance of the seventh capacitor C7 and the eighth capacitor C8 are different, for example, the capacitance of the seventh capacitor C7 is 4.7 μf and the capacitance of the eighth capacitor C8 is 0.1 μf.

In some alternative implementations of the present embodiment, referring to fig. 6, the ADC data acquisition module 50 includes an ADC data acquisition chip U3, and a third ground pin GND, an analog voltage pin AVDD, a reference voltage pin REF, a voltage signal input pin AIN0P, a current input signal pin AIN1P, a channel selection pin CHSEL, a pull-down enable pin PDEN, an output serial interface SPI1, and a digital voltage pin DVDD are disposed on the ADC data acquisition chip U3.

The third grounding pin is grounded to GND; the analog voltage pin AVDD, the reference voltage pin REF and the digital voltage pin DVDD are connected to the voltage output VCC of the DC-DC power supply module 20; the reference voltage pin REF is connected to the voltage output VCC of the DC-DC power module 20; the voltage signal input pin AIN0P is connected with the voltage detection module 40; the current input signal pin AIN1P is connected with the current detection module 30; the channel select pin CHSEL and the pull-down enable pin PDEN are connected to the wireless communication module 60; the output serial interface SPI1 is connected to the wireless communication module 60 for transmitting digital signals to the wireless communication module 60.

Specifically, the voltage signal input pin AIN0P is connected to a common connection point between the second end of the first voltage dividing resistor Rd1 and the first end of the second voltage dividing resistor Rd2 in the voltage detection module 40 through the VACD1 network, and receives the second voltage signal of the input power supply usb_vbus collected by the voltage dividing resistor for detection. The current input signal pin AIN1P is connected with a first output pin OUT1 of a first current detection chip U1 through a VACD2 network, is connected with a second output pin OUT2 of a second current detection chip U2 through a VACD3 network, and is used for receiving the voltage amplified signal obtained after the internal processing, analysis and scaling of the first current detection chip U1 or the second current detection chip U2.

The output serial interface SPI1 includes an SDO interface, an SCLK interface, and a CS interface, and corresponds to the SPI1_miso network, the SPI1_sck network, and the SPI1_nss network, respectively, and is connected to a network corresponding to the wireless communication module 60 through the foregoing networks, and is configured to transmit a digital signal obtained by performing analog-to-digital conversion on the second voltage signal and the voltage amplified signal to the wireless communication module 60 through the SPI1_miso network, the SPI1_sck network, and the SPI1_nss network.

The channel select pin CHSEL is connected to the corresponding network of the wireless communication module 60 through a pa6_chsel network, and the pull-down enable pin PDEN is connected to the corresponding network of the wireless communication module 60 through a pa7_pden network. The channel selection pin CHSEL is used for selecting whether an input channel of the ADC data acquisition chip U3 is a voltage signal input pin AIN0P or a current input signal pin AIN1P, and is used for distinguishing a second voltage signal and a voltage amplification signal, so that the accuracy of signal processing can be improved; the pull-down enable pin PDEN is used to pull the pull-down enable pin PDEN low when the external circuit is low.

The reference voltage pin REF is used for collecting the working voltage provided by the DC-DC power module 20 as a reference voltage, comparing the reference voltage with the actual collected voltage, and adjusting the actual voltage according to the comparison result.

In this embodiment, an AIN0N pin, an AIN1N pin, a refnd pin, an NC1 pin, and an NC2 pin are further disposed on the ADC data acquisition chip U3, where a common connection point of the AIN0N pin and the AIN1N pin is grounded, the refnd pin is grounded, and a common connection point of the NC1 pin and the NC2 pin is grounded.

In this embodiment, the ADC data acquisition module 50 further includes a capacitor C9, a capacitor C10, and a capacitor C11, where the capacitor C9 and the capacitor C10 are connected in parallel, and are used for filtering out an interference signal in the working voltage input to the ADC data acquisition module 50, specifically, a first end of the capacitor C9 is connected to the digital voltage pin DVDD, and a second end of the capacitor C9 is grounded; the first end of the capacitor C10 is connected to the digital voltage pin DVDD, and the second end of the capacitor C10 is grounded; the capacitor C11 is configured to filter out an interference signal in the voltage of the input reference voltage pin REF, a first end of the capacitor C11 is connected to the working voltage output by the DC-DC power module 20, and a second end of the capacitor C11 is grounded.

In this embodiment, the ADC data acquisition module 50 is further configured with a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, and a resistor R8, where a first end of the resistor R1 is connected to a common connection point of a second end of the first voltage dividing resistor Rd1 and a first end of the second voltage dividing resistor Rd2 through a VADC1 network, and a second end of the resistor R1 is connected to a voltage signal input pin AIN0P; the first end of the resistor R2 is grounded, and the second end of the resistor R2 is connected with an AIN0N pin; the first end of the resistor R3 is grounded, and the second end of the resistor R3 is connected with an AIN1N pin; the first end of the resistor R4 is connected with a first output pin OUT1 of the first current detection chip U1 through a VACD2 network, and the second end of the resistor R4 is connected with a current input signal pin AIN1P; the first end of the resistor R5 is connected with the second output pin OUT2 of the second current detection chip U2 through a VACD3 network, and the second end of the resistor R5 is connected with the current input signal pin AIN1P; the first end of the resistor R6 is connected with the SDO interface, and the second end of the resistor R6 is connected with the interface corresponding to the wireless communication module 60 through the SPI1_MISO network; the first end of the resistor R7 is connected with an SCLK interface, and the second end of the resistor R7 is connected with an interface corresponding to the wireless communication module 60 through an SPI1_SCK network; the first end of the resistor R8 is connected to the CS interface, and the second end of the resistor R8 is connected to the interface corresponding to the wireless communication module 60 through the SPI1_nss network.

In this embodiment, the ADC data acquisition module 50 is further provided with a capacitor C12 and a capacitor C13, which are used for filtering the interference signals generated by the circuit. The first end of the capacitor C12 is connected between the second end of the resistor R1 and the voltage signal input pin AIN0P, and the second end of the capacitor C12 is connected between the second end of the resistor R2 and the AIN0N pin; the first end of the capacitor C13 is connected between the second end of the resistor R3 and the AIN1N pin, and the second end of the capacitor C13 is connected between the second end of the resistor R4 and the current input signal pin AIN 1P.

In some alternative implementations of the present embodiment, referring to fig. 7, the wireless communication module 60 includes a wireless communication chip U5, where the wireless communication chip U5 is provided with a reset pin RST, an enable pin EN, a third power supply voltage pin VCC1, an input serial interface SPI2, a first general purpose input and output pin GPIO1, a second general purpose input and output pin GPIO2, and an indicator light control pin GPIO3. The wireless communication module 60 may be a WiFi communication module, and is connected to the display device through a WiFi signal.

The reset pin RST is connected with the reset circuit 61; the enable pin EN and the third supply voltage pin VCC1 are connected to the voltage output terminal VCC of the DC-DC power supply module 20; the input serial interface SPI2 is connected with the output serial interface SPI 1; the first general input and output pin GPIO1 is connected with the pull-down enabling pin PDEN; a second general input and output pin GPIO2 is connected to the channel selection pin CHSEL; the indicator lamp control pin GPIO3 is connected to the indicator lamp circuit 62 for controlling the on or off of the indicator lamp.

The input serial interface SPI2 comprises a MISO interface, an SCLK interface and a CS0 interface, wherein the MISO interface is connected with the SDO interface of the output serial interface SPI1 through an SPI1_MISO network, the SCLK interface is connected with the SCLK interface of the output serial interface SPI1 through an SPI1_SCK network, and the CS0 interface is connected with the CS interface of the output serial interface SPI1 through an SPI1_NSS network.

In the present embodiment, referring to fig. 8, the indicator lamp circuit 62 includes a first resistor R9, a second resistor R10, a switching tube Q1, and an indicator lamp, wherein:

the common connection point of the first end of the first resistor R9 and the first end of the second resistor R10 is connected with the voltage output end VCC of the DC-DC power supply module 20, and the second end of the first resistor R9 is respectively connected with the indicator lamp control pin GPIO3 and the grid G of the switching tube Q1; the second end of the second resistor R10 is connected with the drain electrode D of the switching tube Q1; the source electrode S of the switching tube Q1 is connected to an indicator lamp.

In this embodiment, the indicator lamps are LED indicator lamps D11, and the anodes of the LED indicator lamps D11 are connected to the sources S, D11 of the switching tube Q1 and the cathodes thereof are grounded.

In this embodiment, the reset circuit 61 includes a resistor R11 and a switch SW3, a first end of the resistor R11 is connected to the reset pin RST, a second end of the resistor R11 is connected to the normally open contact 2 of the switch SW3, and the normally closed contact 1 of the switch SW3 is grounded. The reset circuit 61 is used for providing a reset signal when the circuit is powered up until the circuit power supply is stable, and the reset signal is withdrawn, so that the anti-interference capability can be improved.

In this embodiment, the wireless communication chip U5 is further provided with a pin ADC, and is connected to the second output pin OUT2 of the second current detection chip U2 through the VADC3 network, and when the current analog signal output by the second current detection chip U2 cannot be transmitted to the ADC data acquisition chip U3 for processing through the current input signal pin AIN1P, the current analog signal can be transmitted to the pin ADC and processed by the wireless communication chip U5.

In this embodiment, the wireless communication chip U5 is further provided with a pin MOSI, a ground pin GND, a pin GPIO4, and a pin GPIO5, and the wireless communication module 60 further includes a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, and a resistor R24, where the pin MOSI is specifically connected to the test point TP7; the grounding pin GND is grounded; the first end of the resistor R12 is connected with the pin ADC, and the second end of the resistor R12 is connected with the second output pin OUT2 of the second current detection chip U2 through a VADC3 network; the common connection point of the first end of the resistor R13 and the first end of the resistor R14 is connected with the voltage output end VCC, the second end of the resistor R13 is connected with the second general input and output pin GPIO2, and the second end of the resistor R14 is connected with the first general input and output pin GPIO1; the first end of the resistor R15 is connected with the pin GPIO4, and the second end of the resistor R15 is a test point TP8; the first end of the resistor R16 is connected with the pin GPIO5, and the second end of the resistor R16 is a test point TP9; a first terminal of the resistor R24 is connected to the enable pin EN, and a second terminal of the resistor R24 is connected to the voltage output terminal VCC of the DC-DC power module 20.

In this embodiment, the wireless communication module 60 further includes a capacitor C14 and a capacitor C15, where the capacitor C14 and the capacitor C15 are connected in parallel, and are used for filtering out an interference signal of the working voltage input to the wireless communication chip U5; specifically, a first end of the capacitor C14 is connected to the voltage output end VCC of the DC-DC power module 20 and the third supply voltage pin VCC1, respectively, a first end of the capacitor C15 is connected to the voltage output end VCC of the DC-DC power module 20 and the third supply voltage pin VCC1, respectively, and a common connection point between a second end of the capacitor C14 and a second end of the capacitor C15 is grounded.

In some alternative implementations, referring to fig. 9, the DC-DC power module 20 includes a power chip U2, a charging unit 21, an overload short-circuit protection unit 22, a voltage division unit 23, and a collection unit 24.

The power chip U2 is connected to the input power USB_VBUS through an input end IN thereof, and performs voltage conversion on the input power USB_VBUS; the first terminal of the charging unit 21 is connected to the input power usb_vbus and the input terminal IN of the power chip U2, respectively, the second terminal of the charging unit 21 is connected to the enable terminal EN of the power chip U2, and the third terminal of the charging unit 21 is grounded.

The first input end of the overload short-circuit protection unit 22 is connected with the voltage bootstrap end BST of the power chip U2, the second input end of the overload short-circuit protection unit 22 is connected with the switch end SW of the power chip U2, and the output end of the overload short-circuit protection unit 22 is connected with the current detection module 30, the ADC data acquisition module 50 and the wireless communication module 60.

The input end of the voltage division unit 23 is connected with the feedback end FB of the power supply chip U2, and the output end of the voltage division unit 23 is commonly connected with the output end of the overload short-circuit protection unit 22.

The first input end of the acquisition unit 24 is connected with the voltage acquisition end VCC2 of the power chip U2, the second input end of the acquisition unit 24 is connected with the load switching end AAM of the power chip U2, and the output end of the acquisition unit 24 is grounded.

The power supply chip U2 is a DC-DC converter, which converts an input voltage and effectively outputs a fixed voltage, and is connected to a direct current through an input terminal IN thereof and performs voltage conversion on the direct current.

It should be noted that, the power chip U2 is a DC-DC input from 4.5V to 24V, and may output 3.3V to provide an operating voltage for all chips.

In this embodiment, the charging unit 21 includes a capacitor C16, a capacitor C17, and a resistor R17, where a first end of the capacitor C16 and a first end of the capacitor C17 are a first end of the charging unit 21, and a second end of the capacitor C16 and a second end of the capacitor C17 are a third end of the charging unit 21; the first terminal of the resistor R17 is connected to the first terminal of the capacitor C17, and the second terminal of the resistor R17 is the second terminal of the charging unit 21.

The input power usb_vbus outputs an enable signal to the enable terminal EN through the charging unit 21 to drive the power chip U2 to operate. Specifically, the input power supply usb_vbus is connected to the charging unit 21, after being electrified, charges the capacitor C17, the charging voltage of the capacitor C17 reaches a preset threshold, after the voltage is divided by the resistor R17, the voltage output by the charging unit 21 is greater than or equal to the starting threshold of the enable end EN of the power chip U2, and the voltage output by the charging unit 21 is used as an enable signal to drive the power chip U2 to work; when the charging voltage of the capacitor C17 does not reach the preset threshold, after the voltage is divided by the resistor R7, the voltage output by the charging unit 21 is smaller than the start threshold of the enable end EN of the power chip U2, and the power chip U2 is in a shutdown state and cannot work.

The overload short-circuit protection unit 22 comprises a resistor R18, a capacitor C18 and an inductor L1, wherein a first end of the resistor R18 is a first input end of the overload short-circuit protection unit 22, and a second end of the resistor R18 is connected with the first end of the capacitor C18; the common connection point of the second end of the capacitor C18 and the first end of the inductor L1 is the second input end of the overload short-circuit protection unit 22; the second end of the inductor L1 is an output end of the overload short-circuit protection unit 22, and is also a voltage output end VCC of the DC-DC power module 20, where the voltage output end VCC provides an operating voltage for the current detection module 30, the ADC data acquisition module 50 and the wireless communication module 60.

In this embodiment, the overload short-circuit protection unit 22 is configured to detect an operating current of the power chip U2, control the operating current within a preset current range, perform overload protection or short-circuit protection on the power chip U2, and maintain stability of an output voltage through the inductor L1 and the capacitor C18.

The voltage dividing unit 23 comprises a resistor R19, a resistor R20, a resistor R21 and a capacitor C19, wherein the first end of the resistor R19 is an input end of the voltage dividing unit 23, and the second end of the resistor R19 is connected with the first end of the resistor R20; the common connection point of the second end of the resistor R20 and the first end of the capacitor C19 is an output end of the voltage dividing unit 23, and the output end of the voltage dividing unit 23 is connected to the voltage output end VCC; the second end of the capacitor C19 is grounded; the first end of the resistor R21 is connected between the second end of the resistor R19 and the first end of the resistor R20, and the second end of the resistor R21 is grounded.

The collecting unit 24 includes a capacitor C20, a resistor R22, and a resistor R23, where a common connection point of the first end of the capacitor C20 and the first end of the resistor R22 is a first input end of the collecting unit 24; the second end of the capacitor C20 is grounded; the common connection point of the second end of the resistor R22 and the first end of the resistor R23 is the second input end of the acquisition unit 24; the second terminal of resistor R23 is grounded.

The voltage collection terminal VCC2 collects the voltage of the input power UBS_VBUS, the voltage is divided by the resistor R22 and the resistor R23, the voltage is transmitted to the load switching terminal AAM, the load switching terminal AAM performs light-heavy load switching according to the received voltage, and when the load is light, the current output is reduced, and the current loss is avoided.

In the present embodiment, referring to fig. 10, the interface output terminal 70 includes an interface output chip CON3 and a second filter circuit 71.

The interface output chip CON3 includes a power output end, a data output interface and a second communication interface, the power output end is connected with the current detection module 30 and the first end of the second filter circuit 71 through the output power vbus_out, and the data output interface and the communication output interface of the interface output chip CON3 are connected with the interface input end 10; the second end of the second filter circuit 71 is grounded for filtering the interference signal in the circuit.

Specifically, the interface output chip CON3 is provided with a pin VBUS1, a pin VBUS2, a pin VBUS3 and a pin VBUS4, and a common connection point of the pin VBUS1, the pin VBUS2, the pin VBUS3 and the pin VBUS4 is a power output end; the data output interface comprises a positive signal data output interface USB_DP and a negative signal data output interface USB_DN, wherein the positive signal data output interface USB_DP is connected with a positive signal data receiving interface USB_DP of the interface input chip CON1, and the negative signal data output interface USB_DN is connected with a negative signal data receiving interface USB_DN of the interface input chip CON 1. The interface output chip CON3 is provided with a pin A_D+, a pin A_D-, a pin B_D+ and a pin B_D-, wherein the common connection point of the pin A_D+ and the pin B_D+ is a positive signal data output interface USB_DP, and the common connection point of the pin A_D-and the pin B_D-is a negative signal data output interface USB_DN;

the second communication interface comprises a second communication transmitting interface UART_TX and a second communication receiving interface UART_RX, an interface output chip CON3 is provided with an RXP1 pin, an RXN1 pin, an RXP2 pin and an RXN2 pin, the common connection point of the RXP1 pin and the RXP2 pin is the second communication transmitting interface UART_TX, and the common connection point of the RXN1 pin and the RXN2 pin is the second communication receiving interface UART_RX. The second communication transmitting interface uart_tx is connected with the first communication receiving interface uart_rx of the interface input chip CON1, and the second communication receiving interface uart_rx is connected with the first communication transmitting interface uart_tx of the interface input chip CON 1.

In this embodiment, the interface output chip CON3 is further provided with a second channel configuration interface, where the second channel configuration interface is a pin CC1 and a pin CC2, and connects the pin CC1 and the pin CC2 of the interface input chip CON1 correspondingly.

In this embodiment, the interface output chip CON3 is further provided with a pin TXP1, a pin TXN1, a pin TXP2, a pin TXN2, and pins GND1-GND10, where a common connection point between the pin TXP1 and the pin TXP2 is a BOOT5 interface, the BOOT5 interface is connected to the BOOT5 interface of the interface input chip CON1, a start mode after circuit reset is selected by setting a state of the BOOT5 interface, and the pin TXN1 and the pin TXN2 are not connected to any device; the common connection point of the pins GND1-GND4 is grounded, the common connection point of the pins GND7-GND10 is grounded, and the pins GND5 and GND6 are empty and can be set as required.

In this embodiment, a first end of the second filter circuit 71 is connected to the power output end and the output power vbus_out, respectively, and a second end of the second filter circuit 71 is grounded for filtering the interference signal in the output power vbus_out.

Specifically, the second filter circuit 71 includes a capacitor C20, a capacitor C21, a capacitor C22, and a capacitor C23, where a common connection point of the first end of the capacitor C20, the first end of the capacitor C21, the first end of the capacitor C22, and the first end of the capacitor C23 is the first end of the second filter circuit 61; the common connection point of the second end of the capacitor C20, the second end of the capacitor C21, the second end of the capacitor C22, and the second end of the capacitor C23 is the second end of the second filter circuit 71.

The capacitance values of the capacitor C20, the capacitor C21, the capacitor C22 and the capacitor C23 may be the same or different, for example, the capacitance values of the capacitor C20 and the capacitor C21 may be 1 μf, and the capacitance values of the capacitor C22 and the capacitor C23 may be 10 μf.

Based on the above voltage-current detection circuit, the embodiment of the present application further provides a voltage-current detection apparatus, which includes the voltage-current detection circuit 1, the adapter 2, the display device 3, and the back-end device 4 as described above.

The adapter 2 is connected to the interface input end 10 through a TYPE-C interface and is used for providing starting voltage for the voltage and current detection circuit 1; the display device 3 is connected with the wireless communication module 60 through a wireless signal, and is used for displaying the collected voltage and current of the input power supply USB_VBUS after digital-to-analog conversion of the received digital signal; the back-end device 4 is connected to the interface output 70 via a power data input interface for receiving communication data.

In the present embodiment, the display device 3 may be a computer, an intelligent terminal, or the like; the back-end device 4 is an electrical device, such as a sound box device.

The voltage and current detection device of the embodiment of the application can be directly connected in series on an existing power adapter Type-C interface, the use is convenient, the other end is directly connected into rear-end equipment, after the rear-end equipment is electrified, the voltage and current detection device can monitor current and voltage data in real time and transmit the data to display equipment in real time, whether the rear-end equipment works normally can be judged according to the displayed voltage and current data, and once the current or voltage exceeds a standard range of judgment, a red FAIL warning can be given to an LED indicator lamp, namely, the LED indicator lamp emits red light, otherwise, green PASS is displayed, namely, the LED indicator lamp displays green light. The circuit has the advantages of simple design, low cost and simple implementation, and can bring benefits and convenience to enterprises and greatly reduce the cost.

The voltage and current detection device can be applied to all testing links of electronic products, including research and development and production links.

It is apparent that the embodiments described above are only some embodiments of the present application, but not all embodiments, the preferred embodiments of the present application are given in the drawings, but not limiting the patent scope of the present application. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a more thorough understanding of the present disclosure. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing, or equivalents may be substituted for elements thereof. All equivalent structures made by the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the protection scope of the application.

Claims

1. A voltage-current detection circuit, comprising:

2. The voltage-current detection circuit of claim 1, wherein the interface input comprises an interface input chip, a first filter circuit, and an electrostatic protection circuit;

3. The voltage-current detection circuit of claim 1, wherein the current detection module comprises a first current detection chip and a sampling resistor, the first current detection chip having a first supply voltage pin, a first ground pin, a first positive current detection pin, a first negative current detection pin, a first output pin, and a first off control pin disposed thereon;

4. The voltage-current detection circuit of claim 3, wherein the current detection module further comprises a second current detection chip having a second supply voltage pin, a second ground pin, a second positive current detection pin, a second negative current detection pin, a second output pin, and a second off control pin disposed thereon;

5. The voltage-current detection circuit of claim 1, wherein the ADC data acquisition module comprises a voltage detection chip having a third ground pin, an analog voltage pin, a reference voltage pin, a voltage signal input pin, a current input signal pin, a channel select pin, a pull-down enable pin, an output serial interface, and a digital voltage pin disposed thereon;

6. The voltage-current detection circuit of claim 5, wherein the wireless communication module comprises a wireless communication chip provided with a reset pin, an enable pin, a third supply voltage pin, an input serial interface, a first universal input and output pin, a second universal input and output pin, and an indicator light control pin;

7. The voltage-current detection circuit of claim 6, wherein the indicator light circuit comprises a first resistor, a second resistor, a switching tube, and an indicator light, wherein:

the source electrode of the switch tube is connected with the indicator lamp.

8. The voltage-current detection circuit of any one of claims 1 to 7, wherein the DC-DC power module comprises a power supply chip, a charging unit, an overload short-circuit protection unit, a voltage division unit, and a collection unit, wherein:

9. The voltage-current detection circuit of claim 8, wherein the interface output comprises an interface output chip and a second filter circuit;

10. A voltage-current detecting apparatus comprising an adapter, a display device, a back-end device, and the voltage-current detecting circuit according to any one of claims 1 to 9;