CN212541917U - SSD test carrier plate and SSD test system - Google Patents
SSD test carrier plate and SSD test system Download PDFInfo
- Publication number
- CN212541917U CN212541917U CN202021180666.7U CN202021180666U CN212541917U CN 212541917 U CN212541917 U CN 212541917U CN 202021180666 U CN202021180666 U CN 202021180666U CN 212541917 U CN212541917 U CN 212541917U
- Authority
- CN
- China
- Prior art keywords
- ssd
- capacitor
- interface
- power
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
The utility model discloses a SSD test support plate, which comprises a base plate, a power interface, a SSD interface and a communication interface, wherein the SSD interface and the power interface are arranged on the front surface of the base plate, and the communication interface is arranged on the back surface of the base plate; the SSD interface is used for connecting an SSD, the power supply interface is electrically connected with the SSD interface, the communication interface is electrically connected with the SSD interface, and the communication interface is used for connecting a test host to transmit a test signal. The utility model discloses a SSD tests support plate passes through communication interface and is connected with test host, can receive its test signal and carry out corresponding functional test to SSD, can realize SSD's multinomial functional test to efficiency of software testing is high. Furthermore, the utility model discloses still disclose a SSD test system.
Description
Technical Field
The utility model relates to a solid state disk tests technical field, in particular to SSD tests support plate and SSD test system.
Background
With the rapid development of the internet, the storage demand of people on data information is also continuously promoted, and an SSD (Solid State drive) is widely used in many fields such as vehicle-mounted, industrial control, video monitoring, network monitoring and the like as a carrier for storing data information due to its characteristics of high storage speed, low power consumption and the like.
Currently, in the production process of the SSD, a plurality of tests such as a first card opening test, an RDT bad block test, a BIT built-in self test, and a second card opening test are required to verify the functional integrity thereof. However, each function test of the SSD is configured with a corresponding test carrier, that is, when a certain function of the SSD is tested, the test carrier is connected to the corresponding test carrier, so that the test carrier can only implement a single function test of the SSD, and the test function is single; in addition, when testing different functions of the SSD, different test carrier boards need to be switched to perform testing, which is troublesome to operate and low in testing efficiency.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a SSD tests support plate to solve the problem that test support plate test function singleness and efficiency of software testing are low that is used for the SSD to test at present.
Specifically, the utility model provides a SSD test support plate, this SSD test support plate includes base plate, power source, SSD interface and communication interface, SSD interface and power source set up in the front of base plate, communication interface sets up in the back of base plate;
the SSD interface is used for connecting an SSD, the power supply interface is electrically connected with the SSD interface, the communication interface is electrically connected with the SSD interface, and the communication interface is used for connecting a test host to transmit a test signal.
Preferably, the SSD test carrier plate further includes a power interface circuit, a voltage conversion circuit, and an SSD interface circuit, which are disposed on the substrate and connected in sequence, where the power interface circuit includes a first output terminal, a first capacitor, a second capacitor, a power ground terminal, a first power input terminal, and a second power input terminal;
the first power supply input end and the second power supply input end are respectively connected with the power supply interface;
the first capacitor and the second capacitor are connected in parallel between the first power supply input end and the second power supply input end;
the first output end is connected with the first power supply input end;
the power ground terminal is connected to the second power input terminal.
Preferably, the voltage conversion circuit includes a second input terminal, a filtering module, a voltage conversion chip, a voltage stabilizing module and a second output terminal;
the first end of the filtering module is connected with the second input end, and the second end of the filtering module is connected with the first end of the voltage conversion chip;
the second end of the voltage conversion chip is connected with the first end of the voltage stabilizing module, and the second end of the voltage stabilizing module is connected with the second output end;
the second input end is connected with the first output end, and the second output end is connected with the SSD interface circuit.
Preferably, the filter module comprises a third capacitor, a fourth capacitor and a fifth capacitor;
first ends of the third capacitor, the fourth capacitor and the fifth capacitor are respectively connected with the second input end, and second ends of the third capacitor, the fourth capacitor and the fifth capacitor are respectively grounded.
Preferably, the voltage stabilizing module comprises a sixth capacitor, a voltage stabilizing diode, an inductor, a seventh capacitor, a first resistor, a second resistor, an eighth capacitor, a ninth capacitor and a tenth capacitor;
the first end of the sixth capacitor is connected with the voltage conversion chip, the second end of the sixth capacitor is connected with the first end of the voltage stabilizing diode, and the second end of the voltage stabilizing diode is grounded;
the first end of the inductor is connected with the voltage conversion chip, and the second end of the inductor is connected with the second output end;
the first ends of the seventh capacitor, the first resistor and the second resistor are connected with each other and are all connected with the voltage conversion chip, the second end of the seventh capacitor, the second end of the first resistor and the second end of the inductor are connected with each other and are all connected with the second output end, and the second end of the second resistor is grounded;
the first end of the eighth capacitor is connected with the second output end, and the second end of the eighth capacitor is grounded;
the first end of the ninth capacitor is connected to the second output end, the second end of the ninth capacitor is grounded, the first end of the tenth capacitor is connected to the first end of the ninth capacitor, and the second end of the tenth capacitor is connected to the second end of the ninth capacitor.
Preferably, the SSD interface circuit includes a third input terminal, a third resistor, a fourth resistor, a first diode LED, a second diode LED;
first ends of the third resistor and the fourth resistor are connected with each other and connected with a V5 pin and a third input end of the SSD interface;
a second end of the third resistor is connected with a first end of the first diode LED, a second end of the first diode LED is connected with a GND pin of the SSD interface and is grounded, a second end of the fourth resistor is connected with a first end of the second diode LED, and a second end of the second diode LED is connected with an RSV pin of the SSD interface;
wherein the third input terminal is connected to the second output terminal.
Preferably, the SSD interface and the communication interface include an rxp pin, an rxn pin, a txn pin, and a txp pin for forming a connection.
Preferably, the number of the communication interfaces is several;
the SSD interfaces form SSD interface groups, and each SSD interface group corresponds to one communication interface.
Preferably, the SSD test carrier board further comprises a plurality of switches;
the number of the power interfaces is several;
the switch is respectively connected with the power supply interface and the plurality of SSD interface groups.
The utility model discloses still disclose a SSD test system, this SSD test system includes the SSD test support plate of aforementioned record, and this SSD test support plate includes base plate, power source, SSD interface and communication interface, SSD interface and power source set up in the front of base plate, communication interface sets up in the back of base plate;
the SSD interface is used for connecting an SSD, the power supply interface is electrically connected with the SSD interface, the communication interface is electrically connected with the SSD interface, and the communication interface is used for connecting a test host to transmit a test signal.
Compared with the prior art, the technical scheme of the embodiment of the application has the beneficial effects that: the SSD test carrier plate is externally connected with a power supply through a power supply interface to be electrified, is connected with a test host through a communication interface to receive a test signal, and performs function test on an SSD connected with the SSD test carrier plate through an SSD interface; the SSD test carrier plate can receive different test signals to test different functions of the SSD, so that multiple function tests of the SSD are realized, the SSD test carrier plate can realize multiple tests on one plate, the test carrier plate does not need to be switched in the process of performing multiple function tests on the SSD, the phenomenon that a disk is pulled out and inserted for multiple times is avoided, the operation is simple, and the test efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of an SSD test carrier according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of the SSD test carrier of fig. 1 from another view angle;
fig. 3 is a circuit diagram of a power interface circuit of the SSD test carrier of fig. 1;
fig. 4 is a circuit diagram of a switch circuit of the SSD test carrier of fig. 1;
fig. 5 is a circuit diagram of a voltage converting circuit of the SSD test carrier of fig. 1;
fig. 6 is a circuit diagram of an SSD interface circuit of the SSD test carrier of fig. 1;
fig. 7 is a circuit diagram of a communication interface circuit of the SSD test carrier of fig. 1.
Detailed Description
In the following, the embodiments of the present invention will be described in detail with reference to the accompanying drawings, and obviously, the described embodiments are only some embodiments, not all embodiments, of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The utility model provides a SSD tests support plate, refer to fig. 1 and fig. 2, this SSD tests support plate includes base plate 100, power source, SSD interface 110 and communication interface 120, SSD interface 110 and power source set up in the front of base plate 100, communication interface 120 sets up in the back of base plate 100;
the SSD interface 110 is configured to connect to the SSD, the power interface is electrically connected to the SSD interface 110, the communication interface 120 is electrically connected to the SSD interface 110, and the communication interface 120 is configured to connect to the test host to implement data interaction, for example, the test host transmits a test signal to the SSD through the communication interface 120, and the SSD sends a test result to the test host through the communication interface 120 after the test is completed.
The SSD test carrier plate according to this embodiment is used as a test tool for SSD function test, and can implement a unified test of multiple functions of the SSD, such as a primary card opening test, an RDT bad block test, a BIT built-in self test, a secondary card opening test, and the like.
The substrate 100 of the SSD test carrier has a front surface and a back surface, wherein the front surface is provided with an SSD interface 110 and a power interface, and the back surface is provided with a communication interface 120; the communication interface 120 is connected to the test host through a data line, the SSD interface 110 is used for placing an SSD, and the power interface is used for connecting to a power supply to obtain a working power supply required by the entire SSD test carrier from the power supply. It should be noted that the SSD interface 110 may be a sata (serial ata) interface, and the mentioned test host may be a computer, or may be other terminals, including but not limited to this, and those skilled in the art can select the interface according to the actual situation.
Specifically, during testing, the test host receives the test command and issues a test signal corresponding to the function to be tested of the SSD, and the SSD test carrier receives the test signal through the communication interface 120 of the SSD test carrier, so as to perform a function test on the SSD placed on the SSD interface 110.
Therefore, it is easy to understand that the test host can issue test signals with different functions, and the SSD test carrier 100 performs tests with different functions on the SSD according to the test signals with different functions, so as to implement multiple function tests of the SSD, that is, the SSD test carrier 100 can implement multiple tests with one board, and the test carrier does not need to be switched during the process of performing multiple function tests on the SSD, thereby avoiding pulling out the plug tray for multiple times, which is simple to operate and improves the test efficiency.
In a preferred embodiment, referring to fig. 3 to 6, the SSD test carrier further includes a power interface circuit, a voltage converting circuit and an SSD interface circuit disposed on the substrate 100 and connected in sequence, wherein the power interface circuit includes a first output terminal, a first capacitor C1, a second capacitor C2, a power ground terminal, a first power input terminal and a second power input terminal;
the first power supply input end and the second power supply input end are respectively connected with the power supply interface;
a first capacitor C1 and a second capacitor C2 are connected in parallel between the first power input terminal and the second power input terminal;
the first output end is connected with the first power supply input end;
the power ground terminal is connected to the second power input terminal.
The first power supply input end and the second power supply input end are connected with a power supply, and the first output end is connected with the voltage conversion circuit.
The power interface circuit according to the embodiment is used for receiving the power voltage of the power supply to realize the power-on test of the SSD. Specifically, referring to fig. 3, the first power input terminal and the second power input terminal are respectively corresponding to an anode and a cathode of the power interface, in practical application, the power supply is connected to the entire SSD test carrier plate through the power interface, and the power supply voltage is input from the first power input terminal and the second power input terminal, and after filtering and voltage stabilization are performed through the first capacitor C1 and the second capacitor C2 which are arranged in parallel, the power supply voltage is output from the first output terminal, and in addition, the second power input terminal (which is connected to the cathode of the power supply) is grounded for electrical protection. The input power supply voltage is 12V, and the first capacitor C1 and the second capacitor C2 can adopt 100uF/10V capacitors. In addition, the voltage conversion circuit is used for performing voltage conversion, the SSD interface circuit is used for receiving the voltage to perform the power-on test of the SSD, and the specific circuit design is described in detail in the following embodiments, which is not described herein.
Further, referring to fig. 5, the voltage conversion circuit includes a second input terminal, a filtering module 10, a voltage conversion chip 20, a voltage stabilizing module 30, and a second output terminal;
the first end of the filter module 10 is connected to the second input end, and the second end of the filter module 10 is connected to the first end of the voltage conversion chip 20;
the second end of the voltage conversion chip 20 is connected to the first end of the voltage stabilization module 30, and the second end of the voltage stabilization module 30 is connected to the second output end;
the second input end is connected with the first output end, and the second output end is connected with the SSD interface circuit.
The voltage conversion circuit related to the embodiment is used for realizing the voltage conversion from the power supply voltage to the working voltage so as to realize the normal test of the SSD test carrier plate on the SSD carrier plate. Specifically, the second input terminal, the filtering module 10, the voltage conversion chip 20, the voltage stabilization module 30, and the second output terminal are sequentially connected, and the second input terminal is connected to the first output terminal of the power interface circuit, so as to convert the 12V power voltage received by the power interface from the power supply into the 5V working voltage for effective output.
Wherein, the filtering module 10 is used for filtering the ripple to eliminate the interference noise to obtain a stable dc voltage, and the stable dc voltage is output to the voltage converting chip 20; the voltage conversion chip 20 is used for performing voltage conversion, and an RT8279GSP chip can be adopted as a forward low dropout regulator, which can stably output a voltage of 5V; the voltage stabilizing module 30 functions to suppress self-oscillation, so as to stabilize and rectify the voltage and current output by the voltage converting chip 20 and then output the voltage and current.
In addition, referring to fig. 4, a switch SW may be further disposed between the first output end and the second input end, so as to switch on and off the power interface circuit and the voltage conversion circuit by operating the switch SW, thereby implementing the power on and off of the SSD test carrier board.
Further, referring to fig. 5, the filter module 10 includes a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5;
first ends of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are respectively connected with the second input end, and second ends of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are respectively grounded.
Preferably, the third capacitor C3 and the fourth capacitor C4 may adopt 10uF capacitors, and the fifth capacitor C5 may adopt 0.1uF capacitors, that is, in this embodiment, the filter module 10 adopts a form of parallel connection of a large capacitor and a small capacitor to realize the filtering function thereof. Wherein, the big electric capacity can filter out low frequency ripple, and the little electric capacity can filter out high frequency ripple.
Further, referring to fig. 5, the voltage regulation module 30 includes a sixth capacitor C6, a voltage regulation diode D, an inductor L, a seventh capacitor C7, a first resistor R1, a second resistor R2, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10;
a first end of the sixth capacitor C6 is connected to the voltage converting chip 20, a second end of the sixth capacitor C6 is connected to a first end of the zener diode D, and a second end of the zener diode D is grounded;
the first end of the inductor L is connected with the voltage conversion chip 20, and the second end of the inductor L is connected with the second output end;
first ends of a seventh capacitor C7, a first resistor R1 and a second resistor R2 are connected with each other and are all connected with the voltage conversion chip 20, a second end of the seventh capacitor C7, a second end of the first resistor R1 and a second end of the inductor L are connected with each other and are all connected with a second output end, and a second end of the second resistor R2 is grounded;
a first end of the eighth capacitor C8 is connected to the second output end, and a second end of the eighth capacitor C8 is grounded;
a first terminal of the ninth capacitor C9 is connected to the second output terminal, a second terminal of the ninth capacitor C9 is grounded, a first terminal of the tenth capacitor C10 is connected to a first terminal of the ninth capacitor C9, and a second terminal of the tenth capacitor C10 is connected to a second terminal of the ninth capacitor C9.
Specifically, in the voltage stabilizing module 30, filtering and voltage stabilizing rectification are combined through the sixth capacitor C6, the voltage stabilizing diode D and the inductor L, voltage value matching is performed through the seventh capacitor C7, the first resistor R1 and the second resistor R2, and filtering is performed through the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10, so that a stable voltage is output, and the voltage conversion effect is further improved.
Further, referring to fig. 6, the SSD interface circuit includes a third input terminal, a third resistor R3, a fourth resistor R4, a first diode LEDD1, a second diode LEDD 2; the SSD interface 110 includes a V5 pin, a GND pin, and a RSV pin;
first ends of the third resistor R3 and the fourth resistor R4 are connected to each other, and are connected to a V5 pin and a third input end of the SSD interface 110;
a second end of the third resistor R3 is connected to a first end of a first diode LEDD1, a second end of the first diode LEDD1 is connected to the GND pin of the SSD interface 110 and grounded, a second end of the fourth resistor R4 is connected to a first end of a second diode LEDD2, and a second end of the second diode LEDD2 is connected to the RSV pin of the SSD interface 110;
and the third input end is connected with the second output end.
The SSD interface circuit according to this embodiment is configured to receive an operating voltage for performing a power-on test of the SSD, and specifically, a third input terminal of the SSD interface circuit receives the operating voltage of the voltage conversion circuit to provide the operating voltage to the SSD interface 110, where the first diode LEDD1 is used for indicating whether the operating voltage is abnormal, the second diode LEDD2 is used for indicating whether the SSD connection is abnormal, and the first diode LEDD1 and the second diode LEDD2 can both display red and green colors, where red indicates abnormal, and green indicates normal. It is easy to understand that, a voltage threshold can be preset, when the working voltage is detected to exceed the preset voltage threshold, the first diode LEDD1 is displayed in red, otherwise, the working voltage is displayed in green, the working voltage information of the SSD test carrier plate is fed back to the user in real time through the color display of the first diode LEDD1, and when the working voltage is abnormal, the user can be reminded of powering off in time. Correspondingly, the connection state information of the SSD and the SSD test carrier plate is fed back to a user in real time through the color display of the second diode LEDD2, and when the SSD is abnormally connected, the user can be reminded to adjust and repair in time, so that the normal transmission of test data is ensured.
In addition, the third resistor and the fourth resistor are arranged to prevent the first diode LEDD1 and the second diode LEDD2 from being burned out due to excessive current so as to perform current limiting protection. Actually, referring to fig. 1, the first diode LEDD1 and the second diode LEDD2 involved in the circuit are the first indicator light 130 and the second indicator light 140 correspondingly disposed on the substrate 100.
In a preferred embodiment, referring to fig. 6 and 7, SSD interface 110 and communication interface 120 include an rxp pin, an rxn pin, a txn pin, and a txp pin for making connections.
Specifically, the SSD interface 110 and the communication interface 120 are correspondingly provided with an rxp pin, an rxn pin, a txn pin, and a txp pin, which are connected to each other, and the rxp pin and the rxn pin are used as differential input terminals, and the txn pin and the txp pin are used as differential output terminals, so as to implement signal transmission.
In a preferred embodiment, referring to fig. 1 and 2, there are a plurality of communication interfaces 120;
the SSD interfaces 110 form SSD interface groups, and each SSD interface group corresponds to one communication interface 120.
Specifically, a plurality of communication interfaces 120 and a plurality of SSD interface groups are arranged on the SSD test carrier, and one communication interface 120 is correspondingly connected to a plurality of SSD interfaces 110 in one SSD interface group, so as to increase the number of SSD tests on the SSD test carrier by increasing the number of communication interfaces 120 and SSD interfaces 110 on the SSD test carrier, thereby further improving the test productivity and the test efficiency. Specifically, the number of the communication interfaces 120 may be 12, the SSD interfaces 110 may be 48, and form 12 sets of SSD interfaces 110, and 1 communication interface 120 corresponds to 4 SSD interfaces 110, which should be noted as an example and not a limitation, and a person skilled in the art may select the number and the corresponding relationship of the communication interfaces 120 and the SSD interfaces 110 according to practical situations.
Preferably, referring to fig. 1 and fig. 2, the communication interface 120 corresponds to a set of SSD interface sets correspondingly connected to the communication interface, so as to facilitate plugging and pulling of each SSD during testing, reduce human error operation, save labor cost, and improve testing efficiency. In addition, the space between the SSD interfaces 110 may be set slightly larger to facilitate manual disk replacement.
Further, referring to fig. 1 and 2, the SSD test carrier plate further includes a plurality of openings 150;
the number of the power interfaces is several;
the switch 150 is connected to the power source interface and the plurality of SSD interface groups, respectively.
Specifically, the switches 150 can control the on/off of the multiple SSD interface groups connected to the corresponding power interfaces, that is, the switches 150 can control the multiple SSD interface 110 groups respectively, so as to avoid the transient current of the start-up from being too large, thereby improving the test stability. In order to facilitate control and power-on/off operation, the switch 150 may be disposed on the front surface of the substrate 100 of the SSD test carrier, and disposed corresponding to the SSD interfaces 110 controlled by the switch 150, in combination with the above embodiments, specifically, each of the power interfaces and the switches 150 is 3, and each of the 1 power interface and the 1 switch 150 corresponds to 4 SSD interface 110 groups, that is, 16 SSD interfaces 110, it should be noted that this is only exemplary, and not limiting, and for the configuration of the power interfaces and the switches 150, a person skilled in the art may select according to actual situations.
In addition, the switch 150 may be a switch SW in the circuit mentioned in the above embodiment, and accordingly, the switch SW is disposed between the power interface circuit and the plurality of voltage converting circuits.
The utility model discloses still provide a SSD test system, this SSD test system include SSD test support plate, and the concrete structure of this SSD test support plate refers to above-mentioned embodiment, because this SSD test system has adopted all technical scheme of above-mentioned all embodiments, consequently has all technical effects that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary details one by one here.
The above is only the part or the preferred embodiment of the present invention, no matter the characters or the drawings can not limit the protection scope of the present invention, all under the whole concept of the present invention, the equivalent structure transformation performed by the contents of the specification and the drawings is utilized, or the direct/indirect application in other related technical fields is included in the protection scope of the present invention.
Claims (10)
1. The SSD test carrier plate is characterized by comprising a substrate, a power interface, an SSD interface and a communication interface, wherein the SSD interface and the power interface are arranged on the front surface of the substrate, and the communication interface is arranged on the back surface of the substrate;
the SSD interface is used for connecting an SSD, the power supply interface is electrically connected with the SSD interface, the communication interface is electrically connected with the SSD interface, and the communication interface is used for connecting a test host to transmit a test signal.
2. The SSD test carrier of claim 1, further comprising a power interface circuit, a voltage conversion circuit and an SSD interface circuit disposed on the substrate and connected in sequence, wherein the power interface circuit comprises a first output terminal, a first capacitor, a second capacitor, a power ground terminal, a first power input terminal and a second power input terminal;
the first power supply input end and the second power supply input end are respectively connected with the power supply interface;
the first capacitor and the second capacitor are connected in parallel between the first power supply input end and the second power supply input end;
the first output end is connected with the first power supply input end;
the power ground terminal is connected to the second power input terminal.
3. The SSD test carrier of claim 2, wherein the voltage conversion circuit comprises a second input terminal, a filter module, a voltage conversion chip, a voltage regulation module, and a second output terminal;
the first end of the filtering module is connected with the second input end, and the second end of the filtering module is connected with the first end of the voltage conversion chip;
the second end of the voltage conversion chip is connected with the first end of the voltage stabilizing module, and the second end of the voltage stabilizing module is connected with the second output end;
the second input end is connected with the first output end, and the second output end is connected with the SSD interface circuit.
4. The SSD test carrier of claim 3, wherein the filter module comprises a third capacitor, a fourth capacitor, and a fifth capacitor;
first ends of the third capacitor, the fourth capacitor and the fifth capacitor are respectively connected with the second input end, and second ends of the third capacitor, the fourth capacitor and the fifth capacitor are respectively grounded.
5. The SSD test carrier of claim 3, wherein the voltage regulator module comprises a sixth capacitor, a Zener diode, an inductor, a seventh capacitor, a first resistor, a second resistor, an eighth capacitor, a ninth capacitor, and a tenth capacitor;
the first end of the sixth capacitor is connected with the voltage conversion chip, the second end of the sixth capacitor is connected with the first end of the voltage stabilizing diode, and the second end of the voltage stabilizing diode is grounded;
the first end of the inductor is connected with the voltage conversion chip, and the second end of the inductor is connected with the second output end;
the first ends of the seventh capacitor, the first resistor and the second resistor are connected with each other and are all connected with the voltage conversion chip, the second end of the seventh capacitor, the second end of the first resistor and the second end of the inductor are connected with each other and are all connected with the second output end, and the second end of the second resistor is grounded;
the first end of the eighth capacitor is connected with the second output end, and the second end of the eighth capacitor is grounded;
the first end of the ninth capacitor is connected to the second output end, the second end of the ninth capacitor is grounded, the first end of the tenth capacitor is connected to the first end of the ninth capacitor, and the second end of the tenth capacitor is connected to the second end of the ninth capacitor.
6. The SSD test carrier of claim 3, wherein the SSD interface circuitry comprises a third input, a third resistor, a fourth resistor, a first diode LED, a second diode LED;
first ends of the third resistor and the fourth resistor are connected with each other and connected with a V5 pin and a third input end of the SSD interface;
a second end of the third resistor is connected with a first end of the first diode LED, a second end of the first diode LED is connected with a GND pin of the SSD interface and is grounded, a second end of the fourth resistor is connected with a first end of the second diode LED, and a second end of the second diode LED is connected with an RSV pin of the SSD interface;
wherein the third input terminal is connected to the second output terminal.
7. The SSD test carrier of claim 6, wherein the SSD interface and communication interface comprises an rxp pin, an rxn pin, a txn pin, and a txp pin for making connections.
8. The SSD test carrier of claim 1, wherein the communication interfaces are a plurality of;
the SSD interfaces form SSD interface groups, and each SSD interface group corresponds to one communication interface.
9. The SSD test carrier of claim 8, further comprising a number of switches;
the number of the power interfaces is several;
the switch is respectively connected with the power supply interface and the plurality of SSD interface groups.
10. An SSD test system comprising an SSD test carrier according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021180666.7U CN212541917U (en) | 2020-06-23 | 2020-06-23 | SSD test carrier plate and SSD test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021180666.7U CN212541917U (en) | 2020-06-23 | 2020-06-23 | SSD test carrier plate and SSD test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212541917U true CN212541917U (en) | 2021-02-12 |
Family
ID=74546246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021180666.7U Active CN212541917U (en) | 2020-06-23 | 2020-06-23 | SSD test carrier plate and SSD test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212541917U (en) |
-
2020
- 2020-06-23 CN CN202021180666.7U patent/CN212541917U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203224819U (en) | Mainboard | |
| CN209265427U (en) | A kind of multi-functional switching panel assembly for solid state hard disk | |
| CN213069082U (en) | Detection apparatus for detect TCONLESS mainboard | |
| CN212541917U (en) | SSD test carrier plate and SSD test system | |
| CN112526278B (en) | Switching device for optical module aging test, optical module aging device and method | |
| CN211087338U (en) | Electronic lock board card with multiple voice broadcast selection modes | |
| CN211403415U (en) | Type-C interface function testing device | |
| CN207098196U (en) | Socket | |
| CN211506476U (en) | Serial communication interface device | |
| CN216387328U (en) | Oscilloscope port expansion control equipment for power supply ripple test | |
| CN220252570U (en) | Development board for Internet of things | |
| CN219419782U (en) | Adapter plate and display device | |
| CN220896784U (en) | Data communication device for upgrading vehicle-mounted camera software | |
| CN219552981U (en) | Multi-type interface conversion device based on CPLD | |
| CN215219002U (en) | Automatic identification circuit for OTG equipment mode | |
| CN221081780U (en) | LED display screen and box thereof | |
| CN211928577U (en) | Industrial adapter plate based on fourth-generation mobile communication technology | |
| CN219761120U (en) | Multi-type camera test connection circuit and test system | |
| CN219246069U (en) | Circuit structure for realizing switchable power supply and data transmission | |
| CN216649530U (en) | Information acquisition remote communication terminal | |
| CN215867829U (en) | Optical module parallel burning device | |
| CN215910891U (en) | Serial port access feedback system | |
| CN218568023U (en) | Serial port upgrading device for electronic product | |
| CN209896402U (en) | Bull electronic equipment data line | |
| CN220399848U (en) | Controller software and hardware version acquisition display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: 518000 floors 1-3 and 4 of buildings 4 and 8, zone 2, Zhongguan honghualing Industrial South Zone, No. 1213 Liuxian Avenue, Pingshan community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee after: BIWIN STORAGE TECHNOLOGY Co.,Ltd. Address before: 518000 1st, 2nd, 4th and 5th floors of No.4 factory building, tongfuyu industrial town, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: BIWIN STORAGE TECHNOLOGY Co.,Ltd. |
|
| CP02 | Change in the address of a patent holder |