CN218939689U

CN218939689U - HBT device

Info

Publication number: CN218939689U
Application number: CN202222599279.2U
Authority: CN
Inventors: 李元铭; 蔡宗叡
Original assignee: Xiamen Sanan Integrated Circuit Co Ltd
Current assignee: Xiamen Sanan Integrated Circuit Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2023-04-28
Anticipated expiration: 2032-09-29

Abstract

The utility model discloses an HBT device, wherein a semiconductor structure of the HBT device comprises a substrate, a collector region, a base region and an emitter region from bottom to top; the base region comprises a P+InGaAs base layer, and the emitter region comprises a GaAs emitter layer, an N-InGaAs layer, an N+InGaAs layer and an N+InGaNAs contact layer from bottom to top; the emitter electrode is arranged on the N+InGaNAs contact layer. The N+InGaNAs material is adopted as the emitter contact layer, the energy gap is reduced by utilizing the In component, the energy gap is reduced by utilizing the N component, the emitter contact resistance is lower, and the effects of improving the cut-off frequency, vsat, beta value and the like are realized.

Description

HBT device

Technical Field

The utility model belongs to the technical field of semiconductor devices, and particularly relates to an HBT device.

Background

GaAs-based Heterojunction Bipolar Transistors (HBTs) typically employ materials with a larger band gap than the base layer to form the emitter layer, inhibiting injection of minority carriers from the base layer to the emitter layer, to achieve higher current gain. Emitter contacts are typically made of GaAs or InGaAs, and the contact region allows the Emitter region of the heterojunction bipolar transistor to achieve a lower contact resistance. However, with the improvement of the performance requirements of HBTs, the emitter contact layer realized by the existing GaAs or InGaAs materials has limited regulation and control on contact resistance, and the cut-off frequency and Vsat, beta value and other performances of the device are difficult to meet the requirements.

Disclosure of Invention

Aiming at the defects existing in the prior art, the utility model provides an HBT device.

In order to achieve the above object, the technical scheme of the present utility model is as follows:

an HBT device, a semiconductor structure of which comprises a substrate, a collector region, a base region and an emitter region from bottom to top; the base region comprises a P+InGaAs base layer, and the emitter region comprises a GaAs emitter layer, an N-InGaAs layer, an N+InGaAs layer and an N+InGaNAs contact layer from bottom to top; the emitter electrode is arranged on the N+InGaNAs contact layer.

Optionally, the thickness of the N+InGaNAs contact layer is 2-5 nm.

Optionally, the thickness of the N-InGaAs layer ranges from 1 nm to 5nm, and the thickness of the N+InGaAs layer ranges from 1 nm to 5nm.

Optionally, the collector region comprises a GaAs sub-collector layer, a high-doping concentration InGaP layer, a low-doping concentration InGaP layer and a GaAs collector layer from bottom to top, the base mesa is etched to expose the surface of the GaAs sub-collector layer, and the collector electrode is disposed on the surface of the GaAs sub-collector layer.

Optionally, the thickness of the high-doping concentration InGaP layer is greater than the thickness of the low-doping concentration InGaP layer.

Optionally, the thickness of the GaAs collector layer is 300-400 nm.

Optionally, the thickness of the GaAs sub-collector layer is 300-400 nm.

Optionally, the thickness of the high-doping concentration InGaP layer is 100-200 nm, and the thickness of the low-doping concentration InGaP layer is 100-200 nm.

Optionally, the base region further includes an etch stop layer over the p+ingaas base layer, the emitter mesa is etched to expose the surface of the etch stop layer, the etch stop layer is provided with an opening through which the base electrode contacts the p+ingaas base layer.

Optionally, the collector region comprises a GaAs sub-collector layer, a lower GaAs collector layer, an InGaP layer and an upper GaAs collector layer from bottom to top, the base mesa is etched to expose the surface of the GaAs sub-collector layer, and the collector electrode is disposed on the surface of the GaAs sub-collector layer.

Wherein the material of the N+InGaNAs contact layer is N+In _(1-x) Ga _x N _y As _(1-y) Wherein the value range of x is 0.99-0.9, and the value range of y is 0.01-0.1.

The beneficial effects of the utility model are as follows:

the N+InGaNAs material is adopted as the emitter contact layer, the energy gap is reduced by utilizing the In component, the energy gap is reduced by utilizing the N component, and the emitter contact resistance is lower than that of GaAs or InGaAs contact, so that the effects of improving the cut-off frequency, vsat, beta value and the like are realized, and the comprehensive performance of the device is improved.

Drawings

Fig. 1 is a schematic structural diagram of an HBT device of embodiment 1;

fig. 2 is a schematic structural diagram of the HBT device of embodiment 2.

Detailed Description

The utility model is further explained below with reference to the drawings and specific embodiments. The drawings of the present utility model are merely schematic to facilitate understanding of the present utility model, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.

Example 1

Referring to fig. 1, an HBT device has a semiconductor structure including, from bottom to top, a substrate 1, a collector region 2, a base region 3, and an emitter region 4. The substrate 1 is Al _x Ga _1-x An As layer; the collector region 2 comprises a GaAs sub-collector layer 21, a high-doping concentration InGaP layer 22, a low-doping concentration InGaP layer 23 and a GaAs collector layer 24 from bottom to top; the base region 3 includes, from bottom to top, a p+ingaas base layer 31 and an etch stop layer 32; the emitter region 4 includes, from bottom to top, a GaAs emitter layer 41, an N-InGaAs layer 42, an N + InGaAs layer 43, and an N + InGaNAs contact layer 44. The emitter electrode 5 is provided on the N + InGaNAs contact layer 44. The emitter mesa is etched to expose the surface of the etch stop layer 32, the material of the etch stop layer 32 may be InGaP, the etch stop layer 32 is provided with openings through which the base electrode 6 is in contact with the P + InGaAs base layer 31. The base mesa is etched to expose the surface of the GaAs sub-collector layer 21 and the collector electrode 7 is provided on the GaAs sub-collector layer 21. The device surface is covered with a passivation layer 8, the passivation layer 8 having openings for letting out electrodes.

In the emitter region 4, the thickness of the N-InGaAs layer 42 ranges from 1 to 5nm, for example 3nm; the thickness of the N + InGaAs layer 43 ranges from 1 to 5nm, for example 3nm; the N + InGaNAs contact layer 44 may be 2 to 5nm thick, for example 3nm. The material of the n+inganas contact layer 44 is specifically n+in _(1-x) Ga _x N _y As _(1-y) Wherein the value range of x is 0.99-0.9, and the value range of y is 0.01-0.1. For example, the material composition of the n+inganas contact layer 44 is n+in _0.1 Ga _0.99 N _0.1 As _0.99 、N+In _0.05 Ga _0.95 N _0.05 As _0.95 And the like, and the doping concentration is, for example, 5e18. The emitter electrode 5 is deposited on the N + InGaNAs contact layer 44 and may be a single component metal material, alloy or metal stack material, for example Al is the metal layer in contact with the N + InGaNAs contact layer 44. Using high-concentration InGaNAs material, reducing energy gap by using In component, and reusing N formationThe energy gap is reduced to achieve low emitter contact resistance and to improve cut-off frequency, vsat, beta values. In addition, the InGaNAs material and the InGaAs material have higher lattice matching, and the stability of the multilayer stacking structure is strong.

In the collector region 2, two InGaP layers are interposed in GaAs, and the doping concentration of the lower layer is higher than that of the upper layer. The thickness of the GaAs sub-collector layer 21 is 300 to 400nm and the thickness of the GaAs collector layer 24 is 300 to 400nm. The high-doping concentration InGaP layer and the low-doping concentration InGaP layer described herein mean that both are homogeneously doped and have different doping concentrations, for example, the high-doping concentration InGaP layer 22 has a doping concentration of 1e19 and a thickness of 150nm; the low-doping concentration InGaP layer 23 has a doping concentration of 5e18 and a thickness of 100nm. By inserting two InGaP layers with different doping concentrations into the collector region, vknee Voltage can be effectively reduced, and the performance of the device is further improved. The InGaP layer inserted into the collector region also serves as an etching stop layer.

The passivation layer 8 is made of conventional SiN, siO ₂ And the like, and openings are provided for the emitter electrode 5, the base electrode 6 and the collector electrode 7 to facilitate wiring connection.

HBT V in active application _BE When the forward bias is in forward bias, the concentration of the depletion region of Je is changed without changing Base, and the low-energy-gap material is adopted, so that the problem of energy band discontinuity is reduced, and the impedance problem of the material is changed; HBT V at cut-off application _BE When the reverse bias is applied, the concentration of the depletion region of Je and the material with low energy gap are changed without changing the Base, the problem of energy band discontinuity is reduced, the impedance of the material is changed, and the depletion region of Je is reduced, so that the effects of improving the cut-off frequency, vsat, beta value and the like are achieved.

Example 2

Referring to fig. 2, embodiment 2 differs from embodiment 1 in that collector region 2' includes GaAs sub-collector layer 25, lower GaAs collector layer 26, inGaP layer 27, and upper GaAs collector layer 28 from bottom to top, the base mesa is etched to expose the surface of GaAs sub-collector layer 25, and collector electrode 7 is provided on the surface of GaAs sub-collector layer 25. Wherein the lower GaAs collector layer 26 and the upper GaAs collector layer 28 have similar or identical thicknesses, the InGaP layer 27 has a doping concentration of 8e18 and a thickness of 200nm. The InGaP layer 27 is provided in the middle of the GaAs collector layer to reduce the Vknee Voltage. The remainder was referred to example 1.

The above embodiment is only used to further illustrate an HBT device according to the present utility model, but the present utility model is not limited to the embodiment, and any simple modification, equivalent variation and modification made to the above embodiment according to the technical substance of the present utility model falls within the protection scope of the technical solution of the present utility model.

Claims

1. An HBT device characterized by: the semiconductor structure of the HBT device comprises a substrate, a collector region, a base region and an emitter region from bottom to top; the base region comprises a P+InGaAs base layer, and the emitter region comprises a GaAs emitter layer, an N-InGaAs layer, an N+InGaAs layer and an N+InGaNAs contact layer from bottom to top; the emitter electrode is arranged on the N+InGaNAs contact layer.

2. The HBT device of claim 1 wherein: the thickness of the N+InGaNAs contact layer is 2-5 nm.

3. The HBT device of claim 1 wherein: the thickness of the N-InGaAs layer ranges from 1 nm to 5nm, and the thickness of the N+InGaAs layer ranges from 1 nm to 5nm.

4. The HBT device of claim 1 wherein: the collector region comprises a GaAs sub-collector layer, a high-doping concentration InGaP layer, a low-doping concentration InGaP layer and a GaAs collector layer from bottom to top, the base table top is corroded to the surface of the exposed GaAs sub-collector layer, and the collector electrode is arranged on the surface of the GaAs sub-collector layer.

5. The HBT device of claim 4 wherein: the thickness of the high-doping concentration InGaP layer is larger than that of the low-doping concentration InGaP layer.

6. The HBT device of claim 4 wherein: the thickness of the GaAs collector layer is 300-400 nm.

7. The HBT device of claim 4 wherein: the thickness of the GaAs sub-collector layer is 300-400 nm.

8. The HBT device of claim 4 wherein: the thickness of the high-doping concentration InGaP layer is 100-200 nm, and the thickness of the low-doping concentration InGaP layer is 100-200 nm.

9. The HBT device of claim 1 wherein: the base region further includes an etch stop layer over the P + InGaAs base layer, the emitter mesa being etched to expose the surface of the etch stop layer, the etch stop layer being provided with an opening through which the base electrode contacts the P + InGaAs base layer.

10. The HBT device of claim 1 wherein: the collector region comprises a GaAs sub-collector layer, a lower GaAs collector layer, an InGaP layer and an upper GaAs collector layer from bottom to top, the base table top is corroded to expose the surface of the GaAs sub-collector layer, and the collector electrode is arranged on the surface of the GaAs sub-collector layer.