CN218918006U - Clock control circuit, circuit system and electronic equipment - Google Patents
Clock control circuit, circuit system and electronic equipment Download PDFInfo
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- CN218918006U CN218918006U CN202223281371.0U CN202223281371U CN218918006U CN 218918006 U CN218918006 U CN 218918006U CN 202223281371 U CN202223281371 U CN 202223281371U CN 218918006 U CN218918006 U CN 218918006U
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Abstract
The utility model discloses a clock control circuit, a circuit system and an electronic device, wherein the clock control circuit is applied to an IC chip, the IC chip comprises at least one clock signal input end, and the clock control circuit comprises a clock signal source and a plurality of logic control modules; the output end of the clock signal source is correspondingly connected with the input ends of the logic control modules; the logic control module is used for carrying out logic control on the first clock signal output by the clock signal source and outputting a second clock signal from the output end of the logic control module; the frequency of the first clock signal is the same as the frequency of the second clock signal. The technical scheme provided by the embodiment of the utility model can output multiple paths of clock signals simultaneously only by one clock signal source, is beneficial to reducing the system cost, can ensure that each second clock signal received by the IC chip has higher signal quality, and completely meets the requirements of the IC chip on the clock signals.
Description
Technical Field
The present utility model relates to the field of circuit design technologies, and in particular, to a clock control circuit, a circuit system, and an electronic device.
Background
In most of the existing electronic devices, there are a large number of IC (Integrated Circuit ) chips. When each electronic device in the IC chip works, a clock signal is provided to distribute the working sequence of each device so as to ensure the normal work of the IC chip.
In the prior art, when clock signals are provided for an IC chip, the problems of low clock signal quality, high chip power consumption, high cost and the like exist, and the working requirements of the IC chip are not met.
Disclosure of Invention
The utility model provides a clock control circuit, a circuit system and an electronic device, which are used for optimizing the clock circuit, reducing the cost and improving the signal quality of a clock signal provided to an IC chip.
According to an aspect of the present utility model, there is provided a clock control circuit for use with an IC chip, the IC chip including at least one clock signal input, the clock control circuit including a clock signal source and a plurality of logic control modules;
the output end of the clock signal source is correspondingly connected with the input ends of the logic control modules; the logic control module is used for carrying out logic control on the first clock signal output by the clock signal source and outputting a second clock signal from the output end of the logic control module; the output end of each logic control module is correspondingly connected with at least one clock signal input end on at least one IC chip respectively; the multi-channel clock signal can be output simultaneously by only one clock signal source, which is beneficial to reducing the cost of the system and ensures that each second clock signal received by the IC chip has higher signal quality.
Wherein the frequency of the first clock signal is the same as the frequency of the second clock signal.
Optionally, the logic control module includes an and gate, the and gate includes a first input end, a second input end, and an output end, and the input end of the logic control module includes a first input end and a second input end;
the first input end of the AND gate is used as the first input end of the logic control module and is connected with the output end of the clock signal source, the second input end of the AND gate is used as the second input end of the logic control module and is connected with logic control voltage, and the output end of the AND gate is connected with the clock signal input end of the IC chip. The AND gate has small volume, low power consumption and low cost, so the wiring difficulty of the PCB can be reduced, the occupied space of the device is reduced, and the system cost can be reduced.
Optionally, the level of the logic control voltage is logic 1.
Optionally, the logic control module includes an or gate, the or gate includes a first input end, a second input end, and an output end, and the input end of the logic control module includes a first input end and a second input end;
the first input end of the OR gate is used as the first input end of the logic control module and is connected with the output end of the clock signal source, the second input end of the OR gate is used as the second input end of the logic control module and is connected with logic control voltage, and the output end of the OR gate is connected with the clock signal input end of the IC chip. The OR gate has small volume, low power consumption and low cost, so that the wiring difficulty of the PCB can be reduced, the occupied space of the device is reduced, and the system cost can be reduced.
Optionally, the level of the logic control voltage is logic 0.
Optionally, the clock control circuit further includes a resistor, a first end of the resistor is connected to the logic control voltage, and a second end of the resistor is connected to the second input end of the logic control module to match the input voltage of the logic control module.
Optionally, the clock signal source comprises a crystal oscillator; the crystal oscillator comprises a differential crystal oscillator to provide a stable first clock signal.
Optionally, the delay time of the logic control module is inversely related to the clock frequency of the clock signal source, and the logic control module with small type delay time is selected, so that the logic control module can be matched with the high-frequency first clock signal, and the signal quality of the second clock signal is ensured.
According to another aspect of the utility model, a circuit system is provided, comprising the clock control circuit provided by any of the embodiments of the utility model.
According to another aspect of the utility model, an electronic device is provided comprising the circuitry provided by any of the embodiments of the utility model.
According to the technical scheme, the plurality of logic control modules are arranged at the output end of the clock signal source, so that a point-to-point topological structure is formed between the logic control modules and the clock signal input end of the IC chip, and the first clock signal output by the clock signal source is logically controlled through the logic control modules, so that the purpose of improving the signal quality of the first clock signal is achieved. Compared with the prior art, the technical scheme provided by the embodiment of the utility model can output multiple paths of clock signals simultaneously only by one clock signal source, is beneficial to reducing the system cost, can ensure that each second clock signal received by the IC chip has higher signal quality, and completely meets the requirements of the IC chip on the clock signals.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a clock control circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model;
FIG. 4 is a diagram showing waveforms of clock signals in AND gate logic operation according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model;
FIG. 6 is a diagram showing waveforms of clock signals during OR gate logic operation according to an embodiment of the present utility model;
FIG. 7 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model;
fig. 8 is a waveform diagram of a second clock signal according to an embodiment of the utility model.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
As described in the background art, the prior art has the problems of low clock signal quality, large chip power consumption, high cost and the like when providing clock signals for IC chips, and is not beneficial to the design of mass production products. An IC chip generally includes a plurality of clock interfaces, and in the prior art, a crystal oscillator is generally adopted to provide clock signals for the plurality of clock interfaces at the same time, and this connection mode leads to a plurality of branch lines at the output end of the crystal oscillator, which cannot achieve impedance matching, aggravates the signal reflection phenomenon, makes the integrity of the clock signals worse, and cannot meet the condition of stable operation of the chip. And a plurality of crystal oscillators are adopted to simultaneously provide clock signals for a plurality of clock interfaces, so that the power consumption of an IC chip is increased, the manufacturing cost of the system is increased, and the mass production design of products is not facilitated. For this purpose, a chip with a clock Buffer (Buffer) is used to realize the transmission of the clock signal. According to the scheme, the clock Buffer chip is arranged between the crystal oscillator and the IC chip, the clock signal quality is guaranteed by utilizing the frequency copying function of the clock Buffer chip, but the cost of the clock Buffer chip is still high, and the power consumption cannot be effectively reduced. Therefore, there is room for optimization in the clock circuits in the prior art.
Based on the above problems, the present utility model provides a clock control circuit. Fig. 1 is a schematic diagram of a clock control circuit according to an embodiment of the present utility model, referring to fig. 1, the clock control circuit 20 may be applied to an IC chip 10, the IC chip 10 includes at least one clock signal input terminal SCK (SCK 1, SCK2, SCK3, … …), and the clock control circuit 20 includes a clock signal source 210 and a plurality of logic control modules 220; the output end of the clock signal source 210 is correspondingly connected with the input ends of the logic control modules 220; the logic control module 220 is configured to perform logic control on the first clock signal CLK1 output by the clock signal source 210, and output the second clock signal CLK2 from an output terminal thereof; the output end of each logic control module 220 is correspondingly connected with at least one clock signal input end SCK on at least one IC chip 10; wherein the frequency of the first clock signal CLK1 is the same as the frequency of the second clock signal CLK2.
Specifically, the frequencies of the clock signals required by the clock signal input terminals SCK of the IC chip 10 are the same, and the clock control circuit 20 is configured to transmit the clock signals with the same clock frequency to the clock signal input terminals SCK corresponding to the IC chip 10, so as to control the IC chip to operate stably.
In the present embodiment, the clock control circuit 20 is at least composed of a clock signal source 210 and a logic control module 220, wherein the logic control module 220 is configured to perform logic control on a first clock signal CLK1 output by the clock signal source 210 and output a second clock signal CLK2 to the IC chip 10. Here, the logic control module 220 does not change the frequency of the first clock signal CLK1, and only adjusts the waveform of the first clock signal CLK1 to improve the signal quality of the clock signal received by the IC chip 10.
It should be noted that, since there are multiple branches of the line transmitting the first clock signal CLK1 at the output end of the clock signal source 210, the impedance between the clock signal source 210 and the IC chip 10 is not matched, so that the rising edge and/or the falling edge of the first clock signal CLK1 have the problems of non-monotone, overshoot, rollback, ringing, and the like, thereby causing false triggering of the IC chip 10. The logic control module 220 performs logic control on the first clock signal CLK1, so as to achieve the purpose of adjusting the waveform of the first clock signal CLK1, so as to reduce or eliminate non-monotonic, overshoot, rollback or ringing existing on the rising edge and/or falling edge of the second clock signal CLK2 output by the logic control module 220, so that the clock signal (the second clock signal CLK 2) can meet the requirements of the IC chip 10.
The number of the logic control modules 220 is not less than the number of clock signals required by the IC chip 10, and a point-to-point topology is formed between the logic control modules 220 and the clock signal input terminal SCK of the IC chip 10.
According to the clock control circuit provided by the embodiment of the utility model, the plurality of logic control modules are arranged at the output end of the clock signal source, so that a point-to-point topological structure is formed between the logic control modules and the clock signal input end of the IC chip, and the first clock signal output by the clock signal source is logically controlled by the logic control modules, so that the purpose of improving the signal quality of the first clock signal is achieved. Compared with the prior art, the technical scheme provided by the embodiment of the utility model can output multiple paths of clock signals simultaneously by only one clock signal source, is beneficial to reducing the system cost, can ensure that each second clock signal received by the IC chip has higher signal quality, and completely meets the requirements of the IC chip on the clock signals.
In the above embodiment, the IC chip 10 needs a plurality of clock signals with the same frequency, and in practical use, the circuit system includes a plurality of IC chips 10, and the plurality of IC chips 10 may need the clock signals with the same frequency at the same time, and the clock control circuit 20 is needed to provide the clock signals for the plurality of IC chips 10 at the same time. Fig. 2 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model, and referring to fig. 2, fig. 2 schematically shows a structure in which the clock control circuit 20 is simultaneously connected to a plurality of IC chips 10, and each logic control module 220 corresponds to a clock signal input SCK of an IC chip 10, and the specific principle of the structure is the same as that of the structure shown in fig. 1 and will not be repeated.
In this embodiment, the clock signal source 210 may be a crystal oscillator for generating the first clock signal CLK1. The crystal oscillator can be a differential crystal oscillator so as to eliminate common mode noise and improve the stability of clock signals.
In other embodiments, the clock signal source 210 may also be other oscillators or clock generation modules.
Fig. 3 is a schematic structural diagram of another clock control circuit according to an embodiment of the present utility model, referring to fig. 3, on the basis of the above technical solutions, optionally, the logic control module 220 includes an and gate I1, where the and gate I1 includes a first input end, a second input end and an output end, and the input end of the logic control module 220 includes the first input end and the second input end; the first input terminal of the and gate I1 is connected to the output terminal of the clock signal source 210 as a first input terminal of the logic control module 220, the second input terminal of the and gate I1 is connected to the logic control voltage V1 as a second input terminal of the logic control module 220, and the output terminal of the and gate I1 is connected to the clock signal input terminal SCK of the IC chip 10.
The and gate I1 is a logic operation device implementing logic "multiplication", and outputs a high level only when all its input terminals input a high level (logic 1), otherwise outputs a low level (logic 0).
Specifically, the and gate I1 includes two input terminals, a first input terminal of the and gate I1 inputs the first clock signal CLK1, and a second input terminal inputs the logic control voltage V1, where the logic control voltage may be the first power supply voltage VCC, and a level of the first power supply voltage VCC is logic 1. That is, the logic control voltage V1 at this time is a high level voltage. Fig. 4 is a waveform diagram of a clock signal under and gate logic operation according to an embodiment of the present utility model, and in combination with fig. 4, when the first clock signal CLK1 output by the clock signal source 210 is at a low level, the second clock signal CLK2 output by the and gate I1 is at a low level. When the first clock signal CLK1 is at a high level, the output second clock signal CLK2 is at a high level through the logic operation of the and gate I1. While the clock signal source 210 continuously outputs the first clock signal CLK1, the and gate I1 re-drives the first clock signal CLK1 to the second clock signal CLK2.
Fig. 5 is a schematic structural diagram of another clock control circuit according to an embodiment of the present utility model, referring to fig. 5, on the basis of the above technical solutions, optionally, the logic control module 220 includes an or gate I2, the or gate I2 includes a first input end, a second input end and an output end, and the input end of the logic control module 220 includes the first input end and the second input end; the first input terminal of the or gate I2 is connected to the output terminal of the clock signal source 210 as the first input terminal of the logic control module 220, the second input terminal of the or gate I2 is connected to the logic control voltage V1 as the second input terminal of the logic control module 220, and the output terminal of the or gate I2 is connected to the clock signal input terminal SCK of the IC chip 10.
The or gate I2 is a logic operation device implementing a logical sum, and its output is low only when all its input terminals input a low level (logic 0), otherwise, it outputs a high level (logic 1).
Specifically, the or gate I2 includes two input terminals, the first input terminal of the or gate I2 inputs the first clock signal CLK1, and the second input terminal of the or gate I2 inputs the logic control voltage V1, where the logic control voltage may be the second power supply voltage VSS, and the level of the second power supply voltage VSS is logic 0. That is, the logic control voltage V1 at this time is a low level voltage. Fig. 6 is a waveform diagram of a clock signal under an or gate logic operation according to an embodiment of the present utility model, and in combination with fig. 6, when the first clock signal CLK1 output by the clock signal source 210 is at a low level, the second clock signal CLK2 output by the or gate I2 is at a low level. When the first clock signal CLK1 is at a high level, the output second clock signal CLK2 is at a high level through the logical operation of the or gate I2. While the clock signal source 210 continuously outputs the first clock signal CLK1, the or gate I2 re-drives and outputs the first clock signal CLK1 as the second clock signal CLK2.
According to the technical scheme provided by the embodiment of the utility model, the plurality of logic gate elements (AND gates I1/OR gates I2) are arranged at the output end of the clock signal source 210, so that the first clock signal CLK1 output by the clock signal source 210 is redriven, and adverse phenomena such as non-monotone, overshoot, back hook, ringing and the like of the rising edge and/or the falling edge of the generated second clock signal CLK2 are eliminated or reduced, and the signal quality of the second clock signal CLK2 output to the IC chip 10 is higher, so that the requirements of the IC chip 10 on the clock signal are greatly met. In this embodiment, the function of providing multiple clock signals to the IC chip 10 can be realized by only one clock signal source 210, which is beneficial to realizing clock synchronization and ensuring stable operation of the IC chip 10 compared with the conventional scheme of multiple clock signal sources 210.
Further, when the PCB layout is performed, the logic gate element is small, and can be placed close to the clock signal input SCK of the IC chip 10, so that a large wiring space is not occupied, and the transmission loss of the clock signal is reduced. In addition, since the logic gate element can re-drive the first clock signal CLK1, the distance between the clock signal source 210 and the IC chip 10 can be properly increased, which is beneficial to optimizing the layout wiring of the PCB and reducing the PCB manufacturing difficulty.
In this embodiment, the power consumption of the logic gate element is very small, and the power supply cost of the system is not increased. Compared with the technical scheme that a clock Buffer chip is adopted in the prior art, the cost of the logic gate element is far lower than that of the clock Buffer chip, so that the system cost can be greatly reduced, and the technical scheme provided by the embodiment does not need extra control signals, is beneficial to releasing the internal resources of the IC chip 10 and reduces the system power consumption.
Fig. 7 is a schematic diagram of another clock control circuit according to an embodiment of the present utility model, and referring to fig. 7, optionally, the clock control circuit further includes a resistor R to balance the input voltage of the second input terminal of the logic control module 220. The first end of the resistor R is connected to the logic control voltage V1, and the second end of the resistor R is connected to the second input end of the logic control module 220. For example, taking the and gate I1 as an example, the second input terminal of the and gate I1 is connected to the logic control voltage V1 through the resistor R, and under the voltage division effect of the resistor R, the logic control voltage V1 can be matched to the voltage required by the and gate I1, which is favorable for realizing the stable operation of the and gate I1.
It should be understood that fig. 7 only schematically illustrates the case where the logic control module 220 includes the and gate I1, and is not limited thereto.
It should be noted that, in other embodiments of the present utility model, the logic control module 220 may be a combination structure of the and gate I1 and the or gate I2, or a logic control structure formed by other logic gate elements (such as a nand gate, a nor gate, etc.), as long as the function of re-driving the first clock signal CLK1 can be implemented.
In this embodiment, the delay time of the logic control module 220 is inversely related to the clock frequency of the clock signal source 210. That is, the higher the clock frequency of the clock signal source 210, the smaller the delay time of the logic control module 220, so that the logic control module 220 does not distort the waveform of the first clock signal CLK1 when the first clock signal CLK1 outputted from the clock signal source 210 is re-driven.
Taking the logic control module 220 including the and gate I1 and the clock signal source 210 outputting the fixed clock frequency of 156.25MHz as an example, fig. 8 is a waveform chart of a second clock signal according to an embodiment of the present utility model, and fig. 8 shows waveforms of the second clock signal CLK2 output under 3 different delay times respectively. The #1 waveform is obtained under the condition that the delay time of the AND gate I1 is 5.4ns, the #2 waveform is obtained under the condition that the delay time of the AND gate I1 is 3.4ns, and the #3 waveform is obtained under the condition that the delay time of the AND gate I1 is 2.1 ns. Therefore, under the high-frequency clock signal, the duty ratio of the output second clock signal CLK2 gradually changes from more than 60% to approximately 50% (square wave signal) along with the decrease of the delay time of the and gate I1, thereby meeting the transmission requirement of the high-frequency clock signal and being beneficial to ensuring the signal quality of the second clock signal CLK2 transmitted to the IC chip 10.
Optionally, the embodiment of the present utility model further provides a circuit system, where the circuit system includes an IC chip and the clock control circuit provided by any of the foregoing embodiments, so that the circuit system provided by the present embodiment also has the beneficial effects described in any of the foregoing embodiments.
Optionally, the embodiment of the present utility model further provides an electronic device, where the electronic device includes the circuit system provided by the foregoing embodiment, so that the electronic device provided by this embodiment also has the beneficial effects described in any of the foregoing embodiments, and the electronic device includes, but is not limited to, a smart wearable device, a communication device, a computer, and so on.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present utility model may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present utility model are achieved, and the present utility model is not limited herein.
The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.
Claims (10)
1. A clock control circuit applied to an IC chip, the IC chip comprising at least one clock signal input terminal, characterized in that the clock control circuit comprises a clock signal source and a plurality of logic control modules;
the output end of the clock signal source is correspondingly connected with the input ends of the logic control modules; the logic control module is used for carrying out logic control on the first clock signal output by the clock signal source and outputting a second clock signal from the output end of the logic control module; the output end of each logic control module is correspondingly connected with at least one clock signal input end on at least one IC chip respectively;
wherein the frequency of the first clock signal is the same as the frequency of the second clock signal.
2. The clock control circuit of claim 1, wherein the logic control module comprises an and gate comprising a first input, a second input, and an output, the input of the logic control module comprising the first input and the second input;
the first input end of the AND gate is used as the first input end of the logic control module and is connected with the output end of the clock signal source, the second input end of the AND gate is used as the second input end of the logic control module and is connected with logic control voltage, and the output end of the AND gate is connected with the clock signal input end of the IC chip.
3. The clock control circuit of claim 2, wherein the level of the logic control voltage is a logic 1.
4. The clock control circuit of claim 1, wherein the logic control module comprises an or gate comprising a first input, a second input, and an output, the inputs of the logic control module comprising the first input and the second input;
the first input end of the OR gate is used as the first input end of the logic control module and is connected with the output end of the clock signal source, the second input end of the OR gate is used as the second input end of the logic control module and is connected with logic control voltage, and the output end of the OR gate is connected with the clock signal input end of the IC chip.
5. The clock control circuit of claim 4, wherein the level of the logic control voltage is logic 0.
6. The clock control circuit of any one of claims 2-5, further comprising a resistor, a first terminal of the resistor being coupled to the logic control voltage, a second terminal of the resistor being coupled to the second input terminal of the logic control module.
7. The clock control circuit of claim 1, wherein the clock signal source comprises a crystal oscillator;
the crystal oscillator comprises a differential crystal oscillator.
8. The clock control circuit of claim 1, wherein the delay time of the logic control module is inversely related to the clock frequency of the clock signal source.
9. Circuitry comprising an IC chip and a clock control circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising the circuitry of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202223281371.0U CN218918006U (en) | 2022-11-29 | 2022-11-29 | Clock control circuit, circuit system and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223281371.0U CN218918006U (en) | 2022-11-29 | 2022-11-29 | Clock control circuit, circuit system and electronic equipment |
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| CN218918006U true CN218918006U (en) | 2023-04-25 |
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| CN202223281371.0U Active CN218918006U (en) | 2022-11-29 | 2022-11-29 | Clock control circuit, circuit system and electronic equipment |
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