CN218831235U

CN218831235U - Display panel and display device

Info

Publication number: CN218831235U
Application number: CN202221609039.XU
Authority: CN
Inventors: 王晶; 李然; 陈善韬; 田宏伟
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-06-24
Filing date: 2022-06-24
Publication date: 2023-04-07
Anticipated expiration: 2032-06-24

Abstract

The disclosure provides a display panel and a display device, and relates to the technical field of display. The display panel includes: the display substrate is provided with a storage capacitor; the display substrate comprises a driving layer and a light emitting layer, the driving layer is located between the substrate and the light emitting layer, the driving layer comprises pixel circuits and switch circuits which are distributed at intervals, and the light emitting layer comprises light emitting devices and photosensitive devices which are distributed at intervals; the pixel circuit is connected with the light-emitting device, the first end of the photosensitive device is connected with the first end of the switch circuit and the first end of the storage capacitor respectively, the second end of the photosensitive device and the second end of the storage capacitor are used for loading constant voltage signals, the second end of the switch circuit is used for being connected with the signal acquisition circuit, and the control end of the switch circuit is used for loading control signals. In the embodiment of the disclosure, the light sensing device and the storage capacitor are integrated in the display substrate at the same time, so that the film structure can be simplified, and the ultra-thinning of the display panel can be realized.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of science and technology, display devices are widely used in people's daily life. In order to make the appearance of the display device more beautiful and fashionable, the display panel included in the display device is more and more developed to be ultra-thin. At present, most display panel all include photosensitive device to realize functions such as fingerprint identification, and photosensitive device sets up in the one side that is close to the apron usually, and sets up in the one deck alone, has so increased the complexity of the rete that display panel includes, and is unfavorable for display panel's ultra-thinness development.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

An object of the present disclosure is to provide a display panel and a display device, which can simplify a film structure of the display panel and achieve ultra-thinning of the display panel on the premise of achieving a fingerprint recognition function.

According to an aspect of the present disclosure, there is provided a display panel including:

a substrate;

the display substrate is positioned on one side of the substrate and is provided with a storage capacitor;

the display substrate comprises a driving layer and a light-emitting layer, the driving layer is positioned between the substrate and the light-emitting layer, the driving layer comprises pixel circuits and switch circuits which are distributed at intervals, and the light-emitting layer comprises light-emitting devices and light-sensing devices which are distributed at intervals;

the pixel circuit with emitting device connects, the first end of sensitization device respectively with switching circuit's first end storage capacitor's first end is connected, the second end of sensitization device storage capacitor's second end all is used for loading constant voltage signal, switching circuit's second end is used for being connected with signal acquisition circuit, switching circuit's control end is used for loading control signal.

According to any one of the display panels disclosed by the disclosure, the light-emitting layer comprises a first polar plate and a second polar plate which are sequentially distributed along a direction departing from the substrate;

the first polar plate the second polar plate is in there is the coincidence zone in orthographic projection on the substrate, first polar plate with the second polar plate constitutes first storage capacitor, first polar plate with switching circuit's first end is connected, the second polar plate is used for the loading constant voltage signal.

According to any one of the display panels disclosed by the present disclosure, the upper surface of the first polar plate is of a curved surface structure.

According to the display panel, the surface of the driving layer, which faces away from the substrate, is provided with a protrusion, and an orthographic projection of the first polar plate on the substrate and an orthographic projection of the protrusion on the substrate are overlapped.

According to any one of the display panels of the present disclosure, the driving layer includes a third plate;

the orthographic projections of the third polar plate and the first polar plate on the substrate are overlapped, the third polar plate and the first polar plate form a second storage capacitor, and the third polar plate is connected with the second polar plate.

According to any one of the display panels of the present disclosure, the driving layer includes a fourth plate;

the fourth polar plate is located on one side, close to the substrate, of the third polar plate, an overlapping area exists between orthographic projections of the fourth polar plate and the third polar plate on the substrate, the fourth polar plate and the third polar plate form a third storage capacitor, and the third polar plate is connected with the first end of the switch circuit.

According to any one of the display panels disclosed by the disclosure, the driving layer comprises a first polar plate and a second polar plate which are sequentially distributed along a direction departing from the substrate;

According to any one of the display panels disclosed by the disclosure, the photosensitive device comprises a first conductive electrode, a photoelectric conversion unit and a second conductive electrode which are sequentially distributed along a direction departing from the substrate;

the first conductive electrode is connected with a first end of the switch circuit, and the second conductive electrode is used for loading the constant voltage signal.

According to any one of the display panels in the present disclosure, the switch circuit includes a switch transistor, a first pole of the switch transistor is connected to the first end of the light sensing device, a second pole of the switch transistor is used for being connected to the signal collecting circuit, and a gate of the switch transistor is used for loading a control signal.

According to another aspect of the present disclosure, there is provided a display device including the display panel of the above-described aspect.

The embodiment of the disclosure at least comprises the following technical effects:

in the embodiment of the disclosure, the photosensitive device and the storage capacitor are integrated in the display substrate at the same time, so that the film structure can be simplified, and the ultra-thinning of the display panel is realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 3 is a schematic structural diagram of a touch signal acquisition circuit according to an embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure.

Fig. 5 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 6 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 7 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 8 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 9 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 10 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Fig. 11 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms, such as "upper" and "lower," may be used herein to describe one element of an icon relative to another, such terms are used herein for convenience only, e.g., with reference to the orientation of the example illustrated in the drawings. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting as to the number of their objects.

A transistor is an element including at least three terminals, i.e., a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to a region through which current mainly flows.

The first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities, or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

The disclosed embodiments provide a display panel. As shown in fig. 1 or 2, the display panel includes: the display substrate comprises a substrate BP and a display substrate, wherein the display substrate comprises a driving layer DR and a light emitting layer EE; the driving layer DR and the light emitting layer EE are located at one side of the substrate BP, and the driving layer DR is located between the substrate BP and the light emitting layer EE. The driving layer DR includes a plurality of pixel circuits, and the light emitting layer EE includes a plurality of light emitting devices; the plurality of pixel circuits correspond to the plurality of light emitting devices one to one, and one pixel circuit is connected with the corresponding light emitting device. The corresponding light-emitting device can be controlled to emit light under the driving of the pixel circuit, so that the display of pictures on the display panel is realized.

The material of the substrate BP may be an inorganic material or an organic material. For example, in some embodiments, the material of the substrate BP may be a glass material such as soda-lime glass (so-lime glass), quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or the like. In other embodiments, the material of the substrate BP may be Polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

Alternatively, the substrate BP may be a composite of multiple layers of materials, in addition to a single layer of material. For example, in some embodiments, the substrate BP includes a base film layer, a pressure sensitive adhesive layer, a first polyimide layer, and a second polyimide layer, which are sequentially stacked.

In the embodiments of the present disclosure, one pixel circuit may include a plurality of transistors and pixel capacitors.

The transistor can be a thin film transistor, and the thin film transistor can be selected from a top gate type thin film transistor, a bottom gate type thin film transistor or a double-gate type thin film transistor; the pixel capacitor can be a bipolar plate capacitor or a three-plate capacitor. The material of the active layer of the thin film transistor can be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

It is to be understood that one pixel circuit includes a plurality of transistors, and the type between any two transistors may be the same or different. For example, in some embodiments, part of the transistors in one pixel circuit may be N-type transistors and part of the transistors may be P-type transistors. Still illustratively, in other embodiments, the material of the active layer of a part of the transistors in one pixel circuit may be a low temperature polysilicon semiconductor material, and the material of the active layer of a part of the transistors may be a metal oxide semiconductor material.

In the embodiment of the present disclosure, as shown in fig. 1 or fig. 2, the driving layer DR includes an insulating buffer layer BUF, a transistor layer, an interlayer electrolyte layer ILD, a source-drain metal layer SD, and a planarization layer PLN, which are sequentially distributed in a direction away from the substrate BP, and the transistor layer includes a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga stacked between the insulating buffer layer BUF and the interlayer electrolyte layer ILD. The position relation of each film layer included in the transistor layer can be determined according to the film layer structure of the thin film transistor.

The materials of the insulating buffer layer BUF, the gate insulating layer GI, and the interlayer electrolyte layer ILD may be inorganic insulating materials such as silicon oxide and silicon nitride. The insulating buffer layer BUF may be a single layer of an inorganic material or a plurality of stacked layers of inorganic materials.

The source-drain metal layer SD may be used to form metal traces such as a power line, a data line, a connection line, a constant voltage signal line, and a signal collection line, and may also be used to form an electrode plate of a pixel capacitor. The driving layer DR may include a source/drain metal layer SD, or may include two or three source/drain metal layers SD. Illustratively, the driving layer DR includes a first source-drain metal layer SD1 and a second source-drain metal layer SD2.

The planar layer PLN is provided with a plurality of through holes, the pixel circuits, the through holes and the light-emitting devices are in one-to-one correspondence, and the first electrode of each light-emitting device is connected with the corresponding pixel circuit through the corresponding through hole.

In some embodiments, the transistor layer includes a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga sequentially stacked in a direction away from the substrate BP, and the thin film transistor thus formed is a top gate thin film transistor. In other embodiments, the transistor layer includes a gate metal layer Ga, a gate insulating layer GI, and a semiconductor layer ACT, which are sequentially stacked in a direction away from the substrate BP, so that the thin film transistor formed in this way is a bottom gate thin film transistor.

The semiconductor layer ACT may be used to form an active portion of each transistor included in the pixel circuit, each active portion including a channel region and two connection portions (i.e., a source and a drain) located at both sides of the channel region. The channel region may retain semiconductor properties, with the semiconductor material corresponding to both connections being partially or fully conductive. The material of the semiconductor layer ACT may be an amorphous silicon semiconductor material, a low temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, or other types of semiconductor materials. The transistor layer may include one semiconductor layer ACT or may include two semiconductor layers ACT. Illustratively, the transistor layer includes a semiconductor layer ACT, and is a metal oxide semiconductor layer ACT.

The gate metal layer Ga may be used to form a gate metal layer Ga routing such as a control signal line and a scan line, and may also be used to form another electrode plate of the pixel capacitor. The transistor layer may include a gate metal layer Ga, and may also include two or three gate metal layers Ga. Illustratively, as shown in fig. 1, the transistor layer includes a first gate metal layer Ga1 and a second gate metal layer Ga2, and the transistor included in the pixel circuit may be a double-gate thin film transistor.

In combination with the structure of the semiconductor layer ACT and the structure of the gate metal layer Ga, when the transistor layer includes multiple gate metal layers Ga and/or multiple semiconductor layers ACT, the gate insulating layer GI in the transistor layer may be increased or decreased adaptively. Illustratively, as shown in fig. 1, the transistor layer includes a first gate metal layer Ga1, a first gate insulating layer GI1, a metal oxide semiconductor layer ACT, a second gate insulating layer GI2, and a second gate metal layer Ga2, which are sequentially stacked on the substrate BP.

Optionally, the driving layer DR further includes a passivation layer disposed between the source/drain metal layer SD and the planarization layer PLN, so as to protect the source/drain metal layer SD through the passivation layer. Optionally, the driving layer DR further includes a shielding layer disposed between the insulating buffer layer BUF and the substrate BP, and the shielding layer may overlap at least a portion of a channel region of the transistor to shield light irradiated to the transistor, so that electrical characteristics of the transistor are stable.

In the embodiments of the present disclosure, the light emitting device may be an organic electroluminescent diode, a micro light emitting diode, a quantum dot-organic electroluminescent diode, a quantum dot light emitting diode, or other types of light emitting devices.

For example, in some embodiments, the light emitting device is an organic electroluminescent diode, and the display panel is an OLED display panel. As follows, taking the light emitting device as an organic electroluminescent diode as an example, a possible structure of the light emitting device is exemplarily described.

As shown in fig. 1 or fig. 2, the light-emitting layer EE includes a first electrode layer AN, a pixel defining layer PDL, a functional layer EL, and a second electrode layer COM, which are sequentially stacked in a direction away from the substrate BP.

The first electrode layer AN includes a plurality of first electrodes, the pixel definition layer PDL has first pixel openings corresponding to the plurality of first electrodes one to one, and the first electrodes include exposed regions exposed at the corresponding first pixel openings; the functional layer EL comprises a plurality of light emitting units which are in one-to-one correspondence with the first pixel openings, and the light emitting units are positioned in the corresponding first pixel openings; the second electrode layer COM is provided as a whole layer, and the second electrode of the plurality of light emitting devices shares the second electrode layer COM.

The exposed area of the first electrode forms a luminous area of the corresponding luminous device, and the first electrode is connected with the corresponding pixel circuit through the through hole of the flat layer PLN. A light emitting unit may include an organic electroluminescent material layer, and may further include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

In some embodiments, as shown in fig. 1 or 2, the display panel may further include a thin film encapsulation layer TFT. The thin film encapsulation layer TFT is disposed on a side of the light emitting layer EE facing away from the substrate BP, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block external moisture and oxygen, and prevent the organic light-emitting functional layer EL from being invaded by the moisture and the oxygen to cause material degradation. The organic encapsulation layer is positioned between two adjacent inorganic encapsulation layers so as to achieve planarization and reduce stress between the inorganic encapsulation layers.

The display panel has a display area and a peripheral area located at the periphery of the display area, an edge of the inorganic encapsulation layer may be located at the peripheral area, and an edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Illustratively, the thin film encapsulation layer TFT includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially stacked on a side of the light emitting layer EE facing away from the substrate BP.

In some embodiments, the display panel may further include a touch functional layer, where the touch functional layer is disposed on a side of the thin film encapsulation layer TFT, which is away from the substrate BP, and is used to implement touch operation of the display panel.

In some embodiments, as shown in fig. 1 or fig. 2, the display panel further includes a light guide layer BM, the light guide layer BM is disposed on a side of the touch functional layer away from the substrate BP, and the light guide layer BM includes first light channels BM1 corresponding to the plurality of light emitting devices one to one, so that light emitted by each light emitting device can pass through the corresponding first light channel BM1.

In the related art, in order to realize functions of fingerprint identification, touch control, and the like of the display panel, a photosensitive device OPD is usually disposed on a side of the light emitting layer EE departing from the substrate BP, which causes complexity of a film structure of the display panel, and increases the thickness of the display panel, thereby making it difficult to realize ultra-thinning of the display panel.

In the embodiment of the present disclosure, as shown in fig. 1 or fig. 2, the display substrate is formed with a storage capacitor C, the driving layer DR included in the display substrate includes a switching circuit DR1, and the light emitting layer EE included in the display substrate includes a photosensitive device OPD. In this way, the light sensing device OPD and the storage capacitor C are integrated in the display substrate at the same time, so that the film structure can be simplified, and the ultra-thinning of the display panel can be realized.

The switch circuit DR1 and the pixel circuit are distributed at intervals, and the photosensitive device OPD and the light emitting device are distributed at intervals. The display area of the display panel may have a light sensing device OPD and a switching circuit DR1 corresponding thereto; of course, the display area of the display panel may also have a plurality of light sensing devices OPD and a plurality of switching circuits DR1 corresponding to the plurality of light sensing devices OPD one to one.

In the case of including a plurality of photosensitive devices OPD, one photosensitive device OPD may be disposed in an area corresponding to a group of light emitting devices (red light emitting device, green light emitting device, blue light emitting device), or a plurality of photosensitive devices OPD may be disposed in an area corresponding to a group of light emitting devices (red light emitting device, green light emitting device, blue light emitting device), as long as the light emission of the light emitting devices is not affected, which is not limited in the embodiments of the present disclosure.

Wherein, as shown in fig. 1 or fig. 2, the light guide layer BM further includes the second light path BM2 corresponding to the photosensitive device OPD, so to the light that emitting device sent out after the sheltering reflection of sheltering from the thing, can be detected by photosensitive device OPD along second light path BM2, it is that photosensitive device OPD can detect the reverberation through second light path BM2 promptly.

As shown in fig. 1, fig. 2, and fig. 3, a first end of the photosensitive device OPD is connected to a first end of the switch circuit DR1 and a first end of the storage capacitor C, a second end of the photosensitive device OPD and a second end of the storage capacitor C are both used for loading a constant voltage signal, a second end of the switch circuit DR1 is used for being connected to the signal acquisition circuit, and a control end of the switch circuit DR1 is used for loading a control signal.

The switch circuit DR1 is used for switching between on and off according to a loaded control signal, the switch circuit DR1 is controlled to be on based on a first control signal, and at the moment, the photosensitive device OPD, the storage capacitor C, the switch circuit DR1 and the signal acquisition circuit are in a conducting state, so that resetting of the photosensitive device OPD and the storage capacitor C is achieved; then, the switching circuit DR1 is controlled to be disconnected based on a second control signal, at the moment, the photosensitive device OPD, the storage capacitor C and the switching circuit DR1 are all in a disconnected state, at the moment, the photosensitive device OPD can detect reflected light after shielding reflection and generate an electron-hole pair so as to store electric quantity in the storage capacitor C and realize a photoelectric conversion function; and then the switch circuit DR1 is controlled to be switched on based on a third control signal, and at the moment, the photosensitive device OPD, the storage capacitor C, the switch circuit DR1 and the signal acquisition circuit are in a conducting state, so that the acquisition of the electric quantity stored in the storage capacitor C is realized through the signal acquisition circuit, and fingerprint identification and the like are carried out according to the acquired electric quantity.

In some embodiments, as shown in fig. 1 or fig. 2, the photo sensing device OPD includes a first conductive electrode OPD1, a photoelectric conversion unit OPD2, and a second conductive electrode OPD3 sequentially arranged in a direction away from the substrate BP, the first conductive electrode OPD1 is connected to the first end of the switching circuit DR1, and the second conductive electrode OPD3 is used for loading a constant voltage signal.

The first electrode layer AN includes the first electrode and the first conductive electrode OPD1, and the second electrode of the light emitting device and the second conductive electrode OPD3 of the photo sensor OPD share the second electrode layer COM. In this way, in combination with the second conductive electrode OPD3 of the photo sensor OPD, the constant voltage signal applied to the second conductive electrode OPD3 (second terminal) of the photo sensor OPD is the VSS voltage signal.

As for the photoelectric conversion unit OPD2, the photoelectric conversion unit OPD2 may be a PIN photoelectric conversion unit, or an OPD organic photoelectric conversion unit. When the photoelectric conversion unit OPD2 is an OPD organic photoelectric conversion unit, since the organic photoelectric conversion material included in the photoelectric conversion unit OPD2 is different from the electroluminescent material included in the light emitting unit, the photoelectric conversion unit OPD2 and the light emitting unit can be separately manufactured in the same layer; if the photoelectric conversion unit OPD2 includes one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer, the photoelectric conversion unit OPD2 and the light emitting unit may share one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer.

In some embodiments, as shown in fig. 3, the switching circuit DR1 includes a switching transistor TS, a first pole of the switching transistor TS is connected to the first end of the light sensing device OPD, a second pole of the switching transistor TS is used for connecting to the signal collecting circuit, and a gate of the switching transistor TS is used for loading the control signal.

In connection with the above explanation of the driving layer DR, for example, as shown in fig. 1, the driving layer DR includes a first gate metal layer Ga1, a first gate insulating layer GI1, a semiconductor layer ACT, a second gate insulating layer GI2, a second gate metal layer Ga2, an interlayer electrolyte layer ILD, a source-drain metal layer SD, and a planar layer PLN, which are sequentially stacked in a direction away from the substrate BP, the semiconductor layer ACT includes an active portion of the switching transistor TS, the active portion has a channel region and connection portions located at both sides of the channel region, the first gate metal layer Ga1 includes a first control signal line, the second gate metal layer Ga2 includes a second control signal line, and the first control signal line and the second control signal line both have an overlapping region with the channel region of the switching transistor TS in the thickness direction of the substrate BP; the source-drain metal layer SD includes a signal collection line, a first connection line and a second connection line, both ends of the first connection line are connected to one connection portion of the switching transistor TS and the signal collection line, respectively, and both ends of the second connection line are connected to the other connection portion of the switching transistor TS and the first end of the photo detector OPD, respectively.

In the embodiment of the present disclosure, the storage capacitor C may be formed in the light emitting layer EE, or may be formed in the driving layer DR, or of course, one plate may be formed in the light emitting layer EE, and the other plate may be formed in the driving layer DR. The number of the storage capacitors C may be one, or may be multiple, and for example, the storage capacitors C1, C2, and the like are included.

In some embodiments, as shown in fig. 4 or 5, the light emitting layer EE includes a first plate Cs1 and a second plate Cs2 sequentially distributed in a direction away from the substrate BP; the orthographic projections of the first polar plate Cs1 and the second polar plate Cs2 on the substrate BP have overlapping regions, the first polar plate Cs1 and the second polar plate Cs2 form a first storage capacitor C1, the first polar plate Cs1 is connected with the first end of the switch circuit DR1, and the second polar plate Cs2 is used for loading a constant voltage signal.

In combination with the above-mentioned structure of the photosensitive device OPD, for example, the first electrode layer Cs1 may be fabricated in the same layer as the first conductive electrode OPD1 of the photosensitive device OPD, the second electrode layer Cs2 may be fabricated in the same layer as the second conductive electrode OPD3 of the photosensitive device OPD, and in combination with the above-mentioned structure of the light emitting layer EE, the first electrode layer AN includes the first electrode, the first conductive electrode OPD1, and the first electrode layer Cs1, and the second electrode of the light emitting device, the second conductive electrode OPD3 of the photosensitive device OPD, and the second electrode layer Cs2 of the first storage capacitor C1 share the second electrode layer COM. In this way, in combination with the second conductive electrode OPD3 of the photo sensing device OPD and the second plate Cs2 of the first storage capacitor C1, the constant voltage signal applied to the second conductive electrode OPD3 (the second end of the photo sensing device OPD) and the second plate Cs2 (the second end of the first storage capacitor C1) is the VSS voltage signal.

The first polar plate Cs1 of the first storage capacitor C1 may be integrally disposed with the first conductive electrode OPD1 of the photosensitive device OPD, and may be disposed at intervals, so long as the first polar plate Cs1 of the storage capacitor C and the first conductive electrode OPD1 of the photosensitive device OPD are connected to the first end of the switch circuit DR1 at the same time, which is not limited in the embodiment of the present disclosure.

In other embodiments, as shown in fig. 6 or fig. 7, the driving layer DR includes a first plate Cs1 and a second plate Cs2 sequentially distributed in a direction away from the substrate BP; the orthographic projections of the first polar plate Cs1 and the second polar plate Cs2 on the substrate BP have a superposition region, the first polar plate Cs1 and the second polar plate Cs2 form a first storage capacitor C1, the first polar plate Cs1 is connected with the first end of the switch circuit DR1, and the second polar plate Cs2 is used for loading a constant voltage signal.

The second plate Cs2 of the first storage capacitor C1 is connected to a constant voltage signal line of the source-drain metal layer SD or connected to the second electrode layer COM of the light-emitting layer EE.

In combination with the structure of the driving layer DR, the driving layer DR includes, for example, a semiconductor layer ACT, a gate metal layer Ga, and a source drain metal layer SD, wherein the first polar plate Cs1 is formed on the gate metal layer Ga, and the second polar plate Cs2 is formed on the source drain metal layer SD. Of course, as shown in fig. 6, the first polar plate Cs1 may be formed on the source-drain metal layer SD, and the second polar plate Cs2 may be formed on the gate metal layer Ga, which is not limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, when the switch circuit DR1 is in the off state to store the electric quantity through the storage capacitor C, the larger the electric capacity of the storage capacitor C is, the larger the electric quantity that the storage capacitor C can store is, and the larger the stored electric quantity is, the larger the signal-to-noise ratio is, so that the detection accuracy can be improved.

In this way, in order to increase the storable capacitance of the storage capacitor C, on the one hand, the structure of the first polar plate Cs1 and the second polar plate Cs2 included in the first storage capacitor C1 can be adjusted; on the other hand, the number of the storage capacitors C can be adjusted, that is, the display substrate is further formed with a second storage capacitor C2, a third storage capacitor C3, and the like, and the plurality of storage capacitors C are connected in parallel.

Next, the first plate Cs1 and the second plate Cs2 of the first storage capacitor C1 are formed on the light emitting layer EE, which will be explained in detail. In the case where the first plate Cs1 and the second plate Cs2 of the first storage capacitor C1 are both formed in the driving layer DR, reference is made to the case where the first plate Cs1 and the second plate Cs2 are both formed in the light emitting layer EE.

In some embodiments, as shown in fig. 4, the upper surface of the first polar plate Cs1 (the surface facing the second polar plate Cs 2) has a curved surface structure. Illustratively, the upper surface of the first plate Cs1 is a wavy structure, a spherical structure, or a cambered surface structure. Of course, the upper surface of the first polar plate Cs1 may have other structures besides the curved surface structure, such as a tooth surface-like structure.

Thus, by adjusting the structure of the upper surface of the first plate Cs1, the area of the first plate Cs1 is increased, and combining with the calculation formula of the capacitor, the capacitance of the capacitor is proportional to the plate area of the capacitor, so that the capacitance of the storage capacitor C is increased when the area of the first plate Cs1 is increased.

The adjustment of the overall structure of the first polar plate Cs1 can be realized by adjusting the surface of the driving layer DR deviating from the substrate BP, and the adjustment of the surface of the first polar plate Cs1 facing the second polar plate Cs2 can be further realized. In combination with the structure of the driving layer DR, for example, the surface of the flat layer PLN facing away from the substrate BP may be set to be a wavy structure, so that the first polar plate Cs1 formed on the flat layer PLN is a wavy structure, and the surface of the first polar plate Cs1 facing the second polar plate Cs2 is a wavy structure.

In other embodiments, as shown in fig. 5, the surface of the driving layer DR facing away from the substrate BP has a projection DR2, and there is an overlapping region between the orthographic projection of the first plate Cs1 on the substrate BP and the orthographic projection of the projection DR2 on the substrate BP.

Thus, by arranging the protruding DR2 structure on the surface of the driving layer DR, the distance between the first polar plate Cs1 and the second polar plate Cs2 is shortened, and the capacitance of the capacitor is inversely proportional to the distance between the polar plates by combining the calculation formula of the capacitor, so that the capacitance of the storage capacitor C is increased under the condition that the first polar plate Cs1 and the second polar plate Cs2 are shortened. In addition, the surface area of the first plate Cs1 can be increased by the provision of the projections DR2, so that the capacitance of the storage capacitor C is increased in the case where the area of the first plate Cs1 is increased in combination with the above.

In combination with the structure of the driving layer DR, the protrusion DR2 on the driving layer DR may be a protrusion DR2 formed on the surface of the flat layer PLN hundreds substrate BP. The protrusion DR2 on the driving layer DR may be a block-shaped protrusion, a plurality of columnar protrusions, or a plurality of strip-shaped protrusions extending along the first direction and distributed along the second direction, which is not limited in the embodiment of the present disclosure. The first direction and the second direction may be two intersecting directions, for example, the first direction is a row direction, and the second direction is a column direction.

In still other embodiments, as shown in fig. 8 or fig. 9, the driving layer DR includes a third plate Cs3, the orthographic projections of the third plate Cs3 and the first plate Cs1 on the substrate BP have an overlapping region, the third plate Cs3 and the first plate Cs1 form a second storage capacitor C2, and the third plate Cs3 is connected to the second plate Cs 2. In this way, by increasing the number of the storage capacitors C, i.e., by increasing the second storage capacitor C2 connected in parallel with the first storage capacitor C1, the storable capacitance is increased, and the signal-to-noise ratio is increased.

The third plate Cs3 may be formed on any metal layer included in the driving layer DR. In combination with the structure of the driving layer DR, as shown in fig. 8, the driving layer DR includes a semiconductor layer ACT, a gate insulating layer GI, a gate metal layer Ga, an interlayer dielectric layer ILD, and a source/drain metal layer SD, and the third plate Cs3 may be disposed on any one of the gate metal layer Ga, the semiconductor layer ACT, and the source/drain metal layer SD. Exemplarily, as shown in fig. 8, the third plate Cs3 is provided with a source-drain metal layer SD.

Further, as shown in fig. 10 or fig. 11, the driving layer DR includes a fourth polar plate Cs4, the fourth polar plate Cs4 is located on one side of the third polar plate Cs3 close to the substrate BP, the orthographic projections of the fourth polar plate Cs4 and the third polar plate Cs3 on the substrate BP have an overlapping region, the fourth polar plate Cs4 and the third polar plate Cs3 form a third storage capacitor C3, and the third polar plate Cs3 is connected to the first end of the switching circuit DR1. In this way, by further increasing the number of the storage capacitors C, i.e., by increasing the second storage capacitor C2 and the third storage capacitor C3 in parallel with the first storage capacitor C1, the storable capacitance is increased, and the signal-to-noise ratio is increased.

The fourth polar plate Cs4 may be formed on any metal layer included in the driving layer DR, and the metal layer where the fourth polar plate Cs4 is located on one side of the metal layer where the third polar plate Cs3 is located, which is close to the substrate BP, or may be located on one side of the metal layer where the third polar plate Cs3 is located, which is far from the substrate BP. In combination with the structure of the driving layer DR, as shown in fig. 10, the driving layer DR includes a semiconductor layer ACT, a gate insulating layer GI, a gate metal layer Ga, an interlayer dielectric layer ILD, and a source drain metal layer SD, a third plate Cs3 is disposed on any one of the gate metal layer Ga, the semiconductor layer ACT, and the source drain metal layer SD, and a fourth plate Cs4 is disposed on any one of the remaining two layers of the semiconductor layer ACT, the gate metal layer Ga, and the source drain metal layer SD. Illustratively, as shown in fig. 10, the third plate Cs3 is disposed on the source-drain metal layer SD, and the fourth plate Cs4 is disposed on the gate metal layer Ga.

The embodiment of the present disclosure provides a display device including the display panel described in the above embodiment. With the display panel according to the above embodiment, when the fingerprint recognition function is ensured, the display panel is thinned, and the display device is further thinned.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising:

a substrate;

the display substrate comprises a driving layer and a light emitting layer, the driving layer is located between the substrate and the light emitting layer, the driving layer comprises pixel circuits and switch circuits which are distributed at intervals, and the light emitting layer comprises light emitting devices and photosensitive devices which are distributed at intervals;

the pixel circuit with light emitting device connects, the first end of sensitization device respectively with switch circuit's first end storage capacitor's first end is connected, the second end of sensitization device storage capacitor's second end all is used for loading constant voltage signal, switch circuit's second end is used for being connected with signal acquisition circuit, switch circuit's control end is used for loading control signal.

2. The display panel of claim 1, wherein the light emitting layer comprises a first plate and a second plate sequentially distributed in a direction away from the substrate;

3. The display panel of claim 2, wherein the upper surface of the first plate has a curved structure.

4. The display panel of claim 2, wherein a surface of the driving layer facing away from the substrate has a protrusion, and an orthographic projection of the first plate on the substrate and an orthographic projection of the protrusion on the substrate have an overlapping region.

5. The display panel according to any one of claims 2 to 4, wherein the driving layer includes a third plate;

6. The display panel of claim 5, wherein the driving layer comprises a fourth plate;

the fourth polar plate is located on one side, close to the substrate, of the third polar plate, the orthographic projections of the fourth polar plate and the third polar plate on the substrate are overlapped, the fourth polar plate and the third polar plate form a third storage capacitor, and the third polar plate is connected with the first end of the switch circuit.

7. The display panel of claim 1, wherein the driving layer comprises a first plate and a second plate sequentially distributed in a direction away from the substrate;

8. The display panel according to any one of claims 1 to 4 and 6 to 7, wherein the photosensitive device includes a first conductive electrode, a photoelectric conversion unit, and a second conductive electrode which are sequentially arranged in a direction away from the substrate;

9. The display panel according to any one of claims 1 to 4 and 6 to 7, wherein the switching circuit comprises a switching transistor, a first pole of the switching transistor is connected to the first terminal of the light sensing device, a second pole of the switching transistor is used for being connected to the signal acquisition circuit, and a gate of the switching transistor is used for loading a control signal.

10. A display device comprising the display panel according to any one of claims 1 to 9.