CN218830444U

CN218830444U - CMOS image sensor tester

Info

Publication number: CN218830444U
Application number: CN202222068469.1U
Authority: CN
Inventors: 王林旺; 谭湘; 王志浩; 操文武
Original assignee: Shenzhen Cztek Co ltd
Current assignee: Shenzhen Cztek Co ltd
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2023-04-07
Anticipated expiration: 2032-08-05

Abstract

The utility model provides a CMOS image sensor test machine relates to the semiconductor test field. Wherein, this CMOS image sensor test machine includes: the main control chip comprises an image testing module and an electrical property testing module, is connected with the switch matrix unit and is used for transmitting a testing signal sent by an upper computer to the switch matrix unit; the switch matrix unit is used for respectively conducting the image test module or the electrical property test module with different pins of a Device Under Test (DUT) according to the test signal, and the pins comprise a power supply pin and an image output pin; the switch matrix unit can control the power supply pin and/or the image output pin of the DUT and the electrical property test module and/or the image test module. The utility model provides an use ATE equipment and external image acquisition card combination mode to test problem with high costs to CMOS image sensor among the correlation technique.

Description

CMOS image sensor tester

Technical Field

The utility model relates to a semiconductor test field, particularly, the utility model relates to a CMOS image sensor test machine.

Background

The CMOS image sensor has a series of advantages of high integration level, low power consumption, low cost and the like, and becomes a core sensing device for Internet and Internet of things. The testing process is not required in the design, production, sealing and testing of the CMOS image sensor, and even the testing process can determine the quality of the CMOS image sensor.

At present, the CMOS image sensor is mainly tested in a combined mode of ATE equipment and an external image acquisition card, the scheme is that the ATE equipment is used for electrically testing the CMOS image sensor, and then the external image acquisition card is used for carrying out image testing on the CMOS image sensor. However, the scheme has the defects of high test cost caused by low integration level, large occupied area, unfavorable production line deployment, low troubleshooting efficiency caused by complex system and the like.

Therefore, the test cost for the CMOS image sensor is high by using a combination mode of ATE equipment and an external image acquisition card, and the problem which needs to be solved urgently is solved.

SUMMERY OF THE UTILITY MODEL

The utility model discloses each embodiment provides a CMOS image sensor test machine, can solve and use ATE equipment and external image acquisition card combination mode to carry out the problem that test cost is high to CMOS image sensor among the correlation technique. The technical scheme is as follows:

according to an aspect of the embodiment of the present invention, a CMOS image sensor testing machine, CMOS image sensor testing machine (CIS testing machine) includes: the device comprises a main control chip, a measuring unit and a switch matrix unit, wherein the main control chip comprises an image testing module and an electrical property testing module, is connected with the switch matrix unit and is used for transmitting a testing signal sent by an upper computer to the switch matrix unit; the switch matrix unit is used for respectively conducting the image test module or the electrical property test module with different pins of a Device Under Test (DUT) according to the test signal, and the pins comprise a power supply pin and an image output pin; when the electrical property testing module is respectively conducted with the power supply pin and/or the image output pin of the DUT through the switch matrix unit, the main control chip controls the measuring unit to collect the electrical property parameters of the DUT and transmits the electrical property parameters to the electrical property testing module for electrical property testing; when the image test module is conducted with an image output pin of the DUT through the switch matrix unit, the main control chip controls the image test module to collect and perform image test on image data output by the DUT.

In an exemplary embodiment, the switch matrix unit includes a high-speed signal switch group and a low-speed signal switch group, wherein the high-speed signal switch group includes a first input terminal, a first switch portion and a second switch portion, the first input terminal is connected to the main control chip, the first switch portion is used for conducting the measurement unit and an image output pin of the DUT, and the second switch portion is used for conducting the image test module and the image output pin of the DUT; the low-speed signal switch group comprises a second input end and a third switch part, the second input end is connected with the main control chip, and the third switch part is used for conducting the measurement unit and a power supply pin of the DUT.

In an exemplary embodiment, the pins further comprise input-output pins; the low-speed signal switch group further comprises a fourth switch part and a fifth switch part, the fourth switch part is used for conducting the measurement unit and the input and output pins of the DUT, and the fifth switch part is used for conducting the main control chip and the input and output pins of the DUT.

In an exemplary embodiment, the CIS tester further includes a power output unit; the low-speed signal switch group further comprises a sixth switch part and a seventh switch part, wherein the sixth switch part is used for transmitting the power supply voltage output by the power supply output unit to the DUT when the power supply output unit is conducted with the power supply pin of the DUT; the seventh switch portion is configured to transmit an operating voltage of the DUT to the power output unit when the power output unit is turned on with the power pin of the DUT.

In an exemplary embodiment, the CIS tester further includes a power output unit, wherein the power output unit includes a voltage output module for providing a power supply voltage to the DUT as an operating voltage of the DUT.

In an exemplary embodiment, the power output unit further includes a voltage acquisition module and a voltage compensation module, wherein the voltage acquisition module is connected to the voltage compensation module and is configured to acquire an operating voltage of the DUT and transmit the operating voltage to the voltage compensation module; the voltage compensation module is connected with the voltage output module and used for calculating a difference value between the power supply voltage and the working voltage and feeding the difference value back to the voltage output module, so that the voltage output module adjusts the power supply voltage according to the difference value.

In an exemplary embodiment, the power output unit further includes an overcurrent protection module, and the overcurrent protection module includes a current input terminal and a control output terminal, wherein the current input terminal is connected to an intermediate node between the voltage output module and the switch matrix unit, and is configured to collect a current between the voltage output module and the switch matrix unit; the control output end is connected with the voltage output module and used for sending a turn-off control signal to the voltage output module when the current between the voltage output module and the switch matrix unit exceeds a current threshold value, so that the voltage output module stops providing the power supply voltage for the DUT according to the turn-off control signal.

In an exemplary embodiment, the measurement unit includes an analog-to-digital conversion (ADC) module for transmitting the electrical parameters of the DUT after analog-to-digital conversion to the electrical test module for electrical testing.

In an exemplary embodiment, the measurement unit further includes a filtering module connected to the ADC module, and configured to transmit the filtered electrical parameter of the DUT to the ADC module for analog-to-digital conversion.

In an exemplary embodiment, the CIS tester of the above embodiment further includes a power supply module for supplying power to the CIS tester.

The utility model provides a beneficial effect that technical scheme brought is:

in the technical scheme, the utility model provides a CIS test machine has assembled image acquisition function and electrical property test function, just can accomplish electrical property test and image test to CMOS image sensor on a CIS test machine, has solved and has used ATE equipment and external image acquisition card combination mode to carry out the problem with high costs to CMOS image sensor among the correlation technique.

Drawings

In order to more clearly illustrate the technical solution in the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly described below.

FIG. 1 is a block diagram illustrating the structure of a CIS tester according to an exemplary embodiment;

FIG. 2 is a schematic diagram of a CIS tester shown in accordance with an exemplary embodiment;

FIG. 3 is a flow chart illustrating a CIS tester electrically testing a CMOS image sensor in accordance with an exemplary embodiment;

fig. 4 is a flowchart illustrating a CIS tester performing image testing on a CMOS image sensor according to an exemplary embodiment.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention, and should not be construed as limiting the present invention.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The following are descriptions and explanations of several terms related to the present invention:

CMOS, also known as Complementary Metal Oxide Semiconductor (CMOS), is known in English as CMOS.

CIS is called CMOS Image Sensor in English, and COMS is a Chinese meaning Image Sensor.

A CIS tester, i.e., a CMOS image sensor tester, is used to test a CMOS image sensor.

DUT, the English full name is Device Under Test, and chinese meaning is the Device Under Test, also can regard as the Device Under Test, for example, the utility model discloses well Device Under Test can be the CMOS image sensor who carries out the Test.

ATE Equipment is called Automatic Test Equipment in English, is an integrated circuit Automatic tester in Chinese meaning, can also be regarded as an ATE tester, and can be used for testing a CMOS image sensor.

Electrical parameters including, but not limited to, voltage, current, resistivity, power, etc. of the circuit.

As mentioned above, the CMOS image sensor has a series of advantages such as high integration level, high standardization level, low power consumption, low cost, small size, and randomly readable image information, and with the rapid development in the fields of internet of things, artificial intelligence, and automotive electronics, the CMOS image sensor has become a core sensor device for the application of mobile internet and internet of things. The CMOS image sensor needs to be tested to ensure good working performance of the CMOS image sensor shipped from the factory. At present, an ATE (automatic test equipment) equipment and an image acquisition card are usually used for testing the CMOS image sensor, but the scheme has the defects of high testing cost caused by low integration level, large occupied area, inconvenience for production line deployment, low troubleshooting efficiency caused by complex system and the like.

From the above, it is known that the testing cost of the CMOS image sensor using the ATE device and the external image capture card combination is high, which becomes an urgent problem to be solved.

Therefore, the utility model provides a CIS test machine can realize CMOS image sensor's electrical property test and image test simultaneously, is favorable to reduce cost, has solved and has used ATE equipment and external image acquisition card compound mode to carry out the problem that test cost is high to CMOS image sensor among the correlation technique.

In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Fig. 1 is a block diagram of a CIS tester according to an exemplary embodiment.

In this embodiment, the CIS tester 100 includes a main control chip 110, a measurement unit 130, and at least one switch matrix unit 150.

The main control chip 110 includes an electrical test module 111 and an image test module 113, is connected to the switch matrix unit 150, and is configured to transmit a test signal to the switch matrix unit; the DUT 200 includes a plurality of pins including a power supply pin and an image output pin; the switch matrix unit 150 is used for respectively connecting the image test module 113 or the electrical property test module 111 with different pins of the DUT 200 according to the test signal. In a possible implementation manner, the main control chip may be an ARM chip or an FPGA chip, which is not limited herein.

Specifically, the main control chip 110 sends test signals to the connected switch matrix unit 150, where the test signals include electrical test signals and image test signals; if the test signal sent by the main control chip 110 is an electrical test signal, the switch matrix unit 150 is conducted with the power pin of the DUT 200, the measurement unit 130 obtains the electrical parameter of the DUT 200 and sends the electrical parameter to the electrical test module 111, and the electrical test module 111 performs an electrical test on the electrical parameter after receiving the electrical parameter to obtain an electrical test result.

If the test signal sent by the main control chip 110 is an image test signal, the image test module 113 is conducted with an image output pin of the DUT 200 through the switch matrix unit 150, the DUT 200 sends image data to the image test module 113, and the image test module 113 performs an image test on the image data after receiving the image data, so as to obtain an image test result.

By the technical scheme, the electrical property test and the image test of the DUT are simultaneously completed through the CIS tester, and the problem of high test cost of the CMOS image sensor in a combined mode of an ATE tester and an external image acquisition card is solved.

Fig. 2 is a schematic diagram of a CIS tester according to an exemplary embodiment.

In this embodiment, the CIS tester includes a main control chip, a power output unit, a measurement unit, and a high-speed signal switch group and a low-speed signal switch group connected to at least one DUT. The power output unit comprises an overcurrent protection module, a voltage output module, a voltage compensation module and a voltage acquisition module; the measuring unit comprises an ADC module and a filtering module; the DUT includes a plurality of pins, specifically a power supply pin, an Input Output (IO) pin, and an image output pin.

In one possible implementation, the high-speed signal refers to an image test signal, the image test signal has a high transmission rate, a small signal amplitude and poor interference resistance, in order to reduce signal attenuation caused by switching, a high-speed signal switch group must be used as the high-speed signal, and a high-speed signal switch in the high-speed signal switch group may be a high-speed switch diode, a high-power solid-state optical fiber optical switch, or the like; the low-speed signal refers to an electrical test signal, the electrical test signal is a low-speed signal, the characteristic of the electrical test signal is opposite to that of the high-speed signal, a low-speed signal switch group is used, and the low-speed signal switch in the low-speed signal switch group can be a self-locking switch, a self-resetting switch and the like.

The low-speed signal switch group comprises a second input end, a third switch part, a sixth switch part and a seventh switch part.

The second input end is connected with the main control chip, and the third switch part is used for conducting the measurement unit and a power supply pin of the DUT; a sixth switching part for transmitting the power supply voltage outputted from the power supply output unit to the DUT when the power supply output unit is conducted with the power supply pin of the DUT; and the seventh switch part is used for transmitting the working voltage of the DUT to the power supply output unit when the power supply output unit is conducted with the power supply pin of the DUT.

The main control chip sends an electrical test signal to the low-speed signal switch group through the second input end, and the low-speed signal switch group responds to the electrical test signal and conducts the third switch part and the sixth switch part. Then, the voltage output module outputs the power supply voltage to the DUT, and the DUT starts to work; the measuring unit collects the electrical parameters of the DUT power supply pin, interference is eliminated through the filtering module, analog-to-digital conversion processing is carried out through the ADC module, and the converted electrical parameters are transmitted to the main control chip for electrical testing.

The utility model provides a CIS test machine can realize the voltage compensation function, particularly, main control chip sends electrical property test signal to low-speed signal switch group through the second input, and low-speed signal switch group switches on sixth switch portion and seventh switch portion in response to this electrical property test signal. Then, the voltage output module outputs the power supply voltage to the DUT, and the DUT starts to work; and after the voltage acquisition module acquires the working voltage of the power pin of the DUT, transmitting the working voltage to the voltage compensation module and the measurement unit. After the voltage compensation module obtains the working voltage, calculating a difference value between the power supply voltage and the working voltage, feeding the difference value back to the voltage output module, and adjusting the power supply voltage output to the DUT by the voltage output module according to the difference value; after the measuring unit obtains the working voltage transmitted by the voltage acquisition module, the interference is eliminated through the filtering module, the ADC module is used for carrying out analog-to-digital conversion processing, and the converted working voltage is transmitted to the main control chip for electrical test.

When the seventh switching part is in an on state, the third switching part may be turned off. Through the turned-on seventh switch part, the voltage acquisition module acquires the working voltage of the DUT and transmits the working voltage to the connected measurement unit, the measurement unit eliminates the interference of the working voltage through the filter module, the working voltage is subjected to analog-to-digital conversion through the ADC module, and the converted working voltage is transmitted to the main control chip for electrical property test

The utility model provides a CIS test can realize overcurrent protection, particularly, main control chip sends electrical property test signal to low-speed signal switch group through the second input, and low-speed signal switch group switches on sixth switch portion in response to this electrical property test signal. Then, the voltage output module outputs the power supply voltage to the DUT, and the DUT starts to work; the overcurrent protection module of the power output unit comprises a current input end and a control output end, the current input end is connected to a middle node of the voltage output module and the switch matrix unit, working current between the voltage output module and the low-speed signal switch group is collected, if the working current value exceeds a preset current threshold value, the overcurrent protection module sends a turn-off control signal to the voltage output module, and the voltage output module responds to the turn-off control signal and stops providing power voltage for a DUT.

The low-speed signal switch group further comprises a fourth switch part and a fifth switch part, wherein the fourth switch part is used for conducting the measurement unit and an IO pin of the DUT, and the fifth switch part is used for conducting the main control chip and the IO pin of the DUT.

The main control chip sends an electrical test signal to the low-speed signal switch group, and the low-speed signal switch group responds to the electrical test signal to conduct the fourth switch part and the fifth switch part. Then, the main control chip configures the IO pin of the DUT; and the measurement unit collects IO working voltage of each IO pin of the DUT, interference is eliminated through the filter module, analog-to-digital conversion processing is carried out through the ADC module, and the converted multiple groups of IO working voltage are transmitted to the main control chip for electrical test.

The main control chip configures an IO pin of the DUT, including but not limited to configuring an input state, an output state, an initial state, and the like of the IO pin, for example: and configuring the IO pin of the DUT to be in a pull-up output state, or configuring the initial state of the IO pin of the DUT to be in a low level, or configuring the IO pin of the DUT to be in a push-pull output state.

The high-speed signal switch group comprises a first input end, a first switch part and a second switch part. The first input end is connected with the main control chip, the first switching part is used for conducting the measurement unit and an image output pin of the DUT, and the second switching part is used for conducting the image test module and the image output pin of the DUT.

The main control chip sends an image test signal to the high-speed signal switch group through the first input end, and the high-speed signal switch group responds to the image test signal and conducts the first switch part and the second switch part. Then, an image output pin of the DUT outputs image data to a main control chip, and the main control chip carries out image test on the image data after acquiring the image data; the measurement unit collects electrical parameters of an image output pin of the DUT, interference is eliminated through the filter module, analog-to-digital conversion processing is carried out through the ADC module, and the electrical parameters are transmitted to the main control chip for electrical testing.

The CIS tester further includes a power supply module for supplying power to each module/unit in the CIS tester, for example: and providing working power supply for a measuring module of the CIS tester. The power supply module may be an AC/DC module power supply, or may be a DC/DC module power supply, which is not limited herein.

Referring to fig. 3, a flowchart of a CIS tester for electrical testing of a CMOS image sensor is shown, and the flowchart is applied to the CIS tester 100 shown in fig. 1.

The CIS tester initiates an electrical test to electrically test the DUT, as shown in steps 301-305. Firstly, carrying out open-short circuit test on a circuit of a DUT (device under test), and detecting whether the circuit of the DUT is open or short; if the circuit of the DUT is open or short-circuited, the DUT does not pass the electrical test, the CIS tester generates an electrical test report and sends the report to a user, and the electrical test is finished; if there is no open or short circuit in the circuit of the DUT, the CIS tester powers the DUT, step 307 is executed.

As shown in steps 307 to 311, after the CIS tester supplies power to the DUT, the CIS tester measures a voltage value and/or a current value of each pin of the DUT, and determines whether a circuit of the DUT normally operates based on the voltage value and/or the current value, if the circuit of the DUT fails, the DUT fails the electrical test, and the CIS tester generates an electrical test report and sends the report to a user, and ends the electrical test; if the circuit of the DUT is working properly and the DUT passes the electrical test, the CIS tester will also generate an electrical test report to the user, and step 313 to step 315 are performed, so that the CIS tester can perform an image test on the DUT, and the flowchart of the image test may be specifically shown in fig. 4 and will not be described herein.

It should be noted that there are various ways to determine whether the circuit of the DUT is working normally, for example: and acquiring an interval range of the working voltage and/or the working current of each pin of the DUT, wherein the interval range comprises an upper limit value and a lower limit value, if the measured voltage value and/or the measured current value of each pin of the DUT is not in the interval range, a circuit of the DUT has a fault, and otherwise, if the measured voltage value and/or the measured current value of each pin of the DUT is in the interval range, the circuit of the DUT works normally.

As described in conjunction with fig. 1, steps 301 to 315 may be performed by the CIS testing machine 100. The measurement unit 130 measures an electrical parameter of the DUT 200, the measurement unit 130 obtains the electrical parameter of the DUT 200 and transmits the electrical parameter to the electrical test module 111, and the electrical test module 111 analyzes the electrical parameter to determine whether the DUT 200 passes the electrical test. For example: the measurement unit 130 measures a current value of the DUT 200 as 0, and transmits the current value to the electrical testing module 111, and the electrical testing module 111 determines that an open circuit exists in the circuit of the DUT 200 according to the current value, thereby determining that the DUT 200 fails the electrical test.

Fig. 4 is a flowchart illustrating the CIS testing machine performing image testing on the CMOS image sensor.

As shown in steps 401 to 413, the CIS tester starts image testing and image testing is performed on the DUT. Firstly, sending an image test signal to a DUT (device under test), if a CIS (contact information System) tester does not receive a response signal fed back by the DUT, the DUT fails the image test, the CIS tester generates an image test report and sends the image test report to a user, and the image test is finished; if the DUT responds to the image test signal and sends a response signal to the CIS tester, the CIS tester starts to collect image data output by the DUT. If the CIS tester cannot acquire image data output by the DUT, the DUT fails the image test, the CIS tester generates an image test report and sends the image test report to a user, and the image test is ended; and if the image data output by the DUT can be collected, carrying out image detection on the obtained image data. For example, the image detection includes an image scene test, if the image scene test cannot be completed, the step 403 is executed again until the DUT completes the image scene test, the CIS tester generates an image test report and sends the image test report to the user, and the image test is ended.

It should be noted that there are various ways to perform the image scene test, for example: and carrying out image scene reduction on the acquired image data to obtain a test image scene, carrying out similarity contrast detection on the test image scene and the original image scene, and if the similarity of the test image scene and the original image scene reaches 90%, passing the image scene test.

It is further noted that the number of times of executing steps 403 to 411 is not limited, and this operation is performed to eliminate accidental influences, which may cause the CIS tester not to completely collect the image data sent by the DUT, so that the image scene test cannot be completed; or the image data output by the DUT is partially lost, so that the image scene test of the image data acquired by the CIS tester cannot be completed. However, if the image scene test cannot be successfully completed by performing steps 403 to 411 for a plurality of times, it means that the image scene test cannot be completed because the image function of the DUT fails instead of the image scene test cannot be completed due to accidental influences. As can be seen from the above, the maximum execution time needs to be set, and if the execution times of steps 403 to 411 are equal to or greater than the maximum execution time, the image scene test cannot be completed, the DUT fails the image test, the CIS tester generates an image test report and sends the image test report to the user, and the image test is ended.

As described in conjunction with fig. 1, steps 401 through 413 may be performed by the CIS tester 100. The main control chip 110 transmits an image test signal to enable the DUT 200 to output image data, and the image test module 113 collects the image data output by the DUT 200 and performs an image test according to the image data, thereby determining whether the DUT 200 passes the image test. For example, the image test module 113 may not collect image data output by the DUT 200 or may not receive a response signal generated by the DUT, and thus may determine that the DUT 200 fails the image test.

The above technical scheme, the utility model, realized accomplishing CMOS image sensor's electrical property test and image test on a CIS test machine, solved and need use ATE equipment and external image acquisition card combination mode to carry out the problem that test cost is high to CMOS image sensor among the correlation technique.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless otherwise indicated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The above are only some embodiments of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A CMOS image sensor tester, characterized in that the CMOS image sensor CIS tester comprises: a main control chip, a measuring unit and a switch matrix unit, wherein,

the main control chip comprises an image test module and an electrical property test module, is connected with the switch matrix unit and is used for transmitting a test signal sent by an upper computer to the switch matrix unit;

the switch matrix unit is used for respectively conducting the image test module or the electrical property test module with different pins of a device to be tested (DUT) according to the test signal, and the pins comprise a power supply pin and an image output pin;

when the electrical property testing module is respectively conducted with the power supply pin and/or the image output pin of the DUT through the switch matrix unit, the main control chip controls the measuring unit to collect the electrical property parameters of the DUT and transmits the electrical property parameters to the electrical property testing module for electrical property testing;

when the image test module is conducted with an image output pin of the DUT through the switch matrix unit, the main control chip controls the image test module to collect and test image data output by the DUT.

2. The CMOS image sensor tester of claim 1, wherein the switch matrix unit comprises a high-speed signal switch bank and a low-speed signal switch bank, wherein,

the high-speed signal switch group comprises a first input end, a first switch part and a second switch part, the first input end is connected with the main control chip, the first switch part is used for conducting the measurement unit and an image output pin of the DUT, and the second switch part is used for conducting the image test module and the image output pin of the DUT;

the low-speed signal switch group comprises a second input end and a third switch part, the second input end is connected with the main control chip, and the third switch part is used for conducting the measurement unit and a power supply pin of the DUT.

3. The CMOS image sensor tester of claim 2, wherein the pins further comprise input-output pins;

the low-speed signal switch group further comprises a fourth switch part and a fifth switch part, the fourth switch part is used for conducting the measurement unit and the input and output pins of the DUT, and the fifth switch part is used for conducting the main control chip and the input and output pins of the DUT.

4. The CMOS image sensor tester of claim 3, wherein the CIS tester further comprises a power output unit;

the low-speed signal switch group further comprises a sixth switch part and a seventh switch part, wherein the sixth switch part is used for transmitting the power supply voltage output by the power supply output unit to the DUT when the power supply output unit is conducted with the power supply pin of the DUT;

the seventh switch portion is configured to transmit an operating voltage of the DUT to the power output unit when the power output unit is turned on with the power pin of the DUT.

5. The CMOS image sensor tester of claim 1, wherein the CIS tester further comprises a power output unit, wherein,

the power supply output unit comprises a voltage output module for providing a power supply voltage to the DUT as an operating voltage of the DUT.

6. The CMOS image sensor tester of claim 5, wherein the power output unit further comprises a voltage acquisition module and a voltage compensation module, wherein,

the voltage acquisition module is connected with the voltage compensation module and is used for acquiring the working voltage of the DUT and transmitting the working voltage to the voltage compensation module;

the voltage compensation module is connected with the voltage output module and used for calculating a difference value between the power supply voltage and the working voltage and feeding the difference value back to the voltage output module, so that the voltage output module adjusts the power supply voltage according to the difference value.

7. The CMOS image sensor tester of claim 5, wherein the power supply output unit further comprises an over-current protection module comprising a current input and a control output, wherein,

the current input end is connected with a middle node of the voltage output module and the switch matrix unit and is used for collecting current between the voltage output module and the switch matrix unit;

the control output end is connected with the voltage output module and used for sending a turn-off control signal to the voltage output module when the current between the voltage output module and the switch matrix unit exceeds a current threshold value, so that the voltage output module stops providing the power supply voltage for the DUT according to the turn-off control signal.

8. The CMOS image sensor tester as claimed in claim 1, wherein the measurement unit comprises an analog-to-digital conversion (ADC) module for transmitting the electrical parameters of the DUT subjected to the analog-to-digital conversion to the electrical test module for electrical testing.

9. The CMOS image sensor tester as claimed in claim 8, wherein the measurement unit further comprises a filter module connected to the ADC module for transmitting the electrical parameters filtered by the DUT to the ADC module for analog-to-digital conversion.

10. The CMOS image sensor tester of any one of claims 1 to 9, wherein the CIS tester further comprises a power supply module to supply power to the CIS tester.