CN218827142U - OLED display panel - Google Patents
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- CN218827142U CN218827142U CN202222962476.6U CN202222962476U CN218827142U CN 218827142 U CN218827142 U CN 218827142U CN 202222962476 U CN202222962476 U CN 202222962476U CN 218827142 U CN218827142 U CN 218827142U
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Abstract
The utility model provides a OLED display panel. The OLED display panel is provided with a first shading part, a second shading part, a third shading part and a fourth shading part, wherein the first shading part, the second shading part and the fourth shading part can block light on the side surface of the display area from irradiating the GOA area, and the third shading part can block light on the top of the display area from irradiating the GOA area. Therefore, the shielding effect on light emitted by the light-emitting device in the display area is good, the influence on the first thin film transistor in the GOA area under illumination can be weakened, the negative bias probability of the threshold voltage of the first thin film transistor is further reduced, and the electrical performance of the first thin film transistor is improved; and the problem that sharp corners at the lap joint of a composite layer consisting of the ITO layer, the Ag layer and the ITO layer are easy to break in the manufacturing process can be avoided.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a OLED display panel.
Background
An AMOLED (Active-matrix organic light-emitting diode) is used as a new generation Display technology, and has a higher contrast ratio, a faster response speed, and a wider viewing angle compared to a conventional LCD (Liquid Crystal Display), and is widely applied to the fields of smart phones and TVs (televisions).
The driving of the AMOLED display panel line scanning lines is realized by an external integrated circuit, the external integrated circuit can control the gradual opening of all levels of line scanning lines, and an Array substrate line driving (GOA) technology is adopted, so that the driving circuit of the line scanning lines can be integrated on a substrate of the display panel, the number of external chips (IC) can be reduced, the frame of the display panel can be narrower and thinner, the integration level of the display panel is higher, the product form is richer, the process flow is simpler, and future products are more competitive; the equipment cost can be reduced, the module yield is improved, and the IC cost is saved.
Indium Gallium Zinc Oxide (IGZO) has high mobility and good device stability, and is currently widely used in an indium gallium zinc oxide GOA (IGZO-GOA) circuit. The IGZO-GOA circuit can be applied to the design of LCD display panels and OLED (organic light-emitting diode) display panels.
Currently, an IGZO-TFT (indium gallium zinc oxide thin film transistor) process is generally adopted for the AMOLED, however, the IGZO-TFT has poor stability, process fluctuation can affect the uniformity of the threshold voltage Vth of the whole panel in the IGZO-TFT process, and particularly, after the IGZO-TFT is illuminated, the threshold voltage of the TFT is easily negatively biased.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an OLED display panel can avoid illumination to the influence of the first thin film transistor in the GOA district to can avoid the composite bed that comprises ITO layer, ag layer and ITO layer in the processing procedure in the easy fracture problem of closed angle of overlap joint.
In order to achieve the above object, the present invention provides an OLED display panel, which includes a substrate, a buffer layer disposed on the substrate, a first active layer disposed on the buffer layer, a first gate insulating layer disposed on the first active layer, a first gate disposed on the first gate insulating layer, an interlayer dielectric layer covering the buffer layer, the first active layer, the first gate insulating layer, and the first gate, a first drain electrode, a first source electrode, and a first shading portion disposed on the interlayer dielectric layer at intervals, a second shading portion penetrating through the buffer layer and the interlayer dielectric layer and connecting the substrate and the first shading portion, a passivation layer covering the interlayer dielectric layer, the first drain electrode, the first source electrode, and the first shading portion, a flat layer disposed on the passivation layer, a third shading portion and an anode disposed on the flat layer, a fourth shading portion penetrating through the passivation layer and the flat layer and connecting the first shading portion and the third shading portion, and a pixel defining layer covering the flat layer, the third shading portion, and the anode;
the substrate comprises a display area and a GOA area positioned on one side of the display area; the first drain electrode and the first source electrode are respectively positioned at two sides of the first grid electrode and are respectively connected with two ends of the first active layer through via holes penetrating through the interlayer dielectric layer; the first drain electrode, the first source electrode, the first active layer and the first grid electrode form a first thin film transistor, and the first thin film transistor is positioned in the GOA area;
the pixel defining layer defines an opening area in the display area, and the anode electrode is positioned in the opening area; a light emitting function layer positioned on the anode and a cathode positioned on the light emitting function layer are also arranged in the opening area, and the anode, the light emitting function layer and the cathode form a light emitting device; the first shading part, the second shading part, the third shading part and the fourth shading part are all positioned between the first thin film transistor and the light-emitting device.
At least one first groove is formed in the buffer layer and the interlayer dielectric layer, and the second shading part is arranged in the first groove;
the passivation layer and the flat layer are provided with at least one second groove, and the fourth shading part is arranged in the second groove.
The number of the first grooves is two, and the number of the second grooves is two.
The material of the first active layer is IGZO.
The OLED display panel further comprises a second active layer arranged on the buffer layer, a second grid insulating layer arranged on the second active layer, a second grid arranged on the second grid insulating layer, and a second drain electrode and a second source electrode which are arranged on the interlayer dielectric layer at intervals; the interlayer dielectric layer also covers the second active layer, the second grid electrode insulating layer and the second grid electrode, and the passivation layer also covers the second drain electrode and the second source electrode;
the second drain electrode and the second source electrode are respectively positioned at two sides of the second grid electrode and are respectively connected with two ends of the second active layer through via holes penetrating through the interlayer dielectric layer; the second drain electrode, the second source electrode, the second active layer and the second grid electrode form a second thin film transistor, and the second thin film transistor is positioned in the display area;
one of the second drain electrode and the second source electrode is connected with the anode through a through hole penetrating through the passivation layer and the flat layer, and the second thin film transistor is used for driving the light-emitting device to emit light.
The anode is connected with the second source electrode.
The OLED display panel further comprises a first shading layer and a second shading layer which are arranged between the substrate and the buffer layer and are respectively positioned below the first active layer and the second active layer.
The first drain electrode, the first source electrode, the second drain electrode, the second source electrode, the first shading part and the second shading part are integrally formed, and the first shading part and the second shading part are integrated.
The third shading part, the fourth shading part and the anode are integrally formed and are a whole.
The third shading part, the fourth shading part and the anode are all composite layers formed by ITO layers, ag layers and ITO layers.
The utility model has the advantages that: the utility model discloses a OLED display panel is equipped with first shading portion, second shading portion, third shading portion and fourth shading portion, and wherein first shading portion, second shading portion and fourth shading portion can block the light that the display area side shines to the GOA district, and the light that third shading portion can block the display area top shines to the GOA district. Therefore, the shielding effect on light emitted by the light-emitting device in the display area is good, the influence on the first thin film transistor in the GOA area under illumination can be weakened, the negative bias probability of the threshold voltage of the first thin film transistor is further reduced, and the electrical performance of the first thin film transistor is improved; and the problem that sharp corners at the lap joint of a composite layer consisting of the ITO layer, the Ag layer and the ITO layer are easy to break in the manufacturing process can be avoided.
Drawings
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the present invention and accompanying drawings, which are provided for the purpose of illustration and description and are not intended to limit the present invention.
In the drawings, there is shown in the drawings,
fig. 1 is a schematic structural diagram of an OLED display panel according to the present invention;
fig. 2 is a performance test chart of a first thin film transistor of an OLED display panel according to an embodiment of the present invention;
fig. 3 is a performance test chart of the first thin film transistor of the OLED display panel corresponding to the comparative example.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides an OLED display panel, including a substrate 1, a buffer layer 11 disposed on the substrate 1, a first active layer 61 disposed on the buffer layer 11, a first gate insulating layer 62 disposed on the first active layer 61, a first gate 63 disposed on the first gate insulating layer 62, an interlayer dielectric layer 12 covering the buffer layer 11, the first active layer 61, the first gate insulating layer 62, and the first gate 63, first drain electrodes 64, first source electrodes 65, and first light-shielding portions 51 disposed on the interlayer dielectric layer 12 at intervals, a second light-shielding portion 52 penetrating the buffer layer 11 and the interlayer dielectric layer 12 and connecting the substrate 1 and the first light-shielding portion 51, a passivation layer 13 covering the interlayer dielectric layer 12, the first drain electrodes 64, the first source electrodes 65, and the first light-shielding portions 51, a flat layer 14 disposed on the passivation layer 13, a third light-shielding portion 53 and an anode 21 disposed on the flat layer 14, a fourth light-shielding portion 54 penetrating the passivation layer 13 and the flat layer 14 and connecting the first light-shielding portion 51 and the third light-shielding portion 53, and a third light-shielding portion 14 and an anode light-shielding portion 21 covering the flat pixel defining a flat pixel 15.
The substrate 1 includes a display area AA and a GOA area BB located at one side of the display area AA.
The first drain electrode 64 and the first source electrode 65 are respectively located at two sides of the first gate electrode 63 and are respectively connected with two ends of the first active layer 61 through via holes penetrating through the interlayer dielectric layer 12; the first drain electrode 64, the first source electrode 65, the first active layer 61 and the first gate electrode 63 form a first thin film transistor 6, and the first thin film transistor 6 is located in the GOA region BB.
The pixel defining layer 15 defines an opening area 151 in the display area AA, and the anode electrode 21 is positioned in the opening area 151. A light-emitting functional layer 22 positioned on the anode 21 and a cathode 23 positioned on the light-emitting functional layer 22 are further disposed in the opening region 151, and the anode 21, the light-emitting functional layer 22 and the cathode 23 constitute the light-emitting device 2. The first light shielding portion 51, the second light shielding portion 52, the third light shielding portion 53, and the fourth light shielding portion 54 are located between the first thin film transistor 6 and the light emitting device 2.
Specifically, at least one first trench 10A is disposed in the buffer layer 11 and the interlayer dielectric layer 12, and the second light-shielding portion 52 is disposed in the first trench 10A. In this embodiment, the number of the first grooves 10A is two.
The passivation layer 13 and the planarization layer 14 have at least one second trench 10B, and the fourth light-shielding portion 54 is disposed in the second trench 10B. In this embodiment, the number of the second grooves 10B is two.
The OLED display panel further includes a second active layer 31 disposed on the buffer layer 11, a second gate insulating layer 32 disposed on the second active layer 31, a second gate electrode 33 disposed on the second gate insulating layer 32, and a second drain electrode 34 and a second source electrode 35 disposed on the interlayer dielectric layer 12 at an interval. The interlayer dielectric layer 12 further covers the second active layer 31, the second gate insulating layer 32, and the second gate 33, and the passivation layer 13 further covers the second drain electrode 34 and the second source electrode 35.
The second drain 34 and the second source 35 are respectively located at two sides of the second gate 33, and are respectively connected with two ends of the second active layer 31 through via holes penetrating through the interlayer dielectric layer 12; the second drain electrode 34, the second source electrode 35, the second active layer 31 and the second gate electrode 33 constitute a second thin film transistor 3. The second thin film transistor 3 is located in the display area AA.
One of the second drain electrode 34 and the second source electrode 35 is connected to the anode electrode 21 through a via hole penetrating the passivation layer 13 and the planarization layer 14, and the second thin film transistor 3 is used to drive the light emitting device 2 to emit light. In this embodiment, the anode 21 is connected to the second source 35.
Specifically, the OLED display panel further includes a first light shielding layer 102 and a second light shielding layer 101 disposed between the substrate 1 and the buffer layer 11 and respectively located under the first active layer 61 and the second active layer 31.
The material of the first active layer 61 may be amorphous silicon, or may also be a metal oxide, such as IGZO. In the present embodiment, the material of the first active layer 61 is IGZO.
Specifically, the first drain 64, the first source 65, the second drain 34, the second source 35, the first light-shielding portion 51, and the second light-shielding portion 52 are integrally formed, that is, the first drain 64, the first source 65, the second drain 34, the second source 35, the first light-shielding portion 51, and the second light-shielding portion 52 are manufactured by the same process, and the materials thereof are the same. The above arrangement enables the first light-shielding portion 51 and the second light-shielding portion 52 to be formed in the manufacturing process of the first drain 64, the first source 65, the second drain 34, and the second source 35, that is, the first light-shielding portion 51 and the second light-shielding portion 52 are formed on the basis of the original process, and the number of masks is not increased, so that the process cost is not additionally increased. In this embodiment, the first light-shielding portion 51 and the second light-shielding portion 52 are integrated.
Specifically, the third light-shielding portion 53, the fourth light-shielding portion 54 and the anode 21 are integrally formed, that is, the third light-shielding portion 53, the fourth light-shielding portion 54 and the anode 21 are manufactured by the same process, and the materials thereof are the same. The above arrangement enables the third light-shielding portion 53 and the fourth light-shielding portion 54 to be formed in the manufacturing process of the anode 21, that is, the third light-shielding portion 53 and the fourth light-shielding portion 54 are formed based on the original process, and the number of masks is not increased, so that the process cost is not increased. In this embodiment, the third light-shielding portion 53, the fourth light-shielding portion 54, and the anode 21 are integrated.
Specifically, the third light-shielding portion 53, the fourth light-shielding portion 54 and the anode 21 are made of the same opaque material. Alternatively, the third light-shielding portion 53, the fourth light-shielding portion 54 and the anode 21 are all composite layers formed by ITO (indium tin oxide) layers, ag layers and ITO layers, and can have a good shielding effect on light.
Specifically, the first drain 64, the first source 65, the second drain 34, the second source 35, the first light-shielding portion 51, and the second light-shielding portion 52 are all made of opaque metal, which can perform both the conductive function and the good shielding function for light.
Specifically, the OLED display panel is an AMOLED display panel.
It should be noted that, referring to the existing process, the thicknesses of the buffer layer 11 and the interlayer dielectric layer 12 are both 400nm, the thickness of the passivation layer 13 is 200nm, the thickness of the planarization layer 14 is 1500nm, the thicknesses of the first drain electrode 64, the first source electrode 65, the second drain electrode 34 and the second source electrode 35 are all 350nm, and the thickness of the anode 21 is 150nm, so if the first light-shielding portion 51, the second light-shielding portion 52, the third light-shielding portion 53 and the fourth light-shielding portion 54 are all an integral body and directly extend to the substrate 1 through the holes of the planarization layer 14, the passivation layer 13, the interlayer dielectric layer 12 and the buffer layer 11, due to the fact that there are many holes, the composite layer formed by the ITO layer, the Ag layer and the ITO layer is prone to break at the tapper angle (sharp corner) at the lap joint, resulting in the process problem. Therefore, in the present invention, the first light-shielding portion 51 and the second light-shielding portion 52 form a whole, and the third light-shielding portion 53 and the fourth light-shielding portion 54 form another whole, during the manufacturing process, firstly, in the patterning process of the first drain 64, the first source 65, the second drain 34 and the second source 35, in the region between the first thin film transistor 6 and the second thin film transistor 3, the buffer layer 11 and the interlayer dielectric layer 12 are patterned to form a groove (not shown), and the grooves in the buffer layer 11 and the interlayer dielectric layer 12 are communicated with each other to form a first trench 10A (two first trenches 10A are shown in the figure, and the number of the first trenches 10A is set to two, so that the shielding effect of the second light-shielding portion 52 on light can be further improved, and the electrical performance of the first thin film transistor 6 can be improved), and an opaque metal layer is deposited at the same time, so as to form the first drain 64, the first source 65, the second drain 34, the second source 35, the first source 51 and the second light-shielding portion 52; next, in the patterning process of the anode 21, in the area between the first thin film crystal 6 and the light emitting device 2, the passivation layer 13 and the planarization layer 14 are patterned correspondingly to form a groove (not shown), and the grooves in the passivation layer 13 and the planarization layer 14 are communicated with each other to form a second groove 10B (two second grooves 10B are shown in the figure, and the number of the second grooves 10B is set to two, so that the light shielding effect of the fourth light shielding portion 54 can be further improved, and thus the electrical performance of the first thin film transistor 6 can be improved), so that a composite layer composed of an ITO layer, an Ag layer, and an ITO layer is deposited simultaneously to form the third light shielding portion 53, the fourth light shielding portion 54, and the anode 21. That is, the first and second light-shielding portions 51 and 52 are patterned in advance to reduce the hole depth and avoid the process problem.
The utility model discloses a set up first shading portion, second shading portion, third shading portion and fourth shading portion to block the light irradiation in display area to the GOA district, particularly, first shading portion, second shading portion and fourth shading portion can block the light irradiation in the GOA district of display area side, and the light irradiation in the GOA district of third shading portion can block the top in the display area. Because the first thin film transistor in the GOA area is unstable under the illumination condition, if the light of the display area is directed to the GOA area, the threshold voltage of the first thin film transistor in the GOA area is highly susceptible to negative bias, thereby greatly reducing the electrical performance of the first thin film transistor. Therefore, the utility model discloses a set up first shading portion, second shading portion, third shading portion and fourth shading portion, can have good effect of shielding to the light that light emitting device sent to can weaken the influence that first thin film transistor in the GOA district received under the illumination, and then reduce the negative bias probability of first thin film transistor's threshold voltage.
Referring to fig. 2 and 3, the present invention provides the above embodiment and a comparative example corresponding to the embodiment, and the negative bias of the threshold voltage of the first thin film transistor 6 in the embodiment and the comparative example is measured. The OLED display panel provided by the comparative example is different from the OLED display panel provided by the above embodiment in that: the OLED display panel of the comparative example does not have the first light-shielding portion 51, the second light-shielding portion 52, the third light-shielding portion 53, and the fourth light-shielding portion 54.
Specifically, in the examples and comparative examples, the initial value of the threshold voltage of the first thin film transistor 6 on the side close to the display region in the GOA region was set to 1V. When the OLED display panel was lit for 100h, ids of the first thin film transistor 6 was measured as a function of Vgs at a constant Vds in each of the example and the comparative example. Wherein Vds is the voltage difference between the drain and the source; ids is the current through the drain and source; vgs is the voltage difference between the gate and the drain.
With the first thin film transistor 6 of the embodiment, as shown in fig. 2, when Vds is 0.1V and 10.1V, vgs is about 0V, and the threshold voltage of the first thin film transistor 6 is 0V at this time, that is, the first thin film transistor 6 does not exhibit a significant negative bias phenomenon.
In contrast, for the first tft 6 of the comparative example, as shown in fig. 3, when Vds is 0.1V, vgs is about-3V, and the negative bias value of the threshold voltage of the first tft 6 is-3V, that is, the first tft 6 exhibits a significant negative bias phenomenon.
Therefore, the utility model discloses a set up first shading portion 51, second shading portion 52, third shading portion 53 and fourth shading portion 54 in OLED display panel, can play good shielding effect to the side light that light-emitting device 2 produced in the display area AA and ambient light to avoid first thin-film transistor 6's threshold voltage to take place negative bias phenomenon in GOA district BB, improved first thin-film transistor 6's electrical property.
To sum up, the utility model provides a pair of OLED display panel is equipped with first shading portion, second shading portion, third shading portion and fourth shading portion, and wherein first shading portion, second shading portion and fourth shading portion can block the light that the display area side shines to the GOA district, and the light that the third shading portion can block the display area top shines to the GOA district. Therefore, the shielding effect on light emitted by the light emitting device in the display area is good, the influence on the first thin film transistor in the GOA area under illumination can be weakened, the negative bias probability of the threshold voltage of the first thin film transistor is reduced, and the electrical performance of the first thin film transistor is improved; and the problem that sharp corners at the lap joint of a composite layer consisting of the ITO layer, the Ag layer and the ITO layer are easy to break in the manufacturing process can be avoided.
As described above, various other changes and modifications may be made by those skilled in the art based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the scope of the appended claims.
Claims (10)
1. An OLED display panel, comprising a substrate (1), a buffer layer (11) disposed on the substrate (1), a first active layer (61) disposed on the buffer layer (11), a first gate insulating layer (62) disposed on the first active layer (61), a first gate electrode (63) disposed on the first gate insulating layer (62), an interlayer dielectric layer (12) covering the buffer layer (11), the first active layer (61), the first gate insulating layer (62) and the first gate electrode (63), first drain electrodes (64), first source electrodes (65) and first shading portions (51) disposed at intervals on the interlayer dielectric layer (12), a second shading portion (52) penetrating through the buffer layer (11) and the interlayer dielectric layer (12) and connecting the substrate (1) and the first gate electrode (51), a passivation layer (13) covering the interlayer dielectric layer (12), the first drain electrodes (64), the first source electrodes (65) and the first shading portions (51), a flat shading layer (14) disposed on the passivation layer (13), a third shading portion (14) and a flat anode portion (53) and a flat shading portion (54) disposed on the passivation layer (13), and a pixel defining layer (15) covering the flat layer (14), the third light-shielding portion (53), and the anode (21);
the substrate (1) comprises a display area (AA) and a GOA area (BB) positioned on one side of the display area (AA); the first drain electrode (64) and the first source electrode (65) are respectively positioned at two sides of the first grid electrode (63) and are respectively connected with two ends of the first active layer (61) through via holes penetrating through the interlayer dielectric layer (12); the first drain electrode (64), the first source electrode (65), the first active layer (61) and the first grid electrode (63) form a first thin film transistor (6), and the first thin film transistor (6) is positioned in a GOA area (BB);
the pixel defining layer (15) defines an opening area (151) at the display area (AA), and the anode electrode (21) is positioned within the opening area (151); a light-emitting functional layer (22) positioned on the anode (21) and a cathode (23) positioned on the light-emitting functional layer (22) are further arranged in the opening area (151), and the anode (21), the light-emitting functional layer (22) and the cathode (23) form a light-emitting device (2); the first light shielding part (51), the second light shielding part (52), the third light shielding part (53) and the fourth light shielding part (54) are all positioned between the first thin film transistor (6) and the light-emitting device (2).
2. The OLED display panel according to claim 1, wherein the buffer layer (11) and the interlayer dielectric layer (12) have at least a first trench (10A) therein, and the second light-shielding portion (52) is disposed in the first trench (10A);
at least one second groove (10B) is formed in the passivation layer (13) and the flat layer (14), and the fourth shading portion (54) is arranged in the second groove (10B).
3. The OLED display panel according to claim 2, wherein the number of the first grooves (10A) is two, and the number of the second grooves (10B) is two.
4. The OLED display panel according to claim 1, characterized in that the material of the first active layer (61) is IGZO.
5. The OLED display panel according to claim 1, further comprising a second active layer (31) disposed on the buffer layer (11), a second gate insulating layer (32) disposed on the second active layer (31), a second gate electrode (33) disposed on the second gate insulating layer (32), and a second drain electrode (34) and a second source electrode (35) disposed on the interlayer dielectric layer (12) at an interval; the interlayer dielectric layer (12) further covers the second active layer (31), the second gate insulating layer (32) and the second gate electrode (33), and the passivation layer (13) further covers the second drain electrode (34) and the second source electrode (35);
the second drain electrode (34) and the second source electrode (35) are respectively positioned at two sides of the second grid electrode (33) and are respectively connected with two ends of the second active layer (31) through via holes penetrating through the interlayer dielectric layer (12); the second drain electrode (34), the second source electrode (35), the second active layer (31) and the second grid electrode (33) form a second thin film transistor (3), and the second thin film transistor (3) is located in the display area (AA);
one of the second drain electrode (34) and the second source electrode (35) is connected with the anode (21) through a via hole penetrating through the passivation layer (13) and the flat layer (14), and the second thin film transistor (3) is used for driving the light-emitting device (2) to emit light.
6. The OLED display panel according to claim 5, characterized in that the anode (21) is connected to a second source (35).
7. The OLED display panel according to claim 5, further comprising a first light shielding layer (102) and a second light shielding layer (101) disposed between the substrate (1) and the buffer layer (11) and below the first active layer (61) and the second active layer (31), respectively.
8. The OLED display panel according to claim 5, wherein the first drain electrode (64), the first source electrode (65), the second drain electrode (34), the second source electrode (35), the first light shielding portion (51), and the second light shielding portion (52) are integrally formed, and the first light shielding portion (51) is integral with the second light shielding portion (52).
9. The OLED display panel according to claim 5, wherein the third light-shielding portion (53), the fourth light-shielding portion (54) and the anode (21) are integrally formed and are one piece.
10. The OLED display panel according to claim 9, wherein the third light-shielding portion (53), the fourth light-shielding portion (54), and the anode (21) are each a composite layer of an ITO layer, an Ag layer, and an ITO layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222962476.6U CN218827142U (en) | 2022-11-04 | 2022-11-04 | OLED display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222962476.6U CN218827142U (en) | 2022-11-04 | 2022-11-04 | OLED display panel |
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| CN218827142U true CN218827142U (en) | 2023-04-07 |
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| CN202222962476.6U Active CN218827142U (en) | 2022-11-04 | 2022-11-04 | OLED display panel |
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