CN218632059U - Cell and solar cell module - Google Patents

Abstract

The embodiment of the present application provides a battery sheet and a solar cell module, wherein the battery sheet includes: a silicon sheet; a plurality of busbars, the plurality of busbars are arranged on the silicon sheet at intervals; a plurality of auxiliary Gate lines, the plurality of sub-gate lines are arranged at intervals on the silicon chip, each of the sub-gate lines is connected to a main gate line, and the width of the sub-gate lines is smaller than the width of the main gate lines ; Wherein, the main grid line includes at least one first main grid line, and the contact area between the first main grid line and the silicon wafer is smaller than the orthographic projection of the first main grid line on the silicon wafer area; and/or the sub-gate line includes at least one first sub-gate line, and the contact area between the first sub-gate line and the silicon chip is smaller than that of the first sub-gate line on the silicon chip orthographic area. In the embodiment of the present application, by reducing the contact area, the shielding of the light-receiving area of the solar cell is reduced, and the photoelectric conversion efficiency is improved.

Description

Cells and Solar Modules

technical field

The present application relates to the field of solar cells, in particular to a cell sheet and a solar cell module.

Background technique

With the depletion of fossil energy in the world, the Japanese nuclear leak once again sounded the alarm on energy issues. Undoubtedly, solar photovoltaic power generation will become an important part of future electric energy, and the application of crystalline silicon solar cell modules or thin film solar panels will become more and more People will become more and more dependent on photovoltaic power generation.

However, existing solar cells suffer from low photoelectric conversion efficiency.

Utility model content

The embodiments of the present application provide a cell sheet and a solar cell assembly, which can improve the low photoelectric conversion efficiency of existing solar cells.

An embodiment of the present application provides a battery sheet, the battery sheet includes:

Silicon wafer;

A plurality of busbar lines, the plurality of busbar lines are arranged on the silicon wafer at intervals;

A plurality of sub-gate lines, the plurality of sub-gate lines are arranged on the silicon wafer at intervals, each of the sub-gate lines is connected to a main gate line, and the width of the sub-gate lines is smaller than that of the main gate line line width;

Wherein, the main grid line includes at least one first main grid line, and the contact area between the first main grid line and the silicon wafer is smaller than the orthographic projection area of the first main grid line on the silicon wafer ;and / or

The sub-gate line includes at least one first sub-gate line, and the contact area between the first sub-gate line and the silicon chip is smaller than the orthographic projection area of the first sub-gate line on the silicon chip.

Optionally, the battery sheet includes conductive glue, and the first busbar is disposed on the silicon chip through the conductive glue.

Optionally, the first main gate line includes two opposite ends, the first main gate line extends from one end of the silicon wafer to the other end of the silicon wafer, and the first main gate line At least one end protrudes from the silicon chip so as to be connected to the first main gate line of another battery chip.

Optionally, the length of the first busbar protruding from the silicon chip ranges from 5mm to 200mm.

Optionally, the first busbar includes a conductive wire and a plating layer, and the plating layer is plated on a surface of the conductive wire.

Optionally, at least one of the busbars includes a plurality of first busbars and a plurality of connecting parts, and one of the connecting parts is arranged between two adjacent first busbars, A plurality of the first busbars are connected through the plurality of connection parts, wherein the material of the connection parts is a conductive material.

Optionally, the first busbar is one or a combination of copper wires, aluminum-platinum wires, or copper-aluminum wires.

Optionally, the busbars include second busbars, the material of the second busbars is different from that of the first busbars, and the material of the second busbars is silver.

Optionally, the silicon wafer includes a front side and a back side oppositely arranged, and the battery wafer further includes:

The first gate line layer and the second gate line layer arranged on both sides of the silicon chip, each of the first gate line layer and the second gate line layer includes a plurality of the main gate lines and a plurality of the Auxiliary grid line;

a depletion layer, the depletion layer is arranged on the front side of the silicon chip and is located between the silicon chip and the first gate line layer;

a first passivation layer, the first passivation layer is disposed on the side of the depletion layer away from the silicon wafer, and is located between the depletion layer and the first gate line layer;

a second passivation layer, the second passivation layer is disposed on the back side of the silicon chip, and is located between the silicon chip and the second gate line layer;

A protection layer, the protection layer is disposed on a side of the second passivation layer away from the silicon wafer, and is located between the second passivation layer and the second gate line layer.

The embodiment of the present application also provides a solar cell assembly, the solar cell assembly includes a plurality of battery slices as described above, and the plurality of battery slices are arranged in series with each other.

The beneficial effect of the present application is that: the battery sheet provided by the embodiment of the present application includes a silicon wafer, multiple main gate lines and multiple sub-gate lines, wherein the multiple main gate lines are arranged on the silicon wafer at intervals, and the multiple sub-gate lines The lines are spaced apart from each other on the silicon chip, and the width of a secondary grid line is smaller than that of a main grid line, wherein the main grid line includes at least one first main grid line, and the contact area between the first main grid line and the silicon chip is smaller than that of the first main grid line. The orthographic projection area of a main grid line on the silicon wafer; and/or the sub grid line includes at least one first sub grid line, and the contact area between the first sub grid line and the silicon wafer is smaller than that of the first sub grid line on the silicon wafer orthographic area of . In this application, by setting the contact surface of at least one first main gate line or at least one first sub-gate line with the silicon chip to be smaller than the orthographic projection area on the silicon chip, the contact area is reduced and the The shading of the light-receiving area of the solar cell is avoided, and the photoelectric conversion efficiency is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative efforts.

For a more complete understanding of the present application and its beneficial effects, the following will be described in conjunction with the accompanying drawings. Wherein, the same reference numerals denote the same parts in the following description.

FIG. 1 is a schematic structural diagram of a battery sheet provided in an embodiment of the present application.

FIG. 2 is a schematic cross-sectional view of the battery sheet shown in FIG. 1 .

FIG. 3 is a schematic diagram of a first structure of a first busbar in the battery sheet shown in FIG. 1 .

FIG. 4 is a schematic diagram of a second structure of the first busbar in the cell shown in FIG. 1 .

FIG. 5 is a schematic diagram of another structure of busbars in the battery sheet shown in FIG. 1 .

Fig. 6 is a schematic structural diagram of a solar cell module provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present application, "plurality" means two or more, unless otherwise specifically defined.

Photovoltaic energy has developed rapidly in the past 10 years. At present, the world has a production capacity of nearly 500GW. It is becoming more and more popular because of its sustainable regeneration, no pollution, and simple installation. Currently PERC, Topcon and HJT processes are the three mainstream processes for solar cells, accounting for more than 95% of photovoltaic cells. The final screen printing process in these three processes is made by screen printing with silver paste with a silver content of about 90%, which is used to collect the current generated by the solar cell after being illuminated. Taking the 182-size HJT solar cells as an example, the consumption of silver paste is >200 mg/piece, accounting for more than 20% of the cost of solar cells.

In addition, the contact area between the grid line formed by printing silver paste and the silicon wafer is relatively large, so that the light-receiving area of the solar cell is greatly blocked, resulting in low photoelectric conversion efficiency.

Therefore, in order to solve the above problems, the present application proposes a battery sheet and a solar battery module. The present application will be further described below in conjunction with the accompanying drawings and embodiments.

Please refer to Figures 1 to 3, Figure 1 is a schematic structural view of the battery sheet provided by the embodiment of the present application, Figure 2 is a schematic cross-sectional view of the battery sheet shown in Figure 1, and Figure 3 is the first battery sheet shown in Figure 1 Schematic diagram of the first structure of the busbar. The embodiment of the present application provides a battery sheet 100, including a silicon wafer 10, a plurality of main gate lines 30 and a plurality of auxiliary gate lines 20, wherein the silicon wafer 10 includes a front side and a back side oppositely arranged, and the plurality of main gate lines 30 are connected to each other. A plurality of sub-gate lines 20 are spaced apart from each other on the front and back of the silicon wafer 10 , and the width of the sub-gate lines 20 is smaller than that of the main gate lines 30 . Wherein, the main gate line 30 includes at least one first main gate line 310, and the contact area between the first main gate line 310 and the silicon wafer 10 is smaller than the orthographic projection area of the first main gate line 310 on the silicon wafer 10; and/or The sub-gate line 20 includes at least one first sub-gate line, and the contact area between the first sub-gate line and the silicon chip 10 is smaller than the orthographic projection area of the first sub-gate line on the silicon chip 10 . In this application, the contact area between at least one first main gate line 310 or at least one first sub-gate line and the silicon wafer is smaller than the orthographic projection area on the silicon wafer, so as to reduce the contact area while ensuring electrical conductivity. The shading of the light-receiving area of the solar cell is reduced, and the photoelectric conversion efficiency is improved.

In some embodiments, the battery sheet may be such that the main grid line 30 includes at least one first main grid line 310 , and the auxiliary grid line 20 includes at least one first auxiliary grid line. In some embodiments, the battery sheet may also be such that the main grid line 30 includes at least one first main grid line 310 , and the auxiliary grid line 20 does not include the first auxiliary grid line. In some other embodiments, the battery sheet may also be that the main grid line 30 does not include the first main grid line 310, and the sub-grid line 20 includes at least one first sub-grid line, which is not specifically limited here. The situation can be set.

In some embodiments, a plurality of main gate lines 30 are arranged parallel to each other on the front and back of the silicon wafer 10, a plurality of sub-gate lines 20 are arranged in parallel to each other, and each sub-gate line 20 is arranged perpendicular to a main gate line 30. When the current is turned on, the auxiliary gate line 20 is used to collect the current and transmit it to the main gate line 30 , and the main gate line 30 transmits the current to other loads.

The battery sheet 100 includes conductive glue 80 , and the first busbar 310 is disposed on the silicon chip 10 through the conductive glue 80 .

Wherein, the busbar 30 includes at least one first busbar 310. It can be understood that the plurality of busbars 30 all include the first busbar 310, and it can also be understood that there are some busbars in the plurality of busbars 30. 30 includes a first busbar line 310 , it can also be understood that only one busbar line 30 includes the first busbar line 310 among the plurality of busbar lines 30 . Specifically, it may be set according to actual conditions, and no specific limitation is made here.

Wherein, the busbar 30 includes the first busbar 310. It can be understood that a busbar 30 is composed of the first busbar 310, and it can also be understood that a busbar 30 is composed of a first busbar 310. and other components, it can also be understood that a part of one busbar 30 is composed of the first busbar 310 .

Exemplarily, in some embodiments, at least one busbar 30 is composed of a first busbar 310, that is, the first busbar 310 is used to replace the silver paste printed in the prior art to form the busbar 30, The contact area between the first main grid line 310 and the silicon wafer 10 can be reduced, reducing the shielding of the light-receiving area of the solar cell, thereby improving the photoelectric conversion efficiency. In addition, the amount of silver paste can also be reduced to reduce costs.

Further, since the first main grid lines 310 may be oxidized in some practical applications, in order to avoid oxidation of the first main grid lines 310, at least part of the first main grid lines 310 will be plated with a layer of metal material to form The plating layer 320 is used to solve the situation that the first busbar 310 is oxidized. Specifically, referring to FIG. 3 , a first busbar 310 includes a conductive wire 311 and a plating layer 312 , and the plating layer 312 covers at least part of the conductive wire 311 . That is, at least one busbar 30 among the plurality of busbars 30 is composed of the first busbar 310 , and metal material is plated on at least part of the conductive wires 311 to form a plating layer 312 .

Wherein, on the premise of ensuring the anti-oxidation of the first busbar 310, plating metal material on at least part of the first busbar 310 can be understood as coating a part of the first busbar 310 with a metal material, for example Optionally, in some embodiments, the first busbar 310 includes a first part 3111, a second part 3112 and a third part 3113 connected to each other, and the first part 3111 and the third part 3113 are all plated with a metal material. Second part 3112 unplated metal material. For another example, please continue to refer to FIG. 4 , which is a schematic diagram of a second structure of the first busbar in the battery sheet shown in FIG. 1 . In some other embodiments, the conductive wire 311 of the first busbar 310 includes an inner surface close to the silicon chip 10 and an outer surface far away from the silicon chip 10, and the outer surface of the conductive wire 311 is plated with a metal material to form a plating layer 312. The inner surface of the conductive wire 311 is not coated with metal material. In this way, it can not only ensure that the first busbar 310 is not oxidized, but also save metal materials to reduce costs.

In some embodiments, a first busbar 310 is entirely coated with a metal material to ensure that the first busbar 310 is not oxidized.

Please continue to refer to FIG. 5 . FIG. 5 is a schematic diagram of another structure of busbars in the cell shown in FIG. 1 . In some embodiments, at least one busbar 30 includes a plurality of first busbars 310 and a plurality of connecting parts 330, the plurality of first busbars 310 are arranged at intervals, and each connecting part 330 is arranged at two Between adjacent first main gate lines 310 , two adjacent first main gate lines 310 are connected through the connecting portion 330 , and multiple first main gate lines 310 are connected through a plurality of connecting portions 330 . Through the arrangement of multiple first busbar lines 310 and multiple connecting parts 330, the length of each first busbar line 310 does not necessarily have to be the same as the length of the busbar lines 30, even if the first busbar lines 310 are shorter. It can be connected through the connecting part 330, therefore, even if the grid lines of each battery sheet 100 have different lengths, the first main grid lines 310 can also be applied, reducing the waste of the first main grid lines 310, thereby saving cost. In addition, there is no need to accurately set the length of the first busbar 310 , which reduces the difficulty of the process.

Wherein, the first busbar 310 may be one or a combination of copper wires, aluminum-platinum wires, or copper-aluminum wires. The material of the plating layer 312320 can be one or a combination of nickel, silver, tin, zinc and the like. The plating layer 312 disposed on the first busbar 310 may be one or a combination of nickel-plated copper wires, silver-plated copper wires, tin-plated copper wires or galvanized copper wires. Specifically, it may be set according to actual conditions, and no specific limitation is made here.

In some embodiments, the thickness of the first busbar 310 is less than 0.5mm, and the width of the first busbar 310 is less than 5mm.

In some embodiments, without reducing the conversion efficiency of the battery sheet 100, at least one auxiliary gate line 20 is provided for the first main gate line 310. By setting the auxiliary gate line 20 with the first main gate line 310, it is possible to Further reduce the amount of silver paste.

In some embodiments, the busbar 30 includes two opposite ends, the busbar 30 extends from one end of the silicon wafer 10 to the other end of the silicon wafer 10, and at least one end of the busbar 30 protrudes from the silicon wafer 10. . Wherein, at least one end of the main gate line 30 protrudes from the silicon wafer 10 , both ends of the main gate line 30 protrude from the silicon wafer 10 , or any end of the main gate line 30 protrudes from the silicon wafer 10 . Specifically, it may be set according to actual conditions, and no specific limitation is made here. By protruding the main gate line 30 from the silicon wafer 10, two adjacent battery slices 100 can be connected in series by using the protruding part, so that a plurality of battery slices 100 can be connected in series, which saves the assembly process and cost.

Wherein, the length of the portion 302 where the main gate line 30 protrudes from the silicon chip 10 is 5-200 mm.

It should be noted that the width of the busbars 30 on each cell 100 is different, so the number of busbars 30 on one cell 100 can be set according to the width of the busbars 30, wherein the busbars 30 The root number ranges from 5 to 50 roots.

In some embodiments, the busbar 30 includes a second busbar, the material of the second busbar is different from that of the first busbar, and the material of the second busbar is silver.

In the embodiment of the present application, taking the battery sheet 100 in which the busbar 30 is set as the first busbar 310 and the sub-barbar 20 is silver paste as an example, the process of making the battery sheet 100 in the screen process is as follows:

Prepare semi-finished solar cells that meet the requirements of the sub-grid to be printed, and then use silver paste with a silver content of more than 60-90% to print sub-grid lines 20 with a width of 15-50um on the back, and pass through a drying oven at 150-250°C for 30- The silver paste on the back is dried for 300 seconds, the flipper turns the cell 100 over, and the auxiliary grid lines 20 are printed with the silver paste containing more than 90% silver. For PERC and Topcon batteries, it needs to be sintered at a high temperature of 800°C, and for HJT batteries, it needs to be dried at 150-250°C for 30-300 seconds. Then place a required length of nickel-plated copper wire at the position where the main grid needs to be arranged, and brush it with conductive glue to adhere to the surface of the battery sheet 100, and then cure it at 150-250°C for 3-10 minutes to complete the production of the battery sheet 100.

The battery sheet 100 also includes: a first gate line layer 910 and a second gate line layer 920 arranged on both sides of the silicon chip, and each of the first gate line layer 910 and the second gate line layer 920 includes a plurality of main gate lines 30 and a plurality of A sub-gate line 20, a depletion layer 40, a first passivation layer 50, a second passivation layer 60 and a protective layer 70, wherein the depletion layer 40 is arranged on the front side of the silicon wafer 10, and is located between the silicon wafer 10 and the second between a gate line layer 910; the first passivation layer 50 is disposed on the side of the depletion layer 40 away from the silicon wafer 10, and is located between the depletion layer 40 and the first gate line layer 910; the second passivation layer 60 It is arranged on the back side of the silicon wafer 10, and is located between the silicon wafer 10 and the second gate line layer 920; the protective layer 70 is arranged on the side of the second passivation layer 60 away from the silicon wafer, and is located between the second passivation layer 60 and the second gate line layer 920. between the second gate line layers 920 .

Wherein, in some embodiments, the depletion layer 40 is a PN junction, the first passivation layer 50 is a silicon nitride layer, the second passivation layer 60 is an aluminum oxide layer, and the protection layer 70 is a silicon nitride layer.

In the embodiment of the present application, without reducing the conversion efficiency of the cell 100, nickel-plated copper wires are used to replace the silver paste used for printing on the front and back, while ensuring the reliability of the cell 100. It can be used in PERC, Topcon and HJT battery technologies, and can greatly To reduce silver consumption, taking the 182-size cell 100 as an example, the battery is expected to obtain a silver paste consumption of <50 mg/piece.

Please continue to refer to FIG. 6 , which is a schematic structural diagram of a solar cell module provided in an embodiment of the present application. The embodiment of the present application also provides a solar cell assembly 200, the solar cell assembly 200 includes a plurality of battery slices 100 as described above, and the plurality of battery slices 100 are arranged in series with each other.

The battery sheet and the solar battery module provided by the embodiments of the present application have been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application, and the descriptions of the above embodiments are only used to help understand the present application. At the same time, for those skilled in the art, based on the idea of this application, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the application.

Claims (10)

1. A battery sheet, characterized in that the battery sheet comprises: Silicon wafer; A plurality of busbar lines, the plurality of busbar lines are arranged on the silicon wafer at intervals; A plurality of sub-gate lines, the plurality of sub-gate lines are arranged on the silicon wafer at intervals, each of the sub-gate lines is connected to a main gate line, and the width of the sub-gate lines is smaller than that of the main gate line line width; Wherein, the main grid line includes at least one first main grid line, and the contact area between the first main grid line and the silicon wafer is smaller than the orthographic projection area of the first main grid line on the silicon wafer ;and / or The sub-gate line includes at least one first sub-gate line, and the contact area between the first sub-gate line and the silicon chip is smaller than the orthographic projection area of the first sub-gate line on the silicon chip. 2 . The battery sheet according to claim 1 , wherein the battery sheet includes conductive glue, and the first busbar is disposed on the silicon chip through the conductive glue. 3 . 3. The battery sheet according to claim 1, wherein the first main gate line includes two opposite ends, and the first main gate line extends from one end of the silicon wafer to the silicon wafer and at least one end of the first main gate line protrudes from the silicon chip so as to be connected to the first main gate line of another battery sheet. 4 . The battery sheet according to claim 3 , wherein the length of the first busbar protruding from the silicon chip ranges from 5 mm to 200 mm. 5 . The battery sheet according to claim 1 , wherein the first busbar comprises a conductive wire and a plating layer, and the plating layer is plated on a surface of the conductive wire. 6. The battery sheet according to claim 1, wherein at least one of the busbars comprises a plurality of first busbars and a plurality of connecting parts, and one connecting part is arranged between two phase Between the adjacent first main gate lines, the multiple first main gate lines are connected through the plurality of connecting parts, wherein the material of the connecting parts is a conductive material. 7. The battery sheet according to any one of claims 1-6, wherein the first busbar is one or a combination of copper wires, aluminum-platinum wires, or copper-aluminum wires. 8 . The battery sheet according to claim 1 , wherein the busbars include second busbars, and the material of the second busbars is different from that of the first busbars, so The material of the second busbar is silver. 9. The battery sheet according to claim 1, wherein the silicon sheet includes a front side and a back side oppositely arranged, and the battery sheet further comprises: The first gate line layer and the second gate line layer arranged on both sides of the silicon chip, each of the first gate line layer and the second gate line layer includes a plurality of the main gate lines and a plurality of the Auxiliary grid line; a depletion layer, the depletion layer is arranged on the front side of the silicon chip and is located between the silicon chip and the first gate line layer; a first passivation layer, the first passivation layer is disposed on the side of the depletion layer away from the silicon wafer, and is located between the depletion layer and the first gate line layer; a second passivation layer, the second passivation layer is disposed on the back side of the silicon chip, and is located between the silicon chip and the second gate line layer; A protection layer, the protection layer is disposed on a side of the second passivation layer away from the silicon wafer, and is located between the second passivation layer and the second gate line layer. 10. A solar cell assembly, characterized in that the solar cell assembly comprises a plurality of battery slices according to any one of claims 1-9, and the plurality of battery slices are arranged in series with each other.

Images