CN218632059U - Cell and solar cell module - Google Patents

Abstract

The embodiment of the application provides a battery piece and solar module, wherein, the battery piece includes: a silicon wafer; the main grid lines are arranged on the silicon chip at intervals; a plurality of secondary grid lines, wherein the secondary grid lines are arranged on the silicon wafer at intervals, each secondary grid line is connected with one main grid line, and the width of each secondary grid line is smaller than that of the main grid line; the main grid lines comprise at least one first main grid line, and the contact area of the first main grid line and the silicon chip is smaller than the orthographic projection area of the first main grid line on the silicon chip; and/or the auxiliary grid lines comprise at least one first auxiliary grid line, and the contact area of the first auxiliary grid line and the silicon chip is smaller than the orthographic projection area of the first auxiliary grid line on the silicon chip. According to the embodiment of the application, the contact area is reduced, the shielding of the light receiving area of the solar cell is reduced, and the photoelectric conversion efficiency is improved.

Description

Cell and solar cell module

Technical Field

The application relates to the field of solar cells, in particular to a cell and a solar cell module.

Background

With the exhaustion of world fossil energy, the alarm clock for knocking energy problems again in the event of Japan nuclear leakage undoubtedly becomes an important component of un-electrified electric energy, the application of crystalline silicon solar cell modules or thin-film solar cell panels becomes wider and wider, and the dependence of people on photovoltaic power generation becomes stronger and stronger.

However, the conventional solar cell has a problem of low photoelectric conversion efficiency.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a cell and a solar cell module, which can improve the condition that the photoelectric conversion efficiency of the existing solar cell is low.

The embodiment of the application provides a battery piece, the battery piece includes:

a silicon wafer;

the main grid lines are arranged on the silicon chip at intervals;

the plurality of auxiliary grid lines are arranged on the silicon wafer at intervals, each auxiliary grid line is connected with one main grid line, and the width of each auxiliary grid line is smaller than that of each main grid line;

the main grid lines comprise at least one first main grid line, and the contact area of the first main grid line and the silicon wafer is smaller than the orthographic projection area of the first main grid line on the silicon wafer; and/or

The auxiliary grid lines comprise at least one first auxiliary grid line, and the contact area of the first auxiliary grid line and the silicon chip is smaller than the forward projection area of the first auxiliary grid line on the silicon chip.

Optionally, the battery piece includes a conductive adhesive, and the first main gate line is disposed on the silicon wafer through the conductive adhesive.

Optionally, the first main gate line includes two opposite ends, the first main gate line extends from one end of the silicon wafer to the other end of the silicon wafer, and at least one end of the first main gate line protrudes out of the silicon wafer to be connected to the first main gate line of another battery piece.

Optionally, the length range of the first main gate line protruding the silicon wafer is 5mm to 200mm.

Optionally, the first main gate line includes a conductive wire and a plating layer, and the plating layer is plated on the surface of the conductive wire.

Optionally, at least one of the main gate lines includes a plurality of the first main gate lines and a plurality of connecting portions, one of the connecting portions is disposed between two adjacent first main gate lines, and the plurality of first main gate lines are connected by the plurality of connecting portions, where the connecting portions are made of a conductive material.

Optionally, the first main grid line is one or a combination of a copper wire, an aluminum platinum wire or a copper aluminum wire.

Optionally, the main gate line includes a second main gate line, the material of the second main gate line is different from the material of the first main gate line, and the material of the second main gate line is silver.

Optionally, the silicon wafer includes a front surface and a back surface that are oppositely disposed, and the battery piece further includes:

the first grid line layer and the second grid line layer are arranged on two sides of the silicon chip and respectively comprise a plurality of main grid lines and a plurality of auxiliary grid lines;

the depletion layer is arranged on the front side of the silicon wafer and is positioned between the silicon wafer and the first grid line layer;

the first passivation layer is arranged on one side, far away from the silicon chip, of the depletion layer and is positioned between the depletion layer and the first grid line layer;

the second passivation layer is arranged on the back surface of the silicon wafer and is positioned between the silicon wafer and the second grid line layer;

and the protective layer is arranged on one side of the second passivation layer, which is far away from the silicon wafer, and is positioned between the second passivation layer and the second grid line layer.

The embodiment of the application also provides a solar cell module, which comprises a plurality of the cell sheets, wherein the cell sheets are mutually connected in series.

The beneficial effect of this application lies in: the battery piece provided by the embodiment of the application comprises a silicon chip, a plurality of main grid lines and a plurality of auxiliary grid lines, wherein the plurality of main grid lines are arranged on the silicon chip at intervals, the plurality of auxiliary grid lines are arranged on the silicon chip at intervals, the width of each auxiliary grid line is smaller than that of one main grid line, each main grid line comprises at least one first main grid line, and the contact area of each first main grid line and the silicon chip is smaller than the orthographic projection area of each first main grid line on the silicon chip; and/or the secondary grid line comprises at least one first secondary grid line, and the contact area of the first secondary grid line and the silicon chip is smaller than the forward projection area of the first secondary grid line on the silicon chip. This application is less than the orthographic projection area on the silicon chip through the contact surface that sets up an at least first main grid line or an at least first vice grid line and silicon chip, under the electrically conductive circumstances of assurance, reduces area of contact, has reduced sheltering from solar cell photic area, has improved photoelectric conversion efficiency.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.

Fig. 1 is a schematic structural diagram of a battery cell provided in an embodiment of the present application.

Fig. 2 is a schematic cross-sectional view of the battery cell shown in fig. 1.

Fig. 3 is a schematic view of a first structure of a first main grid line in the battery cell shown in fig. 1.

Fig. 4 is a second structural schematic diagram of the first main grid line in the battery cell shown in fig. 1.

Fig. 5 is another schematic structural diagram of the bus bar in the battery cell shown in fig. 1.

Fig. 6 is a schematic structural diagram of a solar cell module according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Photovoltaic energy rapidly develops in nearly 10 years, the capacity of the photovoltaic energy is close to 500GW all over the world at present, and the photovoltaic energy is more and more popular due to the advantages of sustainable regeneration, no pollution, simple installation and the like. At present, PERC, topcon and HJT processes are 3 major mainstream processes of solar cells and account for more than 95% of photovoltaic cells. The final screen printing procedure in the 3 processes is performed by using silver paste with a silver content of about 90% through a screen printing mode, and is used for collecting current generated by the solar cell after illumination. Taking the HJT solar cell with 182 size as an example, the silver paste consumption is more than 200 mg/cell, which accounts for more than 20% of the cost of the solar cell.

In addition, the contact area between the grid line formed by printing silver paste and the silicon wafer is large, so that the shielding of the light receiving area of the solar cell is large, and the photoelectric conversion efficiency is low.

Therefore, in order to solve the above problems, the present application proposes a cell and a solar cell module. The present application will be further described with reference to the accompanying drawings and embodiments.

Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a battery cell according to an embodiment of the present disclosure, fig. 2 is a schematic cross-sectional diagram of the battery cell shown in fig. 1, and fig. 3 is a schematic structural diagram of a first main grid line in the battery cell shown in fig. 1. The embodiment of the application provides a battery piece 100, including silicon chip 10, many main grid lines 30 and many vice grid lines 20, wherein, silicon chip 10 is including relative front and the back that sets up, and many main grid lines 30 set up in the front and the back of silicon chip 10 at intervals each other, and many vice grid lines 20 set up in the front and the back of silicon chip 10 at intervals each other, and the width of vice grid line 20 is less than the width of main grid line 30. The main gate line 30 includes at least one first main gate line 310, and a contact area of the first main gate line 310 and the silicon wafer 10 is smaller than an orthographic projection area of the first main gate line 310 on the silicon wafer 10; and/or the secondary grid lines 20 comprise at least one first secondary grid line, and the contact area of the first secondary grid line and the silicon chip 10 is smaller than the forward projection area of the first secondary grid line on the silicon chip 10. The contact surface of the at least one first main grid line 310 or the at least one first auxiliary grid line and the silicon wafer is smaller than the forward projection area on the silicon wafer, so that the contact area is reduced under the condition of ensuring the electric conduction, the shielding of the light receiving area of the solar cell is reduced, and the photoelectric conversion efficiency is improved.

In some embodiments, the battery cell may be that the main grid lines 30 include at least one first main grid line 310, and the sub-grid lines 20 include at least one first sub-grid line. In some embodiments, the battery cell may also be that the main grid lines 30 include at least one first main grid line 310, and the sub-grid lines 20 do not include a first sub-grid line. In other embodiments, the cell sheet may also be that the main grid line 30 does not include the first main grid line 310, and the secondary grid line 20 includes at least one first secondary grid line, which is not specifically limited herein and is set according to practical situations.

In some embodiments, a plurality of main gate lines 30 are disposed in parallel with each other on the front and back sides of the silicon chip 10, a plurality of sub-gate lines 20 are disposed in parallel with each other, each sub-gate line 20 is disposed perpendicular to one main gate line 30, when a current is conducted, the sub-gate line 20 is used for collecting and transmitting the current to the main gate line 30, and the main gate line 30 transmits the current to other loads.

The battery piece 100 includes a conductive paste 80, and the first main gate line 310 is disposed on the silicon chip 10 through the conductive paste 80.

The main gate lines 30 include at least one first main gate line 310, which may be understood as a plurality of main gate lines 30 all including the first main gate line 310, or may be understood as a part of the plurality of main gate lines 30 including the first main gate line 310, or may be understood as only one main gate line 30 of the plurality of main gate lines 30 including the first main gate line 310. The specific configuration may be set according to actual conditions, and is not particularly limited herein.

The main gate lines 30 including the first main gate line 310 may be understood as one main gate line 30 composed of the first main gate line 310, may also be understood as one main gate line 30 composed of one first main gate line 310 and others, and may also be understood as one main gate line 30 having a portion composed of the first main gate line 310.

Illustratively, in some embodiments, at least one main gate line 30 is composed of the first main gate line 310, that is, the first main gate line 310 is used to replace silver paste printed in the prior art to form the main gate line 30, so that the contact area between the first main gate line 310 and the silicon wafer 10 can be reduced, the shading of the light receiving area of the solar cell is reduced, and the photoelectric conversion efficiency is improved. In addition, the silver paste consumption can be reduced, and the cost is reduced.

Further, since the first main grid line 310 may be oxidized in some practical applications, in order to avoid oxidation of the first main grid line 310, a metal material is plated on at least a portion of the first main grid line 310 to form a plated layer 320, so as to solve the problem of oxidation of the first main grid line 310. Specifically, with continued reference to fig. 3, a first bus bar 310 includes conductive wires 311 and a plating layer 312, and the plating layer 312 covers at least a portion of the conductive wires 311. That is, at least one of the plurality of bus bars 30 is composed of the first bus bar 310, and the metal material is plated on at least a portion of the conductive wire 311 to form a plated layer 312.

In the above, under the precondition that the first main grid line 310 is ensured to be resistant to oxidation, the metal material plated on at least a portion of the first main grid line 310 may be understood as a metal material coated on a portion of one first main grid line 310, and for example, in some embodiments, the first main grid line 310 includes a first portion 3111, a second portion 3112 and a third portion 3113 which are connected, where the first portion 3111 and the third portion 3113 are completely plated with the metal material, and the second portion 3112 is not plated with the metal material. For another example, referring to fig. 4, fig. 4 is a schematic diagram illustrating a second structure of the first main gate line in the battery cell shown in fig. 1. In other embodiments, the conductive wires 311 of the first bus bar 310 include an inner surface close to the silicon chip 10 and an outer surface far from the silicon chip 10, the outer surface of the conductive wires 311 is plated with a metal material to form a plated layer 312, and the inner surface of the conductive wires 311 is not plated with the metal material. Therefore, the first main grid line 310 can be prevented from being oxidized, and metal materials can be saved, so that the cost is reduced.

In some embodiments, all of the first bus bar 310 is coated with a metal material to ensure that the first bus bar 310 is not oxidized.

Referring to fig. 5, fig. 5 is a schematic view of another structure of the main gate line in the battery cell shown in fig. 1. In some embodiments, at least one of the bus bars 30 includes a plurality of first bus bars 310 and a plurality of connecting portions 330, the plurality of first bus bars 310 are disposed at intervals, each connecting portion 330 is disposed between two adjacent first bus bars 310, the two adjacent first bus bars 310 are connected by the connecting portions 330, and the plurality of first bus bars 310 are connected by the plurality of connecting portions 330. Through the arrangement of the plurality of first main grid lines 310 and the plurality of connecting parts 330, the length of each first main grid line 310 does not need to be the same as that of the main grid line 30, and the first main grid lines 310 can be connected through the connecting parts 330 even if being short, so that the first main grid lines 310 can be applicable even if the grid lines of each battery piece 100 are different in length, the waste of the first main grid lines 310 is reduced, and the cost can be saved. In addition, the length of the first main gate line 310 does not need to be set precisely, and the process difficulty is reduced.

The first main grid line 310 may be one or a combination of a copper wire, an aluminum platinum wire, or a copper aluminum wire. The material of the plating layer 312320 can be one or a combination of nickel, silver, tin, zinc, and the like. The plating layer 312 disposed on the first main grid line 310 may be one or a combination of a nickel-plated copper wire, a silver-plated copper wire, a tin-plated copper wire, or a zinc-plated copper wire. The specific configuration may be set according to practical situations, and is not limited specifically herein.

In some embodiments, the thickness of the first bus bar 310 is less than 0.5mm, and the width of the first bus bar 310 is less than 5mm.

In some embodiments, at least one sub-grid line 20 is disposed for the first main grid line 310 without reducing the conversion efficiency of the battery piece 100, and the silver paste usage can be further reduced by disposing the sub-grid line 20 with the first main grid line 310.

In some embodiments, the main gate line 30 includes two oppositely disposed ends, the main gate line 30 extends from one end of the silicon chip 10 to the other end of the silicon chip 10, and at least one end of the main gate line 30 protrudes from the silicon chip 10. The silicon chip 10 protruding from at least one end of the main gate line 30 may be the silicon chip 10 protruding from both ends of the main gate line 30, or the silicon chip 10 protruding from any end of the main gate line 30. The specific configuration may be set according to practical situations, and is not particularly limited herein. Through the arrangement that the main grid line 30 protrudes out of the silicon wafer 10, two adjacent battery pieces 100 can be connected in series by utilizing the protruding part, so that the battery pieces 100 are connected in series, and the assembly end process and the cost are saved.

Wherein, the length of the part 302 of the main grid line 30 protruding the silicon chip 10 is in the range of 5-200mm.

It should be noted that, the widths of the main grid lines 30 on each battery piece 100 are different, so the number of the main grid lines 30 arranged on one battery piece 100 can be set according to the widths of the main grid lines 30, where the number of the main grid lines 30 ranges from 5 to 50.

In some embodiments, the bus bar 30 includes a second bus bar, which is made of a different material than the first bus bar, and is made of silver.

In the embodiment of the application, the main gate line 30 is set as the first main gate line 310, and the sub-gate line 20 is the battery sheet 100 made of silver paste, which illustrates that the flow of the manufacturing process of the battery sheet 100 in the silk screen process is as follows:

preparing a semi-finished product of the solar cell meeting the requirement of the secondary grid to be printed, printing the secondary grid line 20 with the width of 15-50um on the back surface by using silver paste with the silver content of more than 60-90%, drying the back surface silver paste for 30-300 seconds by using a drying furnace at 150-250 ℃, turning 100 the cell by using a sheet turning machine, and printing the secondary grid line 20 by using the silver paste with the silver content of more than 90%. In the case of PERC and Topcon batteries, the batteries need to be sintered at a high temperature of 800 ℃, and in the case of HJT batteries, the batteries need to be dried at a temperature of 150-250 ℃ for 30-300 seconds. And then placing nickel-plated copper wires with required lengths at the positions where the main grids need to be arranged, brushing conductive adhesive to adhere the nickel-plated copper wires on the surface of the battery piece 100, and curing the nickel-plated copper wires for 3-10 minutes at the temperature of 150-250 ℃ to finish the manufacture of the battery piece 100.

The battery sheet 100 further includes: the first grid line layer 910 and the second grid line layer 920 are arranged on two sides of the silicon wafer, and each of the first grid line layer 910 and the second grid line layer 920 comprises a plurality of main grid lines 30 and a plurality of auxiliary grid lines 20, a depletion layer 40, a first passivation layer 50, a second passivation layer 60 and a protection layer 70, wherein the depletion layer 40 is arranged on the front side of the silicon wafer 10 and is positioned between the silicon wafer 10 and the first grid line layer 910; the first passivation layer 50 is arranged on one side of the depletion layer 40 far away from the silicon wafer 10 and is positioned between the depletion layer 40 and the first grid line layer 910; the second passivation layer 60 is disposed on the back surface of the silicon wafer 10 and between the silicon wafer 10 and the second gate line layer 920; the protective layer 70 is disposed on a side of the second passivation layer 60 away from the silicon wafer and between the second passivation layer 60 and the second gate line layer 920.

In some embodiments, the depletion layer 40 is a PN junction, the first passivation layer 50 is a silicon nitride layer, the second passivation layer 60 is an aluminum oxide layer, and the protection layer 70 is a silicon nitride layer.

Under the condition that does not reduce battery piece 100 conversion efficiency, the printing that uses nickel-plated copper line replacement front and back uses the silver thick liquid, guarantees battery piece 100 reliability simultaneously, can be used to PERC, topcon and HJT battery technique, can reduce silver consumption by a wide margin, takes 182 size battery pieces 100 as an example, and silver thick liquid consumption that this battery forecast can obtain < 50 mg/piece.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a solar cell module according to an embodiment of the present disclosure. The embodiment of the present application further provides a solar cell module 200, where the solar cell module 200 includes a plurality of the above-mentioned battery pieces 100, and the plurality of battery pieces 100 are mutually connected in series.

The cell and the solar cell module provided by the embodiment of the application are described in detail above. The principles and embodiments of the present application are described herein using specific examples, which are presented only to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A battery cell, comprising:

a silicon wafer;

the main grid lines are arranged on the silicon chip at intervals;

the plurality of auxiliary grid lines are arranged on the silicon wafer at intervals, each auxiliary grid line is connected with one main grid line, and the width of each auxiliary grid line is smaller than that of each main grid line;

the main grid lines comprise at least one first main grid line, and the contact area of the first main grid line and the silicon wafer is smaller than the orthographic projection area of the first main grid line on the silicon wafer; and/or

The auxiliary grid lines comprise at least one first auxiliary grid line, and the contact area of the first auxiliary grid line and the silicon chip is smaller than the forward projection area of the first auxiliary grid line on the silicon chip.

2. The battery piece of claim 1, wherein the battery piece comprises a conductive adhesive, and the first bus bar is arranged on the silicon chip through the conductive adhesive.

3. The cell of claim 1, wherein the first main grid line comprises two oppositely arranged ends, the first main grid line extends from one end of the silicon chip to the other end of the silicon chip, and at least one end of the first main grid line protrudes from the silicon chip to be connected with the first main grid line of another cell.

4. The battery piece as recited in claim 3, wherein the first main grid line protrudes beyond the silicon chip by a length ranging from 5mm to 200mm.

5. The battery piece of claim 1, wherein the first busbar line comprises conductive wires and a plating layer, and the plating layer is plated on the surfaces of the conductive wires.

6. The battery piece of claim 1, wherein at least one of the bus bars comprises a plurality of first bus bars and a plurality of connecting portions, one of the connecting portions is disposed between two adjacent first bus bars, and the plurality of first bus bars are connected by the plurality of connecting portions, and wherein the connecting portions are made of a conductive material.

7. The battery piece of any one of claims 1-6, wherein the first bus bar is one or a combination of copper wires, aluminum platinum wires or copper aluminum wires.

8. The battery piece of claim 1, wherein the main grid lines comprise second main grid lines, the material of the second main grid lines is different from that of the first main grid lines, and the material of the second main grid lines is silver.

9. The cell of claim 1, wherein the silicon wafer comprises a front side and a back side disposed opposite to each other, the cell further comprising:

the first grid line layer and the second grid line layer are arranged on two sides of the silicon chip and respectively comprise a plurality of main grid lines and a plurality of auxiliary grid lines;

the depletion layer is arranged on the front surface of the silicon wafer and is positioned between the silicon wafer and the first grid line layer;

the first passivation layer is arranged on one side, far away from the silicon chip, of the depletion layer and is positioned between the depletion layer and the first grid line layer;

the second passivation layer is arranged on the back surface of the silicon wafer and is positioned between the silicon wafer and the second grid line layer;

and the protective layer is arranged on one side of the second passivation layer, which is far away from the silicon wafer, and is positioned between the second passivation layer and the second grid line layer.

10. A solar cell module comprising a plurality of the cell segments defined in any one of claims 1-9, wherein the plurality of cell segments are arranged in series with one another.

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